CN207409480U - Array of capacitors, semiconductor devices - Google Patents
Array of capacitors, semiconductor devices Download PDFInfo
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- CN207409480U CN207409480U CN201721270885.2U CN201721270885U CN207409480U CN 207409480 U CN207409480 U CN 207409480U CN 201721270885 U CN201721270885 U CN 201721270885U CN 207409480 U CN207409480 U CN 207409480U
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- lower electrode
- supporting layer
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- 239000003990 capacitor Substances 0.000 title claims abstract description 164
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims description 57
- 238000003860 storage Methods 0.000 claims description 14
- 230000005611 electricity Effects 0.000 claims description 9
- 239000010410 layer Substances 0.000 description 450
- 239000000463 material Substances 0.000 description 98
- 238000000034 method Methods 0.000 description 68
- 238000005530 etching Methods 0.000 description 35
- 239000011241 protective layer Substances 0.000 description 34
- 230000008569 process Effects 0.000 description 20
- 239000003795 chemical substances by application Substances 0.000 description 18
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 230000007547 defect Effects 0.000 description 8
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 230000002093 peripheral effect Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 230000035755 proliferation Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 239000002356 single layer Substances 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
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- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
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- 238000000926 separation method Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
The utility model provides a kind of array of capacitors, semiconductor devices.The tubular structure of the lower electrode of the first supporting layer connection capacitor in array of capacitors, possesses preferable integrality since the first supporting layer can extend to the border of device region, tubular structure so as to the lower electrode to device region boundary can also play good supporting role, avoid the problem that the tubular structure run-off the straight of the lower electrode positioned at device region boundary or cave in.
Description
Technical field
The utility model is related to technical field of semiconductors, more particularly to a kind of array of capacitors and a kind of semiconductor devices.
Background technology
With the continuous development of semiconductor technology, to the performance requirement of capacitor in semiconductor integrated circuit also increasingly
Height, for example, it is desirable to which the capacitor formed in limited area can possess the capacitance of bigger.A solution is to lead to
Crossing increases the height of the lower electrode in capacitor, to increase lower contact area between electrode and capacitor dielectric layer, so that institute
The capacitor of formation has larger capacitance.
However, the increase with lower electrode height so that the depth-width ratio of lower electrode also increases accordingly, and then easily causes
The problem of lower electrode bending is deformed or collapsed.For this purpose, supporting layer can be formed on the side wall of the lower electrode, with to the lower electricity
Pole is supported, so as to avoid the problem that lower electrode occurs bending and deformation or collapses.
Wherein, supporting layer may be formed at the side wall of lower electrode on the position of intermediate region.Specifically, lower electrode and branch
The forming method of support layer generally includes：
With reference first to a substrate 100 shown in Figure 1A, is provided, being defined on the substrate 100 has one for forming capacitor
The device region 100A and external zones 100B positioned at device region 100A peripheries；
With continued reference to shown in Figure 1A, sequentially forming one first sacrificial layer 111, one first layer of support material 121 and one second
Sacrificial layer 112 is on the substrate 100；
Run through second sacrificial layer 112, the first layer of support material 121 and first referring next to shown in Figure 1B, forming one
The through hole of sacrificial layer 111 in the device region 100A, and formed electrode 140 in the bottom and side wall of the through hole；
Referring next to shown in Fig. 1 C, second sacrificial layer 112 is removed；However, due to 121 middle position of the first layer of support material
Area in the part of device region 100A peripheries is larger, so that the part also has more film defects accordingly.
During removing second sacrificial layer 112, the film defects can be further formed broken hole 121a, thus, etch
Agent can enter 121 lower section of the first layer of support material, and etch the first sacrificial layer 110.
Therefore, in the preparation process of traditional supporting layer, since the first sacrificial layer of part 111 can be etched away in advance, lead
The first layer of support material is caused to generate sheet to start, and then makes the pattern for the supporting layer being ultimately formed abnormal, even results in part
The problem of supporting layer comes off especially can not usually form complete supporting layer positioned at device region 100A boundaries.
Utility model content
The purpose of this utility model is to provide a kind of array of capacitors, the supporting layer of the array of capacitors possesses preferably
Integrality.
Array of capacitors provided by the utility model, including：
There is one substrate a device region for being formed with capacitor and one to be located at the external zones of device region periphery；
Electrode once is arranged on the device region of the substrate, and the lower electrode has multiple tubular structures；
One first supporting layer, is formed on the device region of the substrate, and first supporting layer connects the lower electricity
Multiple tubular structures of pole, and extend to the border of the device region；
One capacitor dielectric layer is formed on the surfaces externally and internally of the lower electrode；
One top electrode is formed in the surface of the capacitor dielectric layer, by institute corresponding to the surfaces externally and internally of the lower electrode
It states top electrode, the capacitor dielectric layer and the lower electrode and forms capacitance.
Optionally, the array of capacitors further includes：One protection ring, the external zones positioned at the substrate is along described
On the region of device region.
Optionally, the array of capacitors further includes：One second supporting layer, with interval on first supporting layer
And the tubular structure of the lower electrode is connected, second supporting layer extends to the border of the device region, and described
Two supporting layers and first supporting layer are at various height on position.
Optionally, the array of capacitors further includes：One the 3rd supporting layer is arranged on second supporting layer and is located at
The top of the lower electrode, and a port is formed in the 3rd supporting layer, it is corresponding in the height projection area of the port
A part for the top port of the tubular structure of the lower electrode.
Optionally, in the tubular structure of the lower electrode, the height of the corresponding cylinder side wall in the port is less than
The height of the cylinder side wall in the port is not corresponded to, so that tubular structure cylinder when covered with three supporting layer
The size of interconnected connected entrance increases outside internal and cylinder.
Optionally, multiple lower electrodes are formed on the substrate, do not correspond to the portion of the port in the 3rd supporting layer
Point be linked to each other to form an entirety, the 3rd supporting layer, second supporting layer and first supporting layer with it is more
A tubular structure connection, to be supported to multiple tubular structure poles.
The another object of the utility model is, provides a kind of semiconductor devices, including：
One substrate, have one be formed with capacitor device region and one be located at device region periphery external zones, and
A node contact is also formed in the device region on the substrate, the node contact is electrically connected with the capacitor；
Electrode once is arranged on the device region of the substrate and is electrically connected with the node contact, and described
Lower electrode has a tubular structure；
One supporting layer is formed on the device region of the substrate, and the supporting layer connects the described of the lower electrode
Tubular structure, and extend to the border of the device region；
One capacitor dielectric layer is formed on the surfaces externally and internally of the lower electrode；And
One top electrode is formed in corresponding to the surfaces externally and internally of the lower electrode on the surface of the capacitor dielectric layer, by
The top electrode, the capacitor dielectric layer and the lower electrode form capacitance.
Optionally, a storage unit is also formed with over the substrate, and the storage unit and the node contact are electrical
Connection.
Optionally, multiple capacitors are formed with over the substrate, and multiple lower electrodes of multiple capacitors are equal
It is connected with same supporting layer.
In capacitor provided by the utility model, even if still having positioned at the part on device region border in the first supporting layer
Standby preferable shape, so that being formed in the lower electrode on device region border can also be supported, and avoids that lower electrode pattern occurs
Exception or the problem of cave in.
Description of the drawings
Figure 1A~1C is a kind of structure diagram of capacitor in its preparation process；
Fig. 2 is the flow diagram of the forming method of the array of capacitors in the utility model embodiment one；
Fig. 3 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S110 processes at it
In top view；
Fig. 3 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 3 A performs step at it
Along the diagrammatic cross-section on aa ' directions during rapid S110；
Fig. 4 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S120 processes at it
In top view；
Fig. 4 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 4 A performs step at it
Along the diagrammatic cross-section on aa ' directions during rapid S120；
Fig. 5 A are the forming method of the array of capacitors in the utility model embodiment one when it performs step S130
Top view；
Fig. 5 B~5C are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 5 A is held at it
Along the diagrammatic cross-section on aa ' directions during row step S130；
Fig. 6 A are the forming method of the array of capacitors in the utility model embodiment one when it performs step S140
Top view；
Fig. 6 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 6 A performs step at it
Along the diagrammatic cross-section on aa ' directions during rapid S140；
Fig. 7 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S150 processes at it
In top view；
Fig. 7 B~Fig. 7 C are the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 7 A at it
Step S150 is performed in the process along the diagrammatic cross-section on aa ' directions；
Fig. 8 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S160 processes at it
In top view；
Fig. 8 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 8 A performs step at it
Along the diagrammatic cross-section on aa ' directions during rapid S160；
Fig. 9 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S170 processes at it
In top view；
Fig. 9 B~9C are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 9 A is held at it
Along the diagrammatic cross-section on aa ' directions during row step S170；
Figure 10 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S180 processes at it
In top view；
Figure 10 B~10C are respectively the forming method of the array of capacitors in the utility model embodiment one shown in Figure 10 A
Along the diagrammatic cross-section on aa ' directions during it performs step S180；
Figure 11 A are the top view of the array of capacitors in the utility model embodiment two；
Figure 11 B are array of capacitors in the utility model embodiment two shown in Figure 11 A along the section on aa ' directions
Schematic diagram；
Figure 12 A are the distribution schematic diagram of the capacitor in semiconductor device array in the utility model embodiment three；
Figure 12 B are the structure diagram corresponded in the semiconductor devices shown in Figure 12 A on aa ' directions；
Wherein, reference numeral is as follows：
100/200/300- substrates；100A/200A/300A- device regions；
100B/200B/300B- external zones；111/211- the first sacrificial layer；
The inner circle of the first sacrificial layers of 211A-；The outer part of the first sacrificial layers of 211B-；
112/212- the second sacrificial layer；121/221- the first layer of support material；
121a/221a- broken holes；Electrode under 140-；
The first supporting layers of 220a/320a-；The second layer of support material of 222-；
The second supporting layers of 220b/320b-；The 3rd layer of support material of 223-；
The 3rd supporting layers of 220c/320c-；230- protective layers；
240- through holes；Electrode under 250/350-；
250a- top ports；250b- connected entrances；
260- mask layers；260a- is open；
270/370- capacitor dielectric layers；280/380- top electrodes；
281/381- the first conductive layer；282/382- the second conductive layer；
290/390- capacitances；201/301- node contacts；
302- bit line contacts；410- memory active regions；
411- bit line contacts area；412- storage node contacts area；
413- gate structures；420- isolation structures；
430- peripheral circuit active areas.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to the utility model proposes array of capacitors, semiconductor devices makees into one
Step is described in detail.According to following explanation, will be become apparent from feature the advantages of the utility model.It should be noted that attached drawing uses
Very simplified form and using non-accurate ratio, only to it is convenient, lucidly aid in illustrating the utility model embodiment
Purpose.
Embodiment one
The array of capacitors in the utility model is described in detail in forming method in the present embodiment with reference to capacitor.
Fig. 2 is the flow diagram of the forming method of the array of capacitors in the utility model embodiment one, such as Fig. 2 institutes
Show, a kind of implementation of the forming method of array of capacitors provided by the utility model includes：
Step S110 provides a substrate, has one to be located at institute for forming the device region of capacitor and one on the substrate
The external zones of device region periphery is stated, is formed with one first sacrificial layer and one first layer of support material over the substrate；
Step S120, an embedded protective layer correspond to area of the external zones along the device region in first sacrificial layer
In domain, the protective layer separation first sacrificial layer is an outer part and one on the external zones on the device region
Inner circle；
Step S130 forms one second sacrificial layer over the substrate, and forms multiple through holes on the device region, institute
Through hole is stated through second sacrificial layer, first layer of support material and first sacrificial layer；
Step S140 forms electrode and in the through hole, the bottom and side of the through hole is covered in the lower electrode
The part of wall forms multiple tubular structures；
Step S150 forms one the 3rd supporting layer at the top of the lower electrode；
Step S160 removes second sacrificial layer, to expose the surface in first layer of support material,
During second sacrificial layer is removed, by the isolation of the protective layer, the inner circle of first sacrificial layer
Intactly to connect multiple tubular structures of the lower electrode；
Step S170 etches first layer of support material, to be formed as first of the correspondence covering device region
Layer is supportted, first supporting layer connects multiple tubular structures of the lower electrode, and first supporting layer extends to institute
State the border of device region and removal first sacrificial layer；
Step S180 sequentially forms a capacitor dielectric layer and a top electrode on the surfaces externally and internally of the lower electrode, by institute
It states top electrode, the capacitor dielectric layer and the lower electrode and forms capacitance.
With reference to the corresponding structure diagram of each step, array of capacitors in the present embodiment is further explained
Forming method.
Fig. 3 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S110 processes at it
In top view；Fig. 3 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 3 A is performed at it
Along the diagrammatic cross-section on aa ' directions during step S110.
In step s 110, with specific reference to a substrate 200 shown in Fig. 3 A and Fig. 3 B, is provided, have one on the substrate 200
For forming the external zones 200B that the device region 200A and one of capacitor is located at the device region 200A peripheries, in the substrate
One first sacrificial layer 211 and one first layer of support material 221 are formed on 200.
Wherein, the first layer of support material 221 is used to form the first supporting layer subsequently formed, first sacrificial layer
211 thickness definition goes out the height of the first supporting layer subsequently formed, and therefore, the thickness of first sacrificial layer 211 can root
It is adjusted according to the height and position for the first supporting layer that need to be formed.Further, first layer of support material 221 can utilize heavy
Product technique forms (for example, chemical vapor deposition method).In addition, during the first layer of support material 221 is formed, usually can
Film defects are generated in the first layer of support material formed, it is easily rotten when the film defects are in the etching agent
Erosion, so as to which broken hole can be formed in the first layer of support material.
Fig. 4 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S120 processes at it
In top view；Fig. 4 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 4 A is performed at it
Along the diagrammatic cross-section on aa ' directions during step S120.
In the step s 120, with specific reference to shown in Fig. 4 A and Fig. 4 B, an embedded protective layer 230 is in first sacrificial layer
211 correspond to the external zones 200B along in the region of the device region 200A, and the protective layer 230 separates described first and sacrifices
Layer 211 is the peripheral 211B portions on the external zones 200B and an inner circle 211A on the device region 200A.
Need to illustrate it must is that part of devices area 200A and external zones 200B are illustrated only in Fig. 4 A, therefore illustrates only device
Protective layer 230 on the one side of area 200A.It should be appreciated, however, that the protective layer 230 can be along the whole of device region 200A
A border is arranged in the periphery of device region 200A.That is, protective layer 230 is formed in the periphery of device region 200A, so as to utilize
It states protective layer 230 and is used as an isolation barrier, the etching agent avoided enter into external zones 200B enters device region 200A in advance
In, so as to the part for preventing inner circle 211A in the first sacrificial layer 211 is removed in advance and to the complete of the first layer of support material
Property impact so that in the first supporting layer formed positioned at device region 200A borders part still have preferable shape
Looks.
Preferably, suitable material can be used and form protective layer, so as to protective layer 230 and to the first sacrificial layer 211
Etching selection it is bigger, so as to be located in the part of external zones 200B when the first layer of support material 221 and have broken hole and lead
When the broken hole of etching agent from the first layer of support material 221 being caused to enter and etch the part of outer part 211B in the first sacrificial layer 211,
Since etching agent is very small to the etch rate of protective layer 230, so as to which etching agent will not be under 230 barrier effect of protective layer
One step is diffused in device region 200A, and then the part of inner circle 211A in the first sacrificial layer 211 can be avoided not gone in advance
It removes, it is advantageously ensured that the pattern of the first supporting layer subsequently formed.Wherein, to protective layer 230 and to the first sacrificial layer 211
Etching selection ratio can be more than or equal to 1:10, it is chosen as 1:10~1:10000.For example, when first sacrificial layer 211 is oxygen
During SiClx layer, silicon nitride layer can be used in the protective layer 230.
In optional scheme, the protective layer 230 can formed the first sacrificial layer 211 and the first layer of support material 221 it
After formed, specifically：After the first sacrifice 210 and the first layer of support material 221 is formed, it is sacrificial through described first to form one
The groove of domestic animal layer 211 and the first layer of support material 221, the groove are located at external zones 200B and close to the regions of device region 200A
In, i.e. the groove is located at the periphery of device region 200A；Then, the material of protective layer is filled in the groove, and can be combined
Flatening process removes the protective layer material at 221 top of the first layer of support material, so as to form protective layer in the grooves
230.In this way, formed protective layer 230 can be made to extend not only through first sacrificial layer 211 also, make the surface of protective layer 230
Higher than the surface of the first sacrificial layer 211, be conducive to improve barrier effect of the protective layer 230 to etching agent.
Certainly, the protective layer also can be after the first sacrificial layer 211 be formed, and is forming the first layer of support material 221
It is formed before, the protective layer flushed with first sacrificial layer 211 can be formed at this time and the first layer of support material 221 is covered
The first sacrificial layer of lid 211 and protective layer.
In addition, a node contact 201 is also formed in the substrate 200, the node contact 201 and follow-up institute's shape
Into capacitor lower electrode be electrically connected.
Fig. 5 A are the forming method of the array of capacitors in the utility model embodiment one when it performs step S130
Top view；Fig. 5 B~5C are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 5 A is performed at it
Along the diagrammatic cross-section on aa ' directions during step S130.
In step s 130, with specific reference to shown in Fig. 5 A~5C, one second sacrificial layer 212 of formation is in first fid
On the bed of material 221, and multiple through holes 240 are formed on the device region 200A, the through hole 240 runs through second sacrificial layer
212nd, first layer of support material 221 and first sacrificial layer 211.
It is understood that 211 institute of second sacrificial layer 212, the first layer of support material 221 and first sacrificial layer
The lamination of composition can provide a formation substrate to be subsequently formed lower electrode.It is specifically, described logical by being formed in the lamination
Hole 240, so as to form the lower electrode with a tubular structure by the bottom and side wall of the through hole 240.Therefore, formed
The total height for having the lamination of the through hole 240 can define the height of tubular structure in the lower electrode subsequently formed, so as to
By the height for the capacitor that the first sacrificial layer 211 of increase and the thickness of the second sacrificial layer 212, increase are subsequently formed, thus
The electrode surface area of capacitor can be increased, thus, you can further improve the capacitance of formed capacitor.
Emphasis is with reference to shown in figure 5B, in the present embodiment, after the second sacrificial layer 212 is formed, can also continue to form one
On second sacrificial layer 212, second layer of support material 222 is used to form the second supporting layer two layer of support material 222,
To be supported to the capacitor formed.In the present embodiment, 222 and second sacrificial layer 212 of the second layer of support material,
One layer of support material 221 and first sacrificial layer 211 collectively form to form the substrate of lower electrode, therefore, are being formed
In the step of through hole 240, the through hole 240 more runs through second layer of support material 222.That is, described through hole 240 runs through
Second layer of support material 222, the second sacrificial layer 212, the first layer of support material 221 and the first sacrificial layer 211.Wherein, described
One layer of support material 221 and second layer of support material 222 can be used same material and formed, such as can be silicon nitride
Layer.And second sacrificial layer 212 and first sacrificial layer 211 can also be used identical material and formed, such as can be
Silicon oxide layer.
Fig. 6 A are the forming method of the array of capacitors in the utility model embodiment one when it performs step S140
Top view；Fig. 6 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 6 A performs step at it
Along the diagrammatic cross-section on aa ' directions during S140.
In step S140, electrode 250 is in the through hole 240 with specific reference to shown in Fig. 6 A and Fig. 6 B, being formed, institute
The bottom and side wall that lower electrode 250 covers the through hole 240 is stated, to form multiple tubular structures.
That is, the part being located in the lower electrode 250 formed in the through hole 240, the shape of pattern and the through hole 240
Looks are coincide, so that the part being located in the lower electrode 250 in the through hole 240 forms a tubular structure, wherein, under described
It is located at the inner surface inside cylinder in the tubular structure of electrode 250 away from first sacrificial layer 211, the lower electrode 250
The tubular structure in be located at outer surface outside cylinder close to first sacrificial layer 211 and, lead in the tubular structure
It crosses inside top port 250a connecting cylinders and outside cylinder.Further, the lower electrode 260 can be polysilicon electrode, also may be used
Think metal electrode.Instantly when electrode is metal electrode, such as titanium nitride (TiN) formation may be employed.
Specifically, the lower electrode 250 can be formed on the basis of depositing operation with reference to flatening process.Specifically, institute
State the forming method of lower electrode 250 for example including：First, an electrode material layer is formed on the substrate 200, the electrode material
The bed of material covers the bottom and side wall of the through hole 240 and covering second layer of support material 222；Then, planarization is performed
Technique (for example, chemical mechanical milling tech) removes the part for being located at 222 top of the second layer of support material in electrode material layer,
So that remaining electrode material layer is made only in through hole 240, to form the lower electrode of a tubular structure.
In addition, in the present embodiment, node contact 201 is also formed in substrate 200, the node contact 201 passes through institute
It states through hole 240 to expose, so that the bottom of the tubular structure of the lower electrode 250 formed can be with the node contact 201
It is electrically connected.
In the present embodiment, by forming two supporting layers on the side wall of the tubular structure of lower electrode 250, to strengthen under
The support strength of electrode.It should be appreciated, however, that can also supporting layer be adjusted according to actual state accordingly in other embodiments
Height and increase supporting layer quantity.
Fig. 7 A are the forming method of the array of capacitors in the utility model embodiment one when it performs step S150
Top view；Fig. 7 B~7C are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 7 A is performed at it
Along the diagrammatic cross-section on aa ' directions during step S150.
It, can also be under in addition to being formed with supporting layer on the side wall in the tubular structure of lower electrode 250 in the present embodiment
The top of electrode 250 sets a supporting layer, further to strengthen the support force to lower electrode 250.
That is, it is specific to join shown in Fig. 7 A~7C in step S150, in the array of capacitors of the present embodiment, also form one the 3rd
Supporting layer 220c is at the top of the lower electrode 250.Wherein, the 3rd supporting layer 220c can utilize depositing operation, photoetching work
Skill and etching technics are formed.It should be noted that depositing operation is being utilized to be formed for the material of the 3rd supporting layer 220c of composition
During layer, since the size of the top port 250a of tubular structure is smaller, it can make to be formed in lower electricity by controlling film-forming process
The material layer at the top of the tubular structure of pole 250 will not be filled into the tubular structure.
In the present embodiment, using the photoetching process with along with, while the 3rd supporting layer 220c and the second supporting layer are defined
The figure of 220b.Specifically, the forming method of the 3rd supporting layer 220c and the second supporting layer 220b comprises the following steps.
First step with reference to shown in figure 7B, forms one the 3rd layer of support material 223 in second layer of support material 222
On, the 3rd layer of support material 223 covers the top port 250a of the lower electrode 250, and as described above, passes through control the
The film-forming process of three layer of support material can make the 3rd layer of support material 223 be not filled with the cylinder in the lower electrode 250
In the cylinder inside of shape structure.
Second step with continued reference to shown in Fig. 7 B, forms the device region of the mask layer 260 on the substrate 200
In 200A, at least one opening 260a is formed in the mask layer 260, the height projection area of the opening 260a is locally overlapped
The top port 250a of the tubular structure of the lower electrode 250.
That is, the atop part port 250a of tubular structure is corresponded in the opening 260a of mask layer 260, therefore, is being utilized
Mask layer 260 for the 3rd layer of support material 223 of mask etching with formed the 3rd supporting layer 220c after, the part top port
250a can be exposed by the 3rd supporting layer 220c, so that with being connected outside cylinder inside cylinder, in this way, can ensure that tubular knot
It can be exposed inside the cylinder of structure, in favor of forming capacitor dielectric layer and top electrode subsequently on the inner surface inside cylinder.
In addition, the top end of adjacent multiple tubular structures can be corresponding in the same opening 260a of the mask layer
Mouth 250a, i.e., the top port 250a of adjacent multiple tubular structures can be exposed by same opening.With multiple tubular structures
It is corresponding, can make to be formed with multiple opening 260a in the mask layer 250, and make it is same opening 260a in be corresponding with it is adjacent extremely
The top port 250a of few two lower electrodes, thus, the opening size on mask layer 260 on the one hand be added, so as to have
Beneficial to simplified technique；On the other hand, by opening up opening on mask layer by layer 260, the portion of non-corresponding opening in mask layer 260 is made
Divide an entirety for remaining as interconnection, be also in the 3rd supporting layer defined using the mask layer 260 as a result,
One entirety, i.e. the 3rd supporting layer connects the top of multiple tubular structures, to be supported to multiple tubular structures.Also, this
In embodiment, the mask layer 260 is also simultaneously for defining the image of the second supporting layer, therefore, the second support of the formation
Layer is also an entirety, to connect the cylinder side wall of the tubular structure of multiple lower electrodes 250.In the present embodiment, adjacent four cylinders
The top port 250a of shape structure is corresponded in same opening 260a, therefore, it is being performed etching to the 3rd layer of support material
Afterwards, the atop part port 250a of four adjacent tubular structures is exposed simultaneously by same opening 260a.
Third step, with reference to shown in figure 7C, with the mask layer 260 for the 3rd layer of support material 223 described in mask etching,
To form corresponding the 3rd supporting layer 220c for covering the device region 200A, it is formed in the 3rd supporting layer 220c pair
The port of the opening 260a is answered, the top of the tubular structure of the lower electrode 250 is exposed by the port
A part of port 250a.
In the present embodiment, multiple tubular structures, and the same opening 260a of the mask layer are formed on the substrate 200
In be corresponding with the top port 250a of adjacent multiple tubular structures, therefore, in the 3rd support formed in 220c
Multiple ports are formed with accordingly, and the top port of adjacent multiple tubular structures can be exposed in same port
250a。
As seen in figure 7 c, the figure of the second supporting layer 220b can also be defined simultaneously by the mask layer 260,
Therefore, after with the mask layer 260 for the 3rd layer of support material of mask etching, the second fid to exposing is also continued to
The bed of material 222 performs etching, to form the second supporting layer 220b.The second supporting layer 220b's and the 3rd supporting layer 220c
Partial graphical corresponds.Wherein described second supporting layer 220b is formed on the cylinder side wall of tubular structure, and the second supporting layer
The figure of part of the figure of 220b with not corresponding to top port 250a in the 3rd supporting layer 220c is corresponding, i.e. described
Second supporting layer 220b is contacted with the side wall of the tubular structure, and is extended along the direction away from the tubular structure.
It is understood that top port 250a is not corresponded in the figure and the 3rd supporting layer 220c of the second supporting layer 220b
Part figure, do not correspond to accordingly it is described opening 260a height projection area in.That is, the second layer of support material
In the part contacted in 222 with the tubular structure of lower electrode 250, the corresponding throwing in the opening 260a in the height direction in part
In the domain of shadow zone, thus, be mask etching the second layer of support material 222 and the 3rd fid using the mask layer 260
During the bed of material 223, you can part retains the part contacted in the second layer of support material 222 with lower electrode 250, to form second
Support layer 220b and part retain the part for the side wall that tubular structure is corresponded in the 3rd layer of support material 223, to form the 3rd
Support layer 220c.
Therefore, the 3rd layer of support material 223 and second exposed is sequentially etched for mask using the mask layer 260
Layer of support material 222, with formed the 3rd supporting layer 220c and the second supporting layer 220b when, as shown in Figure 5 C, the second supporting layer
220b be located at the tubular structure of lower electrode 250 close to top cylinder side wall on, so as on side wall to lower electrode 250 into
Row support；3rd supporting layer 220c is located at the top of lower electrode 250, and the 3rd supporting layer 220c exposes atop part
Port 250a.
Four steps, emphasis is referred to reference to figure 7C shown in, in preferred scheme, formation the 3rd supporting layer 220c it
Afterwards, exposed lower electrode 250 can also further be etched, i.e. partly remove in the tubular structure from the 3rd supporting layer
The cylinder side wall exposed in the port of 220c, to reduce what is exposed in the tubular structure from the port of the 3rd supporting layer
Cylinder side wall height so that in the tubular structure when covered with the 3rd supporting layer 220c cylinder inside and cylinder outside phase
The size of intercommunicated connected entrance 250b increases.Wherein, the mask layer 260 can be continued with as lower electrode described in mask etching
250, certainly, also can remove the mask layer 260 and directly using the 3rd supporting layer 220c as mask etching under electrode.
In subsequent technique, formed capacitor dielectric layer and top electrode need to be made by the connected entrance 250b, it can
The inner surface inside the cylinder of tubular structure is covered simultaneously.Therefore, by connected entrance 250b, be on the one hand conducive to capacitor dielectric layer and
Top electrode is covered in cylinder inside, on the other hand can also avoid causing in the company of being formed in due to the undersized of connected entrance 250b
The completely plugged connected entrance 250b of capacitor dielectric layer on port 250b, therefore, by expanding the size of connected entrance 250b, can prevent
Connected entrance 250b generating bottle neck dams, and then ensure that the top electrode subsequently formed can be filled into the cylinder of the tubular structure
In portion.
Fig. 8 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S160 processes at it
In top view；Fig. 8 B are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 8 A is performed at it
Along the diagrammatic cross-section on aa ' directions during step S160.
In step S160, with specific reference to shown in Fig. 8 A and Fig. 8 B, second sacrificial layer 212 is removed, to expose
Surface of the lower electrode 250 in first layer of support material 221 is stated, during second sacrificial layer 212 is removed, by
By the isolation of the protective layer 230, the inner circle 211A of first sacrificial layer 211 for intactly connect it is described under
Multiple tubular structures of electrode 250.
After the 3rd layer of support material and the second layer of support material are etched using mask layer 260, you can expose described
Second sacrificial layer 212, so as to be performed etching using etching agent to the second sacrificial layer 212.At this point, the etching agent can be carved directly
Lose the second sacrificial layer 212 for exposing and the etching agent can also horizontal proliferation, with further laterally etched second supporting layer
The second sacrificial layer 212 below 220b, and expose first layer of support material 221.Specifically, the etching agent can
By external zones 200B horizontal proliferation into device region 200A, with to the portion being located in the second sacrificial layer 212 in device region 200A
Divide and perform etching, can also be entered by the opening portion of the 3rd supporting layer 220c and etch the second sacrificial layer 212.
As shown in Figure 8 A and 8 B, after second sacrificial layer is removed, first layer of support material 221 exposes
Go out, as noted previously, as the film forming characteristics of the first layer of support material 221, causes in the first formed layer of support material 221 often
Film defects can often be generated.During due to the electrode 250 under preparation, 221 middle position of the first layer of support material is partly eliminated
Part in device region 200A, the film so as to make the part in the first layer of support material 221 positioned at device region 200A lack
It falls into and greatly reduces, however, but substantial amounts of thin there are still having in the part of external zones 200B in the first layer of support material 221
Film defect.Therefore, when removing the second sacrificial layer 212 using etching agent, since first layer of support material 221 is exposed
Go out, so as to easily cause the film defects in the first layer of support material of etchant 221, and then in the first layer of support material
Broken hole 221a is formed in 221.That is, in the part of external zones 200B, film defects are highly prone to the first layer of support material 221
The erosion of etching agent and generate broken hole 221a.When the first layer of support material 221 is formed with broken hole in the part of external zones 200B
During 221a, then etching agent can be entered by the broken hole to the first sacrificial layer 211, and then can be in advance to the first sacrificial layer 211
In be located at external zones 200B in part perform etching, yet with the presence of protective layer 230, effectively prevent etching agent into one
Horizontal proliferation is walked into device region 200A, so that the inner circle 211A of first sacrificial layer 211 is intactly to connect
Multiple tubular structures of the lower electrode 250, and then avoid and be located at device region in the first layer of support material 221
The part of 200A is affected, and especially can ensure that the portion for being located at device region 200A borders in the first supporting layer subsequently formed
The integrality divided.
Fig. 9 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S170 processes at it
In top view；Fig. 9 B and Fig. 9 C are that the forming method of the array of capacitors in the utility model embodiment one shown in Fig. 9 A exists
It performs step S170 in the process along the diagrammatic cross-section on aa ' directions.
In step S170, with specific reference to shown in Fig. 9 A~9C, first layer of support material 221 is etched, to be formed as
One corresponds to the first supporting layer 220a for covering the device region 200A, the first supporting layer 220a connections lower electrode 250
Multiple tubular structures, and the first supporting layer 220a extends to the border of the device region 200A.
With specific reference to shown in Fig. 9 B, the side wall in the first layer of support material with the tubular structure of the lower electrode 250 contacts
Part partly retained, to form the first supporting layer 220a, for being supported on the side wall of tubular structure to lower electrode.
Also, before the first layer of support material is etched, the first sacrificial layer 211 below does not have under the barrier effect of protective layer 230
It is removed, ensures that the integrality of the first formed supporting layer 220a, enable the first formed supporting layer 220a
Enough extend to the boundary position of device region 200A.
Wherein, when forming the first supporting layer 220a, when first layer of support material and the 3rd layer of support material
When possessing larger etching selection ratio, then first fid can be etched directly using the 3rd supporting layer 220c as mask
The bed of material is to form the first supporting layer 220a；Alternatively, when first layer of support material and the etching of the 3rd layer of support material
It is when selecting smaller or even when first layer of support material is identical with the material of the 3rd layer of support material, then available
Technique is etched back to, first layer of support material is etched to form the first supporting layer 220a, although at this point, portion can be consumed
Divide the 3rd supporting layer 220c, the 3rd supporting layer smaller yet with the thickness of the first supporting layer 220a, therefore consuming
220c can't have an impact its support effect.
In addition, as shown in Figure 9 B, by being etched back to technique by mask or utilization of the 3rd supporting layer 220c, the two
The figure of the first supporting layer 220a formed with the figure for the part for not corresponding to top port in the 3rd supporting layer 220c
Shape is corresponding.That is, the figure of the first supporting layer 220a is similar with the figure of the second supporting layer 220b.The present embodiment
In, multiple lower electrodes 250 are formed on substrate, and multiple lower electrodes 250 are contacted with the 3rd supporting layer 220c, phase
It answers, the first supporting layer 220a is also an entirety, and contacted with multiple lower electrodes 250, so as to multiple institutes
Lower electrode 250 is stated to be supported.
Further, the protective layer 230 can be used the material identical with the first layer of support material material and be formed, from
And when etching first layer of support material to form the first supporting layer 220a, can partly consume protective layer 230 or
All consume the protective layer 230.It is of course also possible to removing the first sacrificial layer 211 and then the removal protective layer
230；Alternatively, in the step of removing the first sacrificial layer 211, the protective layer 230 is removed.
Referring next to shown in Fig. 9 C, first sacrificial layer 211 is removed, so that with described first in the lower electrode 250
The surface of sacrificial layer contact is exposed.It is understood that after the first sacrificial layer is removed, you can make the lower electrode
The most outer surface that 250 tubular structure is located at outside cylinder exposes.
As method class with removing the second sacrificial layer, by using corresponding etching agent, and make etching agent directly to sudden and violent
Expose the first sacrificial layer perform etching and etching agent can also further horizontal proliferation, with it is further removal be located at first
Support the first sacrificial layer below layer 220a.
Figure 10 A are that the forming method of the array of capacitors in the utility model embodiment one performs step S180 processes at it
In top view；Figure 10 B~10C are respectively the formation of the array of capacitors in the utility model embodiment one shown in Figure 10 A
Method is during it performs step S180 along the diagrammatic cross-section on aa ' directions.
In step S180, powered on specific reference to a capacitor dielectric layer 270 and one shown in Figure 10 A~10C, is sequentially formed
Pole 280 is on the surfaces externally and internally of the lower electrode 250, by the top electrode 280, the capacitor dielectric layer 270 and the lower electricity
Pole 250 forms capacitance.
As shown in figs. 10 a and 10b, in the present embodiment, first is formed on the side wall of the tubular structure of lower electrode 250
Supporting layer 220a, the second supporting layer 220b and the 3rd supporting layer 220c, therefore, the lower electrode 250 of the covering of capacitor dielectric layer 270 expose
While the surface gone out, the first supporting layer 220a, the second supporting layer 220b and the 3rd supporting layer 220c are also further covered
Its surface exposed, i.e. the capacitor dielectric layer 270 coat the tubular structure of the lower electrode 250 be located at cylinder inside
Inner surface and the outer surface outside cylinder, to make full use of two opposite surfaces of lower electrode 250, forming has larger electricity
The capacitor of pole surface area.Specifically, the capacitor dielectric layer 270 is formed using gas-phase deposition, it is described for being formed
The process gas of capacitor dielectric layer 270 enters by the port of the 3rd supporting layer 220c to be formed on the surface of lower electrode 250,
And the process gas is entered further across connected entrance 250b in the cylinder inside of tubular structure, so as to the interior table inside cylinder
Capacitor dielectric layer 270 can be formed on outer surface outside face and cylinder.
Preferably, the capacitor dielectric layer 270 can be high-K dielectric layer.Further, the capacitor dielectric layer 270 is
Multilayered structure is, for example, the double-layer structure of silicon dioxide layer/silicon nitride layer.It, can be successively when forming the capacitor dielectric layer 270
It is respectively formed the silicon dioxide layer and the silicon nitride layer.
In addition, in the present embodiment, the bottom outside the cylinder of the tubular structure of the lower electrode 250 is with being formed in substrate 200
In node contact 201 connect, therefore, the capacitor dielectric layer 260 is not covered outside the cylinder of the tubular structure of the lower electrode 250
The part of the bottom in portion.
With continued reference to shown in Figure 10 C, one top electrode 280 of covering is on the capacitor dielectric layer 270, and the lower electrode
260 can form capacitance inside corresponding cylinder and outside the cylinder with the capacitor dielectric layer 270 and the top electrode 280.
That is, in the capacitor formed, it is being simply formed under one layer on the basis of electrode 260, is making full use of lower 260 two, electrode opposite
Surface, may make up capacitance in the both sides of lower electrode 260 respectively, the capacitance of the formed capacitor of increase.
Wherein, the top electrode 280 can be single layer structure or multilayered structure, when described 280 lists of top electrode
It is, for example, polysilicon electrode, or metal electrode when powering on extremely metal electrode, such as may be employed during layer structure
Titanium nitride (TiN) formation.In the present embodiment, the top electrode 280 includes one first conductive layer 281 and one second conductive layer 282,
The surface of first conductive layer 281 along the capacitor dielectric layer 270 is covered on the surface of the capacitor dielectric layer 270,
And the pattern of the pattern of first conductive layer 281 and the capacitor dielectric layer 270 corresponds to；Second conductive layer 282 covers
It covers first conductive layer 281 and the region between adjacent lower electrode 250 can be filled.Specifically, first conductive layer 281
Such as can be titanium nitride layer, second conductive layer 282 can be polysilicon layer or metal layer, for example, described second leads
Tungsten (W) formation may be employed in electric layer 282.
Embodiment two
The array of capacitors provided is described in detail in the utility model, the array of capacitors includes a shape
The first supporting layer of the lower electrode is used to support into the lower electrode in device region and one, first supporting layer can prolong
Reach the border of device region, i.e. the part in the first supporting layer positioned at device region border still possesses preferable integrality.
Figure 11 A are the top view of the array of capacitors in the utility model embodiment two；Figure 11 B are the sheet shown in Figure 11 A
Array of capacitors in utility model embodiment two is along the diagrammatic cross-section on aa ' directions.With reference to shown in Figure 11 A and Figure 11 B,
The array of capacitors includes：
There is one substrate 200 a device region 200A and one for being formed with capacitor to be located at device region 200A peripheries
External zones 200B；
Electrode 250 once are arranged on the device region 200A of the substrate 200, and the lower electrode 250 is with more
A tubular structure；
One first supporting layer 220a is formed on the device region 200A of the substrate 200, first supporting layer
Multiple tubular structures of the 220a connections lower electrode 250, and extend to the border of the device region 200A；Described first
Supporting layer 220a is used to support lower electrode 250, since the part for being located at device region 200A borders in the first supporting layer 220a remains to
Preferable integrality is enough kept, so as to can also play the work of support to being formed in the borderline tubular structures of device region 200A
With, avoid in lower electrode 250 be located at device region 200A it is borderline partially due to the increase of height and occur bending and deformation or fall
The problem of collapsing；
One capacitor dielectric layer 270 is formed on the surfaces externally and internally of the lower electrode 250；
One top electrode 280 is formed in the capacitor dielectric layer 270 corresponding to the surfaces externally and internally of the lower electrode 250
On surface, to be formed capacitance 290 with the capacitor dielectric layer 270 and the lower electrode 250.
Further, node contact 201, the node contact and the lower electrode 250 are also formed in the substrate 200
It is electrically connected.Specifically, the node contact 201 is connected with the cylinder bottom of the tubular structure of the lower electrode 250.
In the present embodiment, the array of capacitors further includes a protection ring 230, positioned at the periphery of the substrate 200
Area is along on the region of the device region.
With continued reference to shown in Fig. 9 B, the array of capacitors further includes one second supporting layer 220b, the second supporting layer 220b
It is located at interval on the first supporting layer 220a and connects the tubular structure of the lower electrode 250, and described second
Supporting layer 220b extends to the border of the device region 200A, and the second supporting layer 200a and the first supporting layer 200b exists
On different height and positions.That is, by forming multiple supporting layers on the different height position of the tubular structure of lower electrode 250,
It can strengthen the support strength to lower electrode 250.
Certainly, to improve to the support strength of lower electrode, except formed on the cylinder side wall of its tubular structure supporting layer it
Outside, also supporting layer can also be formed at the top of lower electrode.In the present embodiment, one is formed at the top of the lower electrode 250
Three supporting layer 220c, the 3rd supporting layer 220c is arranged on the second supporting layer 220b, and the 3rd supporting layer
A port is formed in 220c, the tubular structure of the lower electrode 250 is corresponding in the height projection area of the port
A part for top port.Preferably, in the tubular structure of the lower electrode 250, the corresponding cylinder side in the port
The height of wall is less than the height for not corresponding to cylinder side wall in the port, so that the tubular structure is covered with described the
The size for the connected entrance 250b that cylinder is internal during three supporting layer 220c and cylinder outside is interconnected increases.It is it is understood that described
Top port is to be directed to the opening that its inside of tubular structure itself is exposed, and connected entrance 250b is to be directed to be formed with the 3rd
After supporting layer 220c, under the covering of the 3rd supporting layer 220c, the opening that can be exposed inside the cylinder of the tubular structure.
In addition, the part for not corresponding to the port in the 3rd supporting layer 220 is linked to each other to form an entirety, such as
This one, can be connected multiple tubular structures of the 3rd supporting layer 220c with the lower electrode 250, with to multiple described
Tubular structure is supported.And the second supporting layer 220b and the first supporting layer 220a can be with the 3rd supporting layer 220c
Similar, i.e. the first supporting layer 220a and the second supporting layer 220b is also an entirety, so as to can contact multiple tubulars
The cylinder side wall of structure, and extend to the border of device region 200A.
With continued reference to shown in Figure 11 A and Figure 11 B, it should be noted that, it is only schematically illustrated in Figure 11 A more on substrate
The arrangement of a capacitor, and there is no the various components accurately shown in capacitor, for example, first is not shown in Figure 11 A
Support layer, the second supporting layer and the 3rd supporting layer etc..As seen in figs. 11a and 11b, in the tubular structure of the lower electrode 250,
Inner surface inside cylinder and the capacitor dielectric layer 270 and top electrode are all covered on the outer surface outside cylinder
Capacitor dielectric layer 270 outside 280 corresponding covering cylinders inside volume capacitor dielectric layers 270 and cylinder, so as to merely with electric under one
Pole 250, you can respectively constitute two capacitances 290 in the both sides of lower electrode 250 and capacitor dielectric layer 270 and top electrode 280.
Wherein, the top electrode 280 can be single layer structure or multilayered structure, when described 280 lists of top electrode
It is, for example, polysilicon electrode, or metal electrode when powering on extremely metal electrode, such as may be employed during layer structure
Titanium nitride (TiN) formation.In the present embodiment, the top electrode 280 includes one first conductive layer 281 and one second conductive layer 282,
The surface of first conductive layer 281 along the capacitor dielectric layer 270 is covered on the surface of the capacitor dielectric layer 270,
And the pattern of the pattern of first conductive layer 281 and the capacitor dielectric layer 270 corresponds to；Second conductive layer 282 covers
It covers first conductive layer 281 and the region between adjacent lower electrode 250 can be filled.Specifically, first conductive layer 281
Such as can be titanium nitride layer, second conductive layer 282 can be polysilicon layer or metal layer, for example, described second leads
Tungsten (W) formation may be employed in electric layer 282.
Embodiment three
Based on above-described array of capacitors, the utility model also provides a kind of semiconductor devices.Figure 12 A are this reality
With the distribution schematic diagram of the capacitor in semiconductor device array in new embodiment three, Figure 12 B are the semiconductor shown in Figure 12 A
Device is along the structure diagram on aa ' directions.As shown in Figure 12 A and Figure 12 B, the semiconductor devices includes：
There is one substrate 300 a device region 300A and one for being formed with capacitor to be located at device region 300A peripheries
External zones 300B, and it is also formed with a node contact 301, the node in the device region 300A on the substrate 300
Contact 301 is electrically connected with the capacitor；
Electrode 350 once form on the device region of the substrate and are electrically connected with the node contact 301, and
The lower electrode 350 has a tubular structure；
One first supporting layer 320a, is formed on the device region of the substrate, and the supporting layer connects the lower electricity
The tubular structure of pole 350, and extend to the border of the device region 300A；
One capacitor dielectric layer 370 is formed on the surfaces externally and internally of the lower electrode 350；
One top electrode 380 is formed in the surface of the capacitor dielectric layer 370 corresponding to the surfaces externally and internally of the lower electrode
On, the top electrode 350, the capacitor dielectric layer 370 and the lower electrode 380 form capacitance 390.
Wherein, the semiconductor devices can be a memory, and memory generally includes capacitor and is connected to described
The memory transistor of capacitor, the capacitor are used for storing the charge for representing storage information.Therefore, the semiconductor devices is also
It may include a memory cell array, the storage unit in the memory cell array is electrically connected with the capacitor.Specifically,
Storage unit in the memory cell array is electrically connected with the node contact, so as to utilize the node contact 301
Realize the electric connection of storage unit and capacitor.
With continued reference to shown in Figure 12 A and Figure 12 B, in the present embodiment, there is multiple be used for defined in the device region 200A
The memory active region 410 of storage unit is formed, multiple memory active regions 410 are arranged in array.And multiple storages
It is mutually isolated by the isolation structure 420 being formed in substrate 300 between active area 410.The periphery of the device region 200A
The isolation structure 420 is formed with, to isolate to device region 200A and external zones 200B.
Further, a bit line contact area 411 and one is formed in the substrate 300 of the corresponding memory active region 410 to deposit
It stores up in node contact area 412 and the substrate 300 between bitline contact area 411 of institute and the storage node contacts area 412
It is also formed with a gate structure 413.A bit line contact 302 being attached thereto, institute are also formed in bitline contact area 411 of institute
Bitline contact 302 is used to be further attached to a bit line；One is formed in the storage node contacts area 412 therewith to connect
The node contact 301 connect, the lower electrode 350 of the node contact 301 and the capacitor are electrically connected, single so as to fulfill storage
The electric connection of first and described capacitor.
In addition, also definition has multiple peripheral circuit active areas 430 in the external zones 200B, in the correspondence peripheral circuit
Peripheral circuit can be also formed on the substrate 300 of active area 430, for example, in the substrate of the correspondence peripheral circuit active area 430
Multiple gate structures etc. are formed on 300.
With continued reference to shown in Figure 12 B, it is located in the lower electrode 350 on the node contact 301 and is electrically connected therewith,
And extend along the surface away from the substrate and form tubular structure.In the present embodiment, in the tubular knot of the lower electrode 350
The first supporting layer 320a and the second supporting layer 320b are formed on the cylinder side wall of structure, to be propped up on cylinder side wall the lower electrode
Support.And one the 3rd supporting layer 320c is also formed on the top of the lower electrode 350, further strengthen to lower electrode 350
Support strength.Preferably, the multiple lower electrodes 350 being formed on multiple node contacts 301 with same first supporting layer
220a is contacted, i.e. the first supporting layer 220a is integral, and contacts the cylinder side wall of multiple lower electrodes 350 simultaneously, with simultaneously to more
A lower electrode 350 is supported.Certainly, the second supporting layer 320b and the 3rd supporting layer 320c can be with first supporting layer
320a is similar, is an entirety.
Referring next to shown in Figure 12 B, in the tubular structure of the lower electrode 350, inner surface inside cylinder and it is located at
The electricity being all covered on outer surface outside cylinder inside the capacitor dielectric layer 370 and the corresponding covering cylinder of top electrode 380
Hold the capacitor dielectric layer 370 outside dielectric layer 370 and cylinder, so as to merely with a lower electrode 350, you can in lower electrode 350
Both sides respectively constitute two capacitances 390 with capacitor dielectric layer 370 and top electrode 380.
Wherein, the top electrode 380 can be single layer structure or multilayered structure.It is described to power in the present embodiment
Pole 380 includes one first conductive layer 381 and one second conductive layer 382, and first conductive layer 381 is along the capacitor dielectric layer
370 surface is covered on the surface of the capacitor dielectric layer 370, and the pattern of first conductive layer 381 and the electricity
The pattern for holding dielectric layer 370 corresponds to；Second conductive layer 382 cover first conductive layer 381 and can fill it is adjacent under
Region between electrode 350.Specifically, first conductive layer 381 for example can be titanium nitride layer, second conductive layer
382 can be polysilicon layer or metal layer, for example, tungsten (W) formation may be employed in second conductive layer 382.
In conclusion in array of capacitors provided by the utility model, first supporting layer connects the lower electrode
Multiple tubular structures, and the border of device region is can extend to, the first supporting layer is avoided to be located at the part on device region border
There is the problem of sheet is removed or come off, and possess preferable integrality, and then can be ensured that the capacitance to device region boundary
Device can also play preferable supporting role.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.
Foregoing description is only the description to the utility model preferred embodiment, not to any limit of the scope of the utility model
Calmly, any change, the modification that the those of ordinary skill in the utility model field does according to the disclosure above content, belonging to right will
Seek the protection domain of book.
Claims (9)
1. a kind of array of capacitors, which is characterized in that including：
There is one substrate a device region for being formed with capacitor and one to be located at the external zones of device region periphery；
Electrode once is arranged on the device region of the substrate, and the lower electrode has multiple tubular structures；
One first supporting layer, is formed on the device region of the substrate, and first supporting layer connects the lower electrode
Multiple tubular structures, and extend to the border of the device region；
One capacitor dielectric layer is formed in the surfaces externally and internally of the lower electrode；And
One top electrode is formed in the surface of the capacitor dielectric layer, on described corresponding to the surfaces externally and internally of the lower electrode
Electrode, the capacitor dielectric layer and the lower electrode form capacitance.
2. array of capacitors as described in claim 1, which is characterized in that further include：
One protection ring, the external zones positioned at the substrate is along on the region of the device region.
3. array of capacitors as described in claim 1, which is characterized in that further include：
One second supporting layer on first supporting layer and connects the tubular structure of the lower electrode with interval,
Second supporting layer extends to the border of the device region, and second supporting layer from first supporting layer different
On height and position.
4. array of capacitors as claimed in claim 3, which is characterized in that further include：
One the 3rd supporting layer is arranged on second supporting layer and positioned at the top of the lower electrode, and the described 3rd supports
A port is formed in layer, the top end of the tubular structure of the lower electrode is corresponding in the height projection area of the port
A part for mouth.
5. array of capacitors as claimed in claim 4, which is characterized in that corresponding in the tubular structure of the lower electrode
The height of cylinder side wall in the port is less than the height for not corresponding to the cylinder side wall in the port, so that the tubular
The size for the connected entrance that structure is interconnected when covered with three supporting layer inside cylinder and outside cylinder increases.
6. array of capacitors as claimed in claim 4, which is characterized in that do not correspond to the port in the 3rd supporting layer
Part is linked to each other to form an entirety, the 3rd supporting layer, second supporting layer and first supporting layer with
Multiple tubular structure connections, to be supported to multiple tubular structures.
7. a kind of semiconductor devices, which is characterized in that including：
There is one substrate a device region for being formed with capacitor and one to be located at the external zones of device region periphery, and described
A node contact is also formed in the device region on substrate, the node contact is electrically connected with the capacitor；
Electrode once is arranged on the device region of the substrate and is electrically connected with the node contact, and the lower electricity
Has a tubular structure；
One supporting layer is formed on the device region of the substrate, and the supporting layer connects the tubular of the lower electrode
Structure, and extend to the border of the device region；
One capacitor dielectric layer is formed on the surfaces externally and internally of the lower electrode；And
One top electrode is formed on the surface of the capacitor dielectric layer corresponding to the surfaces externally and internally of the lower electrode, by described
Top electrode, the capacitor dielectric layer and the lower electrode form capacitance.
8. semiconductor devices as claimed in claim 7, and be characterized in that, a storage unit is also formed with over the substrate,
The storage unit is electrically connected with the node contact.
9. semiconductor devices as claimed in claim 7 or 8, which is characterized in that multiple capacitors are formed with over the substrate,
Multiple lower electrodes of multiple capacitors are connected with same supporting layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721270885.2U CN207409480U (en) | 2017-09-29 | 2017-09-29 | Array of capacitors, semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721270885.2U CN207409480U (en) | 2017-09-29 | 2017-09-29 | Array of capacitors, semiconductor devices |
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