CN207399250U - A kind of demodulator circuit for supporting 14443 standards of ISO/IEC - Google Patents
A kind of demodulator circuit for supporting 14443 standards of ISO/IEC Download PDFInfo
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- CN207399250U CN207399250U CN201721256354.8U CN201721256354U CN207399250U CN 207399250 U CN207399250 U CN 207399250U CN 201721256354 U CN201721256354 U CN 201721256354U CN 207399250 U CN207399250 U CN 207399250U
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Abstract
The utility model is related to RF tags to identify field,More particularly to a kind of demodulator circuit for supporting 14443 standards of ISO/IEC,The demodulator circuit of 14443 standards of support ISO/IEC,Envelope circuit is taken by sequentially connected,Amplifier circuit,Negative circuit and level shifting circuit realize the ASK modulation of input signal,And pass through the phase inverter that enable signal is provided in negative circuit,The phase inverter is according to the demodulation modes control signal output enable signal received so that negative circuit stops ASK10% modulation,ASK10% modulates the demodulator circuit output 100%ASK signals of 14443 standards of support ISO/IEC,The demodulator circuit of 14443 standards of support ISO/IEC is enabled to realize ASK10% modulation and ASK100% modulation,And the circuit structure is relatively easy,It is easy to implement.
Description
Technical field
The present invention relates to RF tags to identify field, more particularly to a kind of demodulation electricity for supporting 14443 standards of ISO/IEC
Road.
Background technology
Radio frequency identification (Radio Frequency Identification) system is a kind of non-contact automatic recognition system.
With the development of Internet of Things, RFID is received more and more attention.One complete RFID system is by RFID label tag, RFID read-write
Device and back-end server three parts are formed.RFID label tag includes the information such as unique identifier.RFID reader passes through short distance
Radio communication obtain the identification information of RFID label tag, and the label information of acquisition can be sent to back-end server.Afterwards
The information that end server process is obtained from reader, and feedack will be needed to be sent to reader, then will by reader
Feedback information is sent to RFID label tag by radiofrequency signal, so as to fulfill the management to RFID label tag.
The electromagnetic wave carrier frequency according to used in RFID system can be divided into low frequency LF 125KHz-135KHz, high frequency HF
13.56MHz, hyperfrequency UHF 860MHz-960MHz and microwave M icrowave 2.45GHz.Wherein, HF RPID tags by
In its recognition apart from moderate, cost is relatively low, is widely used in gate inhibition, storage and logistics field.According to label data storage and
Label can be divided into passive label, semi-active label and active label by the difference of power supply mode.As shown in Figure 1, passive HF
RFID label chip is broadly divided into three parts：AFE(analog front end) part, digital baseband part and EEPROM storages part.Mould
Intend fore-end and can be mainly divided into rectification and voltage stabilizing circuit module, demodulator circuit module, return modulation circuit module, clock production
Raw module, overvoltage crowbar module, reset signal generation module and electrostatic discharge protective circuit module.
After RFID label tag enters the magnetic field of reader transmitting signal, exchange that rectification circuit generates antenna inductive coupling
Signal carries out rectification and obtains a d. c. voltage signal, which further generates a stabilization by regulator circuit
DC voltage give other modules of analog front circuit, the digital control part of chip and EEPROM storage part power.
Meanwhile demodulator circuit is demodulated aerial signal, and will export signal transmission to digital baseband.Digital baseband and EEPROM pairs
Return signal is transferred to the return modulation circuit in analog front circuit by data after being handled, will by returning to modulation circuit
The data sending of label chip returns reader.Clock generation circuit and reset signal generating circuit generate clock signal and answer respectively
Position signal, and it is transferred to digital baseband part.When label and reader apart from it is close when, the energy obtained on label antenna is opposite
It is more sufficient, it is released by pressure limited protection circuit from antenna part energy, it is ensured that label chip is operated in metastable
Under environment.Electrostatic discharge protective circuit can then protect chip circuit to prevent it from being damaged be subject to electrostatic.
High frequency RFID systems are respectively ISO/IEC 14443Type A/B, ISO/IEC 15693 there are three types of international standard
And ISO/IEC 18000-3.The present invention is using the ISO/IEC 14443Type B standards based on inductive coupling principles.
Transport protocol as defined in 14443 agreements of ISO/IEC is simultaneously suitable for Type A and Type B.Regulation is in reader in Type A
It is that improved synchronization is used come transmission signal by the carrier wave of 13.56MHz when being communicated by downlink with label
The mode of Miller codings transmits signal by way of ASK100% modulation, and demodulation waveforms are as shown in Figure 2.In Type B
Equally using the carrier wave of 13.56MHz come transmission signal, but using asynchronous nrz encoding mode, pass through ASK10% modulation
Mode transmits signal, and demodulation waveforms are as shown in Figure 3.Due to the limitation of label chip cost and size, receiver in chip slapper
It is as simple as possible, the demodulator circuit of label chip AFE(analog front end) part is also required to simplify, if necessary in a chip
It is upper to realize that ASK10% modulation and the mode of ASK100% modulation transmit signal simultaneously, it may result in demodulator circuit complication.
The content of the invention
It is an object of the invention to provide one kind can realize ASK10% modulation and ASK100% modulation, and demodulator circuit
The relatively simple demodulator circuit for supporting 14443 standards of ISO/IEC.
The purpose of the present invention is achieved through the following technical solutions：
A kind of demodulator circuit for supporting 14443 standards of ISO/IEC is provided, envelope circuit, amplification are taken including sequentially connected
Device circuit, negative circuit and level shifting circuit, into the demodulator circuit ASK signals by it is described take envelope circuit after export
For envelope signal, which obtains ASK demodulation pulse signals, ASK demodulation pulse letters after amplifier circuit amplifies
Number by negative circuit realize ASK10% modulation after formed ASK signal waveforms, the ASK signal waveforms pass through level shifting circuit
It is transformed into the voltage domain of digital circuit；The negative circuit includes the phase inverter with enable signal, and the phase inverter is according to receipts
The demodulation modes control signal output enable signal arrived is so that the negative circuit stops ASK10% modulation.
Wherein, it is described that envelope circuit is taken to include sequentially connected half-wave rectifying circuit and low-pass filter circuit.
Wherein, the amplifier circuit includes low gain amplifying circuit and high-gain push-pull amplifier circuit.
Wherein, the low gain amplifying circuit is connected with bias-voltage generating circuit.
Wherein, the input terminal of the phase inverter with enable signal of the negative circuit, which is connected with, is used to implement waveform shaping
With the cross-coupling unit of storage.
Wherein, the cross-coupling unit includes phase inverter invert1 and phase inverter invert2.
Wherein, the level shifting circuit includes four phase inverters and two NMOS tubes, is used to implement from voltage domain to electricity
Press the conversion in domain.
Beneficial effects of the present invention：The demodulator circuit of 14443 standards of support ISO/IEC takes bag by sequentially connected
Network circuit, amplifier circuit, negative circuit and level shifting circuit realize the ASK modulation of input signal, and by reverse phase
The phase inverter of enable signal is provided in circuit, it is necessary to use ASK100% modulation when, can make the phase inverter enable so as to
Stop the ASK10% modulation of negative circuit.The demodulator circuit of 14443 standards of support ISO/IEC can both export 10%ASK
Signal can also stop ASK10% modulation so as to export 100%ASK signals so that 14443 standards of support ISO/IEC
Demodulator circuit can realize ASK10% modulation and ASK100% modulation, and the circuit structure is relatively easy, is easy to implement.
Description of the drawings
Fig. 1 is passive HF RFID label chip structure chart of the present invention；
Fig. 2 is 100%ASK demodulation waveforms schematic diagram of the present invention；
Fig. 3 is 10%ASK demodulation waveforms schematic diagram of the present invention；
Fig. 4 is 10%ASK demodulator circuits functional block diagram of the present invention；
Fig. 5 takes envelope schematic block circuit diagram for the present invention；
Fig. 6 is OP1 amplifier circuits functional block diagram of the present invention；
Fig. 7 is power supply generation circuit functional block diagram of the present invention；
Fig. 8 is bias-voltage generating circuit functional block diagram of the present invention；
Fig. 9 is level shifter functional block diagram of the present invention.
Specific embodiment
Amplitude shift keying (ASK) is " amplitude shift keying ", is a kind of relatively simple modulation system also known as " amplitude-shift keying ".
Amplitude shift keying (ASK) is equivalent to the amplitude modulation in analog signal, and what is be only multiplied with CF signal is binary numeral.Width
Shifting is exactly as constant, and using amplitude as variable using frequency, phase, and information bit is transferred by the amplitude of carrier wave.
In the definition of amplitude shift keying, the amplitude of carrier wave is according to binary-coded method in u0And u1Between switch over, u1Desirable u0With
Value between 0.Keying degree m is defined, to describe different degrees of keying：
Work as u0=u1When, m=0, at this time carrier wave do not modulated；Work as u1When=0, m=1 is this to be modulated to 100% amplitude
Modulation.
ASK modulated signals can be described as：
V (t)=u0[1+m(s(t)-1)]cos(ωct)
S (t) is binary signal, and value is 0 or 1.According to the difference of encoded signal, the modulated signal g (t) of s (t) can be retouched
State for：
G (t)=u0[1+m (s (t) -1)]=mu0s(t)+u0(1-m)
G (t) represents that its frequency spectrum is in frequency domain：
G (f)=mu0S(f)+u0(1-m)δ(f)
Its energy density is represented by：
PSDR(f)=(mu0)2PSDS(f)+[u0(1-m)]2δ(f)
The part of positive frequency is taken, then modulated signal energy spectral density is represented by：
By as above analyzing, the energy spectral density of baseband signal determines the bandwidth of modulated signal, and carrier amplitude and
Keying degree m has codetermined the amplitude of modulated signal.During keying degree m=1, the energy spectral density PSD of modulated signalV(f) it is base band
Signal energy spectral density is multiplied by the 1/4 of carrier wave amplitude peak square, and the reduction of sideband amplitude, and meeting can be caused by reducing keying degree m
It is introduced into and increases weight of the delta function in carrier frequency.
Based on as above analyzing, the functional block diagram of 10%ASK demodulator circuits including sequentially connected as shown in figure 4, take envelope
Circuit, amplifier circuit, negative circuit and level shifting circuit.R1 and C1 provides alternating current path for the ASK envelope signals taken out,
To detect the jump edge signal of ASK signals.OP1 and OP2 is low gain amplifying circuit, and OP3 is high-gain push-pull amplifier circuit,
Phase inverter invert1 and invert2 form cross-couplings storage unit, and (two is defeated for the phase inverter with enable signal by invert3
Enter NAND gate), level shift are that level shifting circuit realizes that the level in different voltages threshold switches, and Bias is bias voltage
Generation circuit provides bias voltage for OP1.In the circuit course of work, the ASK signals of input take envelope circuit by diode
An envelope signal is exported, the jump edge of the envelope signal is sent to the defeated of amplifier OP1 by the alternating current path of R2 and C2
Enter end, this is jumped edge signal and ASK demodulation pulse signals are obtained after the amplification of OP1, OP2 and OP3 three-level, this pulse passes through again
The cross-coupling unit for crossing phase inverter invert1 and invert2 composition realizes waveform shaping and store function, obtained at this time
It is the ASK demodulation pulse signals of standard.Due to ASK demodulated signals at this time with desired waveform on the contrary, so the signal passes through again
It crosses the en phase inverters invert3 with enable signal and can be obtained by required ASK signal waveforms.Turn using level shifting circuit
It changes in the voltage domain of digital circuit to get the ASK demodulated signals that can be directly handled to numerical portion.
Each modular circuit is analyzed below：
Amplifier OP2 and OP1 in Fig. 4 is just the same, and OP3 is a simple phase inverter to provide high-gain, INV1
It is two reversers with INV2, INV3 is the phase inverter (i.e. two input nor gates) with enable signal.Enable signal EN is core
Signals of the piece global reset signal CLR after reverse phase.
Wherein, as shown in figure 5, ANTA and ANTB in envelope circuit is taken to obtain the primary rectifier electricity of REC1 by halfwave rectifier
Pressure, MN3, MN4 and MN5 form active pull-up and a low-pass filter are formed together with C1, and realization follows input ASK signal envelopes
Effect.
Wherein, OP1 and OP2 is low gain amplifying circuit, as shown in fig. 6, OP1 and OP2 are respectively with commonly recommending amplification
Increase a low gain section on the similar transmission curve of device, the bias voltage of circuit is made to fall in this low gain section.It should
Amplifier OP1 reduces influence of the drift to amplification effect of circuit bias voltage using this characteristic, while is also beneficial to carry
The Anti-Jamming of this high circuit.The power supply of the circuit is provided by power generation circuit as shown in Figure 7, the normal work of the circuit
When making, bias voltage is arranged on the slow last transition in characteristic curve, can improve the anti-interference of bias voltage.
Wherein, bias-voltage generating circuit input is about the voltage of 1.56V to VmidSo that MN1 and MP1 are operated in Fig. 8
Saturation region, MP2 and MN2 are operated in deep linear zone, and MN3 and MP3 are operated in sub-threshold region.
Wherein, Fig. 9 shows the level transfer sub-circuit in 10% demodulator circuit, this circuit is by four phase inverters and two
A NMOS tube composition, is used to implement by VmidVoltage domain is to VCCThe conversion of voltage domain.
The demodulator circuit of 14443 standards of support ISO/IEC of the invention, based on inductive coupling principles, realizes Type B
Standard, label chip maximum read distance are 10cm, minimum field strength Hmin=1.5A/m, maximum field strength Hmax=7.5A/m.
The demodulator circuit of 14443 standards of support ISO/IEC of the invention, routine data transfer use 10%ASK modulation demodulation systems.
Meanwhile when label receive 100% modulated signal when, the voltage change that label antenna is experienced clearly, of the invention 10%
ASK demodulator circuits can also demodulate 100%ASK signals.
Claims (7)
1. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC, which is characterized in that take envelope electric including sequentially connected
Road, amplifier circuit, negative circuit and level shifting circuit, into the demodulator circuit ASK signals pass through described in take envelope electric
Output is envelope signal behind road, which obtains ASK demodulation pulse signals, ASK solutions after amplifier circuit amplifies
Pulse signal is adjusted to form ASK signal waveforms after negative circuit realizes ASK10% modulation, the ASK signal waveforms are through over level
Conversion circuit is transformed into the voltage domain of digital circuit；The negative circuit includes the phase inverter with enable signal, the reverse phase
Device enables, and/not enabling so that the negative circuit stops/not stopping ASK10% modulation.
2. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 1, which is characterized in that described
Envelope circuit is taken to include sequentially connected half-wave rectifying circuit and low-pass filter circuit.
3. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 1, which is characterized in that described
Amplifier circuit includes low gain amplifying circuit and high-gain push-pull amplifier circuit.
4. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 3, which is characterized in that described
Low gain amplifying circuit is connected with bias-voltage generating circuit.
5. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 1, which is characterized in that described
The input terminal of the phase inverter with enable signal of negative circuit is connected with the cross-couplings for being used to implement waveform shaping and storage
Unit.
6. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 5, which is characterized in that described
Cross-coupling unit includes phase inverter invert1 and phase inverter invert2.
7. a kind of demodulator circuit for supporting 14443 standards of ISO/IEC according to claim 1, which is characterized in that described
Level shifting circuit includes four phase inverters and two NMOS tubes, is used to implement by VmidVoltage domain is to VCCThe conversion of voltage domain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721256354.8U CN207399250U (en) | 2017-09-27 | 2017-09-27 | A kind of demodulator circuit for supporting 14443 standards of ISO/IEC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721256354.8U CN207399250U (en) | 2017-09-27 | 2017-09-27 | A kind of demodulator circuit for supporting 14443 standards of ISO/IEC |
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| Publication Number | Publication Date |
|---|---|
| CN207399250U true CN207399250U (en) | 2018-05-22 |
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ID=62404188
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721256354.8U Withdrawn - After Issue CN207399250U (en) | 2017-09-27 | 2017-09-27 | A kind of demodulator circuit for supporting 14443 standards of ISO/IEC |
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| Country | Link |
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| CN (1) | CN207399250U (en) |
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2017
- 2017-09-27 CN CN201721256354.8U patent/CN207399250U/en not_active Withdrawn - After Issue
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| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20180522 Effective date of abandoning: 20180717 |
|
| AV01 | Patent right actively abandoned |