CN207381409U - It is inverted the power MOSFET of gate structure - Google Patents
It is inverted the power MOSFET of gate structure Download PDFInfo
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- CN207381409U CN207381409U CN201721009526.1U CN201721009526U CN207381409U CN 207381409 U CN207381409 U CN 207381409U CN 201721009526 U CN201721009526 U CN 201721009526U CN 207381409 U CN207381409 U CN 207381409U
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Abstract
The utility model disclose it is a kind of be inverted gate structure power MOSFET, be inverted gate structure power MOSFET it include which is provided with source electrode, grid and the wafer of drain electrode；In the design, source electrode is arranged on the front of the wafer, and drain and gate is arranged at the back side of wafer；This method it include the processing of a. wafer frontside source electrodes；B. wafer rear grid and the two big step of processing of drain electrode.
Description
Technical field
The present invention relates to power semiconductor technologies field more particularly to a kind of power MOSFET for being inverted gate structure.
Background technology
For common power MOSFET, the front of wafer is the source electrode and grid of device, and the back side of wafer is
The drain electrode of device；And it is for some special applications, it is desirable to which the grid of device is inverted to the back side of wafer；So in wafer
Front be device source electrode, the back side of wafer is the drain and gate of device；But such power is had no in the prior art
MOSFET。
The content of the invention
It is an object of the invention to overcome the deficiencies in the prior art, adapt to real needs, provide a kind of inversion gate structure
Power MOSFET.
In order to achieve the object of the present invention, the technical solution adopted in the present invention is：
The invention discloses a kind of power MOSFET for being inverted gate structure, including which is provided with source electrode, grid and drain electrode
Wafer；Source electrode is arranged on the front of the wafer, and drain and gate is arranged at the back side of wafer.
The source electrode is equipped with an electroplated layer or is printed with tin paste layer.
The electroplated layer or be printed with tin paste layer side wafer frontside be equipped with plastic packaging layer, the electroplated layer being connected with source electrode or
Tin paste layer is exposed to outside plastic packaging layer.
The drain and gate is exposed to the back side of wafer through substrate.
The drain and gate is equipped with metal layer, the metal layer on metal layer and grid in drain electrode by groove every
From.
It is equipped with polyimide insulator in the groove, it is sub- that the metal layer on metal layer and grid in drain electrode passes through polyamides
Amine insulator is isolated.
The beneficial effects of the present invention are：
The present invention changes traditional power MOSFET designs, its drain and gate is arranged to the back side of wafer, makes this work(
Rate MOSFET can be used in some special be used for.
Description of the drawings
Fig. 1 is the wafer rear processing step in the present invention（1）Structure diagram；
Fig. 2 is that the wafer in the present invention proves processing step（1）Structure diagram；
Fig. 3 is the wafer rear processing step in the present invention（2）Structure diagram；
Fig. 4 is the wafer rear processing step in the present invention（3）Structure diagram；
Fig. 5 is the wafer rear processing step in the present invention（4）Structure diagram；
Fig. 6 is the wafer rear processing step in the present invention（5）Structure diagram；
Fig. 7 is the wafer frontside processing step in the present invention（2）Structure diagram；
In figure：
1. wafer;2. substrate;3. at grid pressure welding point;4. at source electrode pressure welding point;5. at the pressure welding point that drains;7. polysilicon;
8. electroplated layer or print solder paste layer;9. plastic packaging layer;10. source electrode;11. metal layer;12. groove;13. polyimide insulator.
Specific embodiment
The present invention is further described with reference to the accompanying drawings and examples：
Embodiment 1：A kind of power MOSFET for being inverted gate structure, referring to Fig. 7；Power MOSFET includes which is provided with source
The wafer 1 (prior art) of pole, grid and drain electrode；In the design, the source electrode 10 of this power MOSFET is arranged on the wafer 1
Front, drain and gate are arranged at the back side of wafer.
Further, the source electrode of the design is equipped with an electroplated layer or is printed with tin paste layer 8, meanwhile, the plating
Layer is printed with the front of wafer 1 of 8 side of tin paste layer and is equipped with plastic packaging layer 9, and the electroplated layer being connected with source electrode 10 or tin paste layer 8 are exposed
Outside plastic packaging layer 9.
And the drain and gate is exposed to the back side of wafer 1 through substrate 2, meanwhile, described on 1 back side of wafer
Drain and gate is equipped with metal layer 11, and the metal layer on metal layer 11 and grid in drain electrode is isolated by groove 12, described
It is equipped with polyimide insulator 13 in groove 12, the metal layer 11 on metal layer and grid in drain electrode passes through polyimide insulative
Body 13 is isolated.
Embodiment 2, referring to Fig. 1 to Fig. 7, a kind of making is inverted the power MOSFET's of gate structure as described in Example 1
Method, this method are implemented on source electrode, grid and the wafer of drain electrode in force, source electrode, grid and the pressure welding of drain electrode
Point is respectively positioned on the front of wafer, this method it include the following steps：
A. to the processing of wafer frontside source electrode:
（1）Electroplated layer or print solder paste layer are done at the pressure welding point of wafer frontside source electrode, referring to Fig. 2；
（2）Wafer frontside plastic packaging forms plastic packaging layer, referring to Fig. 3；
（3）Wafer frontside grinding is exposed by source electrode, referring to Fig. 7；
B. to the processing of wafer rear grid and drain electrode：
（1）Deep trouth is etched to substrate direction at grid and the pressure welding point of drain electrode, the lower end of deep trouth terminates in the inside of substrate；
It is filled in deep trouth with DOPOS doped polycrystalline silicon, referring to Fig. 1；
（2）The back side thickness of wafer is thinned and leaks out the polysilicon in deep trouth, referring to Fig. 3；
（3）Wafer rear metallizes to form metal layer, referring to Fig. 4；
（4）The groove is made in wafer rear photoetching, and drain and gate is isolated, referring to Fig. 5；
（5）Wafer rear does polyimide coating and carries out photoetching, carries out light to the polyimides beyond groove during photoetching
It carves, the polyimides retained in groove forms polyimide insulator, referring to Fig. 6.
In implementation, above-mentioned steps a and step b orders are exchanged.
The power MOSFET for being inverted gate structure as described in Example 1 can be produced thus by this method, is passed through
The power MOSFET for the inversion gate structure that this method is produced can be used for needing grid inversion arriving wafer in the application
It uses, can be used in some special applications in the case of the back side.
What the embodiment of the present invention was announced is preferred embodiment, but is not limited thereto, the ordinary skill people of this field
Member easily according to above-described embodiment, understands the spirit of the present invention, and makes different amplification and variation, but as long as not departing from this
The spirit of invention, all within the scope of the present invention.
Claims (4)
1. a kind of power MOSFET for being inverted gate structure, including which is provided with source electrode, grid and the wafer of drain electrode；Its feature exists
In：Source electrode is arranged on the front of the wafer, and drain and gate is arranged at the back side of wafer；
The source electrode is equipped with an electroplated layer or is printed with tin paste layer；The electroplated layer is printed with the wafer of tin paste layer side just
Face is equipped with plastic packaging layer, and the electroplated layer or tin paste layer being connected with source electrode are exposed to outside plastic packaging layer.
2. the power MOSFET of gate structure is inverted as described in claim 1, it is characterised in that：The drain and gate passes through
Substrate is exposed to the back side of wafer.
3. the power MOSFET of gate structure is inverted as claimed in claim 2, it is characterised in that：It is set on the drain and gate
There is a metal layer, the metal layer on metal layer and grid in drain electrode is isolated by groove.
4. the power MOSFET of gate structure is inverted as claimed in claim 3, it is characterised in that：Polyamides is equipped in the groove
Imines insulator, the metal layer on metal layer and grid in drain electrode are isolated by polyimide insulator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721009526.1U CN207381409U (en) | 2017-08-14 | 2017-08-14 | It is inverted the power MOSFET of gate structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721009526.1U CN207381409U (en) | 2017-08-14 | 2017-08-14 | It is inverted the power MOSFET of gate structure |
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| Publication Number | Publication Date |
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| CN207381409U true CN207381409U (en) | 2018-05-18 |
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| CN201721009526.1U Active CN207381409U (en) | 2017-08-14 | 2017-08-14 | It is inverted the power MOSFET of gate structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564963A (en) * | 2017-08-14 | 2018-01-09 | 深圳市芯电元科技有限公司 | It is inverted the power MOSFET and preparation method of grid structure |
| US20210272746A1 (en) * | 2018-06-29 | 2021-09-02 | Shidengen Electric Manufacturing Co., Ltd. | Electronic device |
-
2017
- 2017-08-14 CN CN201721009526.1U patent/CN207381409U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107564963A (en) * | 2017-08-14 | 2018-01-09 | 深圳市芯电元科技有限公司 | It is inverted the power MOSFET and preparation method of grid structure |
| US20210272746A1 (en) * | 2018-06-29 | 2021-09-02 | Shidengen Electric Manufacturing Co., Ltd. | Electronic device |
| US11967451B2 (en) * | 2018-06-29 | 2024-04-23 | Shindengen Electric Manufacturing Co., Ltd. | Electronic device |
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