CN207352599U - A kind of offline downloaders of FPGA - Google Patents
A kind of offline downloaders of FPGA Download PDFInfo
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- CN207352599U CN207352599U CN201721410019.9U CN201721410019U CN207352599U CN 207352599 U CN207352599 U CN 207352599U CN 201721410019 U CN201721410019 U CN 201721410019U CN 207352599 U CN207352599 U CN 207352599U
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- fpga
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Abstract
The utility model belongs to electronic technology field, there is provided a kind of offline downloaders of FPGA.In the utility model,By using including microcontroller,Power supply chip,Electrical level transferring chip,JTAG download interfaces,The offline downloaders of FPGA of digital card interface and memory,During so that the offline downloaders of the FPGA working under the supply voltage of power supply chip,When microcontroller detects download signal,Microcontroller detects the identification code of FPGA by JTAG download interfaces,When identification code is target identification code,Application program corresponding with target identification code will be stored in digital card read and cached into memory,And the memory of FPGA is wiped by JTAG download interfaces,And being read to the status register of FPGA,When the state of status register is write state,Application program corresponding with target identification code is sent to FPGA by JTAG download interfaces,Realized with this and off line download is carried out to FPGA,Its is simple in structure,Circuit stability,Speed of download is fast,Confidentiality and versatile.
Description
Technical field
The utility model belongs to electronic technology field, more particularly to a kind of offline downloaders of FPGA.
Background technology
With the development of field programmable gate array (Field-Programmable Gate Array, FPGA) technology,
FPGA has been directed to the every field such as communication, Industry Control, robot, image procossing and consumer electronics, and for
For FPGA, it is needed by FPGA downloaders and downloaded or burning application program extremely in actual use
FPGA, so that FPGA carries out relevant work according to corresponding application program.
Even however, same FPGA manufacturers, since the product architecture of the FPGA of its production is not quite similar, FPGA
Downloader can not be substituted for each other use, reduce versatility；In addition, in process of production, FPGA is burnt using computer
Low there are efficiency during record, confidentiality is poor, complicated, and dumb the problems such as facilitating is being used in production line.
Therefore, it is necessary to a kind of technical solution is provided, to solve above-mentioned technical problem.
Utility model content
The purpose of this utility model is to provide a kind of offline downloaders of FPGA, the offline downloaders of the FPGA are supported under off line
Carry, and simple in structure, circuit stability, speed of download are fast, confidentiality and versatile.
The utility model is realized in this way a kind of offline downloaders of FPGA, are connected, the FPGA is downloaded offline with FPGA
Device includes：
Microcontroller, power supply chip, electrical level transferring chip, JTAG download interfaces, digital card interface and memory；
The voltage end of the power supply chip and the voltage end of the microcontroller, the voltage end of the electrical level transferring chip, institute
State the voltage end connection of the voltage end and the FPGA of memory；First output terminal of the microcontroller is downloaded with the JTAG
The input terminal connection of interface, the first output terminal of the JTAG download interfaces is connected with the first input end of the FPGA, described
Second output terminal of JTAG download interfaces is connected with the input terminal of the electrical level transferring chip, the output of the electrical level transferring chip
End is connected with the second input terminal of the FPGA, and the output terminal of the number card interface is connected with the input terminal of the microcontroller,
The input/output terminal of the memory is connected with the input/output terminal of the microcontroller；
The power supply chip is the microcontroller, the electrical level transferring chip, the memory and the FPGA provide
Supply voltage；The number card interface grafting digital card, the digital card are stored with multiple application programs；When the monolithic machine examination
When measuring download signal, the microcontroller detects the identification code of the FPGA by the JTAG download interfaces, in the mark
When code is target identification code, application program corresponding with the target identification code will be stored in the digital card and is read to described
Cached in memory, and the memory of the FPGA is wiped by the JTAG download interfaces, and to described
The status register of FPGA is read, when the state of the status register is write state, will it is described with it is described
The corresponding application program of target identification code is sent to the FPGA by the JTAG download interfaces.
In the utility model, by using including microcontroller, power supply chip, electrical level transferring chip, JTAG download interfaces,
The offline downloaders of FPGA of digital card interface and memory so that the offline downloaders of the FPGA are under the supply voltage of power supply chip
During work, when microcontroller detects download signal, microcontroller detects the identification code of FPGA by JTAG download interfaces, in identification code
For target identification code when, application program corresponding with target identification code will be stored in digital card and is read and is delayed into memory
Deposit, and the memory of FPGA is wiped by JTAG download interfaces, and behaviour is read out to the status register of FPGA
Make, when the state of status register is write state, application program corresponding with target identification code is passed through into JTAG download interfaces
Send to FPGA, realized with this and off line download is carried out to FPGA, its simple in structure, circuit stability, speed of download are fast, confidentiality and
It is versatile.
Brief description of the drawings
Fig. 1 is the modular structure schematic diagram for the offline downloaders of FPGA that one embodiment of the utility model is provided；
Fig. 2 is the modular structure schematic diagram for the offline downloaders of FPGA that another embodiment of the utility model is provided.
Embodiment
In order to make the purpose of the utility model, technical solutions and advantages more clearly understood, below in conjunction with attached drawing and implementation
Example, is further elaborated the utility model.It should be appreciated that specific embodiment described herein is only explaining
The utility model, is not used to limit the utility model.
It is described in detail below in conjunction with realization of the specific attached drawing to the utility model：
Fig. 1 shows the modular structure for the offline downloaders 10 of FPGA that one embodiment of the utility model is provided, in order to just
In explanation, part related to the present embodiment is illustrate only, details are as follows：
As shown in Figure 1, the offline downloaders 10 of FPGA that the utility model embodiment is provided are connected with FPGA20, and should
The offline downloaders 10 of FPGA include：Microcontroller 100, power supply chip 101, electrical level transferring chip 102, JTAG download interfaces 103, number
Code card interface 104 and memory 105.
Wherein, the voltage end of the voltage end of power supply chip 101 and microcontroller 100, electrical level transferring chip 102 voltage end,
The voltage end connection of the voltage end and FPGA20 of memory 105；First output terminal of microcontroller 100 and JTAG download interfaces
103 input terminal connection, the first output terminal of JTAG download interfaces 103 and the first input end of FPGA20 connect, and JTAG is downloaded
Second output terminal of interface 103 is connected with the input terminal of electrical level transferring chip 102, the output terminal of electrical level transferring chip 102 with
The second input terminal connection of FPGA20, the output terminal of digital card interface 104 are connected with the input terminal of microcontroller 100, memory 105
Input/output terminal be connected with the input/output terminal of microcontroller 100.
Specifically, power supply chip 101 is microcontroller 100, electrical level transferring chip 102, memory 105 and FPGA20 provide
Supply voltage；Digital 104 grafting digital card (not shown) of card interface, digital card are stored with multiple application programs；Work as monolithic
When machine 100 detects download signal, microcontroller 100 detects the identification code of FPGA20 by JTAG download interfaces 103, in identification code
For target identification code when, will be stored in digital card application program corresponding with target identification code read into memory 105 into
Row caching, and wipes the memory of FPGA20 by JTAG download interfaces 103, and to the status register of FPGA20
It is read, when the state of status register is write state, application program corresponding with target identification code is passed through
JTAG download interfaces 103 are sent to FPGA20, and download program is carried out to FPGA with this.
It should be noted that in the utility model embodiment, digital card interface 104 refers to safe digital card
(Secure Digital Memory Card, SD) card slot, the SD card slot are stored in the SD card to grafting SD card
Multiple application programs can be the application program of FPGA or the difference of different vendor of the different frameworks of same manufacturer
The application program of the FPGA of framework, is not particularly limited herein；Download signal detected by microcontroller 100 can be host computer
Download button on the offline downloaders 10 of to microcontroller 100 or user's operation FPGA is sent according to user's operation
Afterwards, the push button signalling detected by microcontroller 100, is not particularly limited herein, and it is worth noting that, when user often operates one
Secondary download button, microcontroller 100 carries out a download program to FPGA20, and FPGA provided by the utility model is downloaded offline
Device 10 can set download time.
In addition, in the utility model embodiment, the identification code of FPGA20 is the identity characterization information of FPGA20, each
FPGA20 has a unique identification code, and microcontroller 100 can carry out the identity of FPGA20 by unique identification code
Correct to judge, to identify that FPGA20 to be downloaded is target device, i.e., whether FPGA20 to be downloaded, which needs to download, is answered
With the FPGA of program, and when it is target device that microcontroller 100, which judges FPGA20 to be downloaded, microcontroller 100 can also root
The application program of target FPGA is looked into the multiple application programs stored according to unique identification code in memory 105
Look for, to determine to need the application program being downloaded in target FPGA；Wherein, in multiple application programs that memory 105 stores
Each application program and a codes match.
It is worth noting that, when it is implemented, when microcontroller 100 detects download signal, microcontroller 100 passes through JTAG
The identification code that download interface 103 detects FPGA20 refers to：When microcontroller 100 detects download signal, microcontroller 100 passes through mould
Intend the identification code of JTAG time-series rules FPGA20, likewise, microcontroller 100 deposits FPGA20 by JTAG download interfaces 103
Reservoir carries out erasing and refers to：The FLASH of ordered pair FPGA20 is wiped when microcontroller 100 is by simulating JTAG；In addition, will be with
The corresponding application program of target identification code is sent to FPGA20 by JTAG download interfaces to be referred to：Microcontroller 100 passes through JTAG
Agreement sends application program corresponding with target identification code to FPGA20, to realize the mesh that download program is carried out to FPGA20
's.
Further, when it is implemented, microcontroller 100 can use STM32F4 family chips to realize, it is preferred that should
The model STM32F407ZET6 of STM32F4 family chips, the STM32F407ZET6 chips include power on module, crystal oscillator and
Peripheral electron device, which includes but not limited to the devices such as resistance, capacitance, it is necessary to which explanation, is somebody's turn to do
Connection relation in STM32F407ZET6 chips between each device, module refers to the prior art, and details are not described herein again.
In addition, when it is implemented, memory 100 is somebody's turn to do using the storage chip realization of model IS61WV102416BLL
IS61WV102416BLL storage chips are connected with STM32F407ZET6 chips, for being carried out to the application program stored in SD card
Caching；It should be noted that the circuit structure of the IS61WV102416BLL storage chips refers to the prior art, herein no longer
Repeat.
Further, when it is implemented, electrical level transferring chip 102 can use the electrical level transferring chip of model TXB0108
Realize, which is connected with JTAG download interfaces 103 and FPGA20, is realized with this and counted between the two
According to the compatibility of varying level during transmission, its can compatible 1.2 volts, 1.5 volts, 1.8 volts, 2.5 volts, 3.3 volts etc. it is more
Kind level；In the present embodiment, realize that data pass between JTAG download interfaces 103 and FPGA20 using electrical level transferring chip 102
The compatibility of varying level when defeated, can effectively improve the versatility of the offline downloaders 10 of FPGA.
In the present embodiment, by storing multiple application programs in memory 105, when needing to FPGA20 into line program
During download, microcontroller 100 can be searched according to the identification code of the FPGA20 in the plurality of application program, when find with should
During the corresponding application program of identification code, which is downloaded in FPGA20, without computer download online, supports off line
It is offline to download, speed of download and confidentiality when improving to FPGA20 progress download programs, simple in structure, circuit stability, and
And can compatible different FPGA20, it is versatile.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the offline downloaders 10 of FPGA also wrap
Display 106 is included, the input terminal of display 106 is connected with the second output terminal of microcontroller 100.
Wherein, annotation information of the display 106 in microcontroller 100 carries out FPGA20 program download process is shown
Show.
It should be noted that in the utility model embodiment, when annotation information refers to carrying out download program to FPGA,
The information that progress, download time to download etc. are marked, it includes but not limited to the burning of the identification code of FPGA20, FPGA20
Write whether the FLASH in number, FPGA wipes the information such as successfully.
When it is implemented, display 106 can use liquid crystal display (Liquid Crystal Display, LCD), have
The display devices such as machine light emitting diode (Organic Light-Emitting Diode, OLED) are realized, do not do specific limit herein
System.
In the present embodiment, situations of the FPGA20 in program download process is shown by using display 106,
The problem of user is understood appeared in download progress, and downloading process in time, consequently facilitating user is according to corresponding
The problem of operated accordingly.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the offline downloaders 10 of FPGA also wrap
Positioning indicator 107 is included, the input terminal of positioning indicator 107 is connected with the 3rd output terminal of microcontroller 100.
Wherein, positioning indicator 107 indicates the download state of FPGA20；Wherein, download state refers to applying
Whether program is successfully downloaded to the state of FPGA20, it includes successfully and fail two states.
When it is implemented, positioning indicator 107 is realized using dual-colored LED lamp, such as red LED lamp and green LED lamp, when
When green LED lamp shines, then show that application program is successfully downloaded in FPGA20, i.e. FPGA20 burnings success；Work as red
When LED light shines, then show that application program is not downloaded in FPGA20 successfully, i.e. FPGA20 burning failures.
In the present embodiment, by using positioning indicator 107 to FPGA20 the whether successful state of download program into
Row instruction, understands download state in time easy to user.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, the offline downloaders 10 of FPGA also wrap
Include Universal Serial Bus Interface 108.
Wherein, the output terminal of Universal Serial Bus Interface 108 is connected with the input terminal of digital card interface 104, general serial
The input terminal of bus interface 104 is connected (not shown) by cable with host computer.
Specifically, multiple application programs are stored in by host computer under user's operation by Universal Serial Bus Interface 108
In digital card；When it is implemented, 108 instant USB interface of Universal Serial Bus Interface, it uses the Type B interface of USB to realize.
Further, as one preferred embodiment of the utility model, as shown in Fig. 2, power supply chip 101 includes the first electricity
Source chip 101a and second source chip 101b.
Wherein, the voltage end of the voltage end of the first power supply chip 101a and second source chip 101b constitute power supply chip
101 voltage end, the voltage end of the first power supply chip 101a and the voltage end of microcontroller 100, memory 105 voltage end and
The voltage end connection of electrical level transferring chip 102, the voltage end of second source chip 101b and the voltage end of FPGA20 connect.
Specifically, the first power supply chip 101a is microcontroller 100, electrical level transferring chip 102 and memory 105 provide confession
Piezoelectric voltage, second source chip 101b provide supply voltage for FPGA20.
When it is implemented, the 5V voltage conversions that the first power supply chip 101a powers externally fed or USB are electric into 3.3V
Pressure, and powered with the 3.3V voltages to microcontroller 100, memory 105 and electrical level transferring chip 102；Second source chip
The 5V voltage conversions that 101b powers externally fed or USB are into 3.3V voltages, and the 3.3V voltages are powered to FPGA20.
It should be noted that in the utility model implementation, the first power supply chip 101a uses the electricity of model NCP1117
Source chip realizes that second source chip 101b is realized using the power supply chip of model NCP3170, and it is worth noting that, electricity
The particular circuit configurations of source chip NCP1117 and NCP3170 refer to the prior art, and details are not described herein again.
In the utility model, by using including microcontroller, power supply chip, electrical level transferring chip, JTAG download interfaces,
The offline downloaders of FPGA of digital card interface and memory so that the offline downloaders of the FPGA are under the supply voltage of power supply chip
During work, when microcontroller detects download signal, microcontroller detects the identification code of FPGA by JTAG download interfaces, in identification code
For target identification code when, application program corresponding with target identification code will be stored in digital card and is read and is delayed into memory
Deposit, and the memory of FPGA is wiped by JTAG download interfaces, and behaviour is read out to the status register of FPGA
Make, when the state of status register is write state, application program corresponding with target identification code is passed through into JTAG download interfaces
Send to FPGA, realized with this and off line download is carried out to FPGA, its simple in structure, circuit stability, speed of download are fast, confidentiality and
It is versatile.
The above is only the preferred embodiment of the utility model only, is not intended to limit the utility model, all at this
All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model
Protection domain within.
Claims (10)
1. a kind of offline downloaders of FPGA, are connected with FPGA, it is characterised in that the offline downloaders of FPGA include：
Microcontroller, power supply chip, electrical level transferring chip, JTAG download interfaces, digital card interface and memory；
The voltage end of the voltage end of the power supply chip and the microcontroller, the voltage end of the electrical level transferring chip, described deposit
The voltage end of the voltage end of reservoir and the FPGA connect；First output terminal of the microcontroller and the JTAG download interfaces
Input terminal connection, the first output terminal of the JTAG download interfaces is connected with the first input end of the FPGA, the JTAG
Second output terminal of download interface is connected with the input terminal of the electrical level transferring chip, the output terminal of the electrical level transferring chip with
The second input terminal connection of the FPGA, the output terminal of the number card interface is connected with the input terminal of the microcontroller, described
The input/output terminal of memory is connected with the input/output terminal of the microcontroller；
The power supply chip is the microcontroller, the electrical level transferring chip, the memory and the FPGA provide power supply
Voltage；The number card interface grafting digital card, the digital card are stored with multiple application programs；When the microcontroller detects
During download signal, the microcontroller detects the identification code of the FPGA by the JTAG download interfaces, is in the identification code
During target identification code, application program corresponding with the target identification code will be stored in the digital card and is read to the storage
Cached in device, and the memory of the FPGA is wiped by the JTAG download interfaces, and to the FPGA's
Status register is read, will the described and target mark when the state of the status register is write state
Know the corresponding application program of code to send to the FPGA by the JTAG download interfaces.
2. the offline downloaders of FPGA according to claim 1, it is characterised in that the offline downloaders of FPGA further include aobvious
Show device, the input terminal of the display is connected with the second output terminal of the microcontroller；
Annotation information of the display in the microcontroller carries out the FPGA program download process is shown.
3. the offline downloaders of FPGA according to claim 1, it is characterised in that the offline downloaders of FPGA further include shape
State indicator, the input terminal of the positioning indicator are connected with the 3rd output terminal of the microcontroller；
The positioning indicator indicates the download state of the FPGA.
4. the offline downloaders of FPGA according to claim 1, it is characterised in that the offline downloaders of FPGA further include logical
With serial bus interface, the output terminal of the Universal Serial Bus Interface is connected with the input terminal of the digital card interface, described
The input terminal of Universal Serial Bus Interface is connected by cable with host computer；
The multiple application program is stored in institute by the host computer under user's operation by the Universal Serial Bus Interface
State in digital card.
5. the offline downloaders of FPGA according to any one of claims 1 to 4, it is characterised in that the model of the microcontroller
For STM32F407ZET6.
6. the offline downloaders of FPGA according to claim 1, it is characterised in that the memory is model
The storage chip of IS61WV102416BLL.
7. the offline downloaders of FPGA according to claim 1, it is characterised in that the power supply chip includes the first power supply core
Piece and second source chip；
The voltage end of the voltage end of first power supply chip and the second source chip constitutes the electricity of the power supply chip
Pressure side, the voltage end of first power supply chip and the voltage end of the microcontroller, the voltage end of the memory and described
The voltage end connection of electrical level transferring chip, the voltage end of the second source chip are connected with the voltage end of the FPGA；
First power supply chip is the microcontroller, the electrical level transferring chip and the memory provide supply voltage,
The second source chip provides supply voltage for the FPGA.
8. the offline downloaders of FPGA according to claim 7, it is characterised in that the model of first power supply chip
NCP1117。
9. the offline downloaders of FPGA according to claim 7, it is characterised in that the model of the second source chip
NCP3170。
10. the offline downloaders of FPGA according to any one of claims 7 to 9, it is characterised in that the electrical level transferring chip
Model TXB0108.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201721410019.9U CN207352599U (en) | 2017-10-27 | 2017-10-27 | A kind of offline downloaders of FPGA |
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| CN201721410019.9U CN207352599U (en) | 2017-10-27 | 2017-10-27 | A kind of offline downloaders of FPGA |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112730478A (en) * | 2020-12-24 | 2021-04-30 | 明峰医疗系统股份有限公司 | Configuration upgrading method and system of CT detector and CT scanner |
-
2017
- 2017-10-27 CN CN201721410019.9U patent/CN207352599U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112730478A (en) * | 2020-12-24 | 2021-04-30 | 明峰医疗系统股份有限公司 | Configuration upgrading method and system of CT detector and CT scanner |
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