CN207337123U - A kind of automatic calibration circuit - Google Patents
A kind of automatic calibration circuit Download PDFInfo
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- CN207337123U CN207337123U CN201721063557.5U CN201721063557U CN207337123U CN 207337123 U CN207337123 U CN 207337123U CN 201721063557 U CN201721063557 U CN 201721063557U CN 207337123 U CN207337123 U CN 207337123U
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Abstract
The utility model belongs to correcting circuit technical field,More particularly to a kind of automatic calibration circuit,Including differential-to-single-ended circuit,Level translation circuit and amplifying circuit,Further include add circuit,Analog to digital conversion circuit,Voltage reference circuit,One times of amplifying circuit,Simulation ground,First bleeder circuit,First emitter following circuit,First potentiometer,Negater circuit,Second bleeder circuit,Second emitter following circuit,Second potentiometer,Memory and processor,Solve analog correction in the prior art and use software mode,Control information is drawn according to actual measured results,The pure software bearing calibration calculated using returning,Under the correcting mode of pure software,Each product or passage,The all different problem of the correction parameter to be transferred of software,Matched again with control information is realized in circuit in a manner of hardware,Achieve the purpose that correction,Software need not carry out participating in calibration calculating during collection,So software can accomplish it is general.
Description
Technical field
The utility model belongs to correcting circuit technical field, and in particular to a kind of automatic calibration circuit.
Background technology
For analog acquisition circuit, there are in fact zero and float needs to correct with two kinds of errors of the linearity.Both errors are come
Source is substantially due to capacitance resistance ware precision and PCB parasitic parameters etc. on analog device discreteness, passage.So adopted in simulation
The higher occasion of collection precision, need to be corrected parameter, and need in application process to be corrected calculating by correction parameter.
General analog correction uses software mode, draws control information according to actual measured results, is calculated using recurrence
Pure software bearing calibration.Under the correcting mode of pure software, each product or the correction parameter to be transferred of passage, software
It is all different.
Control information is realized and matched again by the utility model in circuit in a manner of hardware, achievees the purpose that correction,
Software need not carry out participating in calibration calculating during collection.So software can accomplish it is general.
Utility model content
The purpose of the utility model is to overcome analog correction in the prior art to use software mode, according to actual measured results
Draw control information, using returning the pure software bearing calibration that calculates, under the correcting mode of pure software, each product or logical
The all different problem of the correction parameter to be transferred of road, software.
For this reason, the utility model provides a kind of automatic calibration circuit, including differential-to-single-ended circuit, level translation circuit
And amplifying circuit, differential-to-single-ended circuit, level translation circuit and amplifying circuit are sequentially connected in series, further include add circuit,
Analog to digital conversion circuit, voltage reference circuit, one times of amplifying circuit, simulation ground, the first bleeder circuit, the first emitter following circuit, first
Potentiometer, negater circuit, the second bleeder circuit, the second emitter following circuit, the second potentiometer, memory and processor, described puts
The input terminal of big circuit output end connection add circuit, the output terminal of add circuit are sequentially connected in series analog to digital conversion circuit and place
Manage device, the output terminal of voltage reference circuit connects the input terminal, anti-of the input terminal of one times of amplifying circuit, the second bleeder circuit respectively
To the input terminal of circuit, the output terminal of one times of amplifying circuit is sequentially connected in series the first bleeder circuit, the first potentiometer and processing
Device, the input terminal of the first bleeder circuit of simulation ground connection, the output terminal of the first potentiometer are sequentially connected in series the first emitter following circuit
With the input terminal of analog to digital conversion circuit, the output terminal of negater circuit connects the input terminal of the second bleeder circuit, the second bleeder circuit
Output terminal be sequentially connected in series the second potentiometer and processor, the output terminal of the second potentiometer is sequentially connected in series the second emitter following
The input terminal of circuit and add circuit, memory connection processing device.
First bleeder circuit includes resistance R1, resistance R2 and resistance R3, and the first potentiometer includes the first potentiometer
First input end and the first potentiometer the second input terminal, the output terminal of one times of amplifying circuit be sequentially connected in series resistance R1 and
The first input end of first potentiometer, is sequentially connected in series to simulation the second input terminal of resistance R3 and the first potentiometer, resistance
R2 one end is connected between the first input end of resistance R1 and the first potentiometer, and the resistance R2 other ends are connected to resistance R3 and first
Between second input terminal of potentiometer.
Second bleeder circuit includes resistance R4, resistance R5 and resistance R6, and the second potentiometer includes the second potentiometer
First input end and the second potentiometer the second input terminal, the output terminal of voltage reference circuit be sequentially connected in series resistance R4 and
The first input end of second potentiometer, it is defeated that the output terminal of negater circuit is sequentially connected in series resistance R6 and the second of the second potentiometer
Enter end, resistance R5 one end is connected between the first input end of resistance R4 and the second potentiometer, and the resistance R5 other ends are connected to electricity
Hinder between R6 and the second input terminal of the second potentiometer.
First potentiometer and the second potentiometer is digital regulation resistance.
The resistance R1 and resistance R3 is equal, and resistance R1 is more than resistance R2.
The resistance R4 and resistance R6 is equal, and resistance R4 is more than resistance R5.
Digital regulation resistance includes digital end, the output terminal of digital end connection processing device.
The beneficial effects of the utility model:This automatic calibration circuit provided by the utility model, by control information with hard
The mode of part is realized in circuit to be matched again, achievees the purpose that correction, and software need not carry out participating in calibration calculating during collection,
So software can accomplish it is general.
Brief description of the drawings
The utility model is described in further details below with reference to attached drawing.
Fig. 1 is the principle schematic of automatic calibration circuit.
Embodiment
Embodiment 1:
As shown in Figure 1, a kind of automatic calibration circuit, including differential-to-single-ended circuit, level translation circuit and amplifying circuit,
Differential-to-single-ended circuit, level translation circuit and amplifying circuit are sequentially connected in series, it is characterised in that:Further include add circuit,
Analog to digital conversion circuit, voltage reference circuit, one times of amplifying circuit, simulation ground, the first bleeder circuit, the first emitter following circuit, first
Potentiometer, negater circuit, the second bleeder circuit, the second emitter following circuit, the second potentiometer, memory and processor, described puts
The input terminal of big circuit output end connection add circuit, the output terminal of add circuit are sequentially connected in series analog to digital conversion circuit and place
Manage device, the output terminal of voltage reference circuit connects the input terminal, anti-of the input terminal of one times of amplifying circuit, the second bleeder circuit respectively
To the input terminal of circuit, the output terminal of one times of amplifying circuit is sequentially connected in series the first bleeder circuit, the first potentiometer and processing
Device, the input terminal of the first bleeder circuit of simulation ground connection, the output terminal of the first potentiometer are sequentially connected in series the first emitter following circuit
With the input terminal of analog to digital conversion circuit, the output terminal of negater circuit connects the input terminal of the second bleeder circuit, the second bleeder circuit
Output terminal be sequentially connected in series the second potentiometer and processor, the output terminal of the second potentiometer is sequentially connected in series the second emitter following
The input terminal of circuit and add circuit, memory connection processing device.
Preferable analog acquisition link, mathematical model y=k+b, k represents slope, b represents intercept.But due to reality
Circuit and ideal model difference, mathematical model y=k1`x+b1.It is respectively by k to correct the purpose to be reached1`Move to
K and b1B is moved to, both changing values to be corrected are respectively δ k and δ b.
The actual mathematical model of trimming process is y=k+b=(k1`+δk)x+(b1+δb).So our bearing calibration is real
What is completed on border is that this mathematical formulae is realized in a manner of hardware circuit.
Bearing calibration:
The digital quantity of the output terminal of first digital regulation resistance and the second digital regulation resistance (i.e. centre tap position) is stored in
Inside memory, initial default value chooses the midpoint of digital regulation resistance.Processor is read from memory when system electrification
The digital quantity of the centre tap position of first digital regulation resistance and the second digital regulation resistance, is output to the first digital regulation resistance and
The digital end of two digital regulation resistances, controls the first digital regulation resistance and the second digital regulation resistance centre tap position.
In the case of initial default value, analog-digital converter input is connected to simulation ground, hand over word is can obtain, will analyze
Signal hand over word and both theoretical signal hand over words difference work back to the analogue value, you can draw offset voltage value;According to mistake
Adjust magnitude of voltage to change the second digital regulation resistance centre tap position, offset voltage is adjusted to zero, reaches correction analog link section
Away from purpose;After adjusting, the digital quantity of the centre tap position of the second digital regulation resistance after renewal is write into storage again
Device, treat next system electrification read, control again digital regulation resistance 2 centre tap position can automatic correction system intercept, i.e.,
b1To the migration of b.
Corrected in system intercept, and the centre tap of the first digital regulation resistance is in the case of digital regulation resistance midpoint,
In analog-digital converter input terminal input hypothesis full range voltage, hand over word can obtain;Analyze full scale hand over word and theoretical full amount
The hand over word of journey, both are compared and can obtain a reference source value to be adjusted;According to the value to be adjusted change the first numeral electricity
Position device centre tap position, reference voltage value is adjusted, achievees the purpose that to correct analog link slope;, will more after adjusting
The digital quantity of the centre tap position of the first digital regulation resistance after new writes memory again, treat next system electrification read again,
Control the centre tap position of the first digital regulation resistance can automatic correction system slope, i.e. k1`To the migration of k.Correction is completed.
Control information is realized and matched again by the utility model in circuit in a manner of hardware, achievees the purpose that correction,
Software need not carry out participating in calibration calculating during collection, and software can be general.
Embodiment 2:
As shown in Figure 1, on the basis of embodiment 1, first bleeder circuit includes resistance R1, resistance R2 and resistance
R3, the first potentiometer include the first input end of the first potentiometer and the second input terminal of the first potentiometer, one times of amplifying circuit
Output terminal be sequentially connected in series the first input end of resistance R1 and the first potentiometer, simulation ground be sequentially connected in series resistance R3 with
Second input terminal of the first potentiometer, resistance R2 one end are connected between the first input end of resistance R1 and the first potentiometer, electricity
The resistance R2 other ends are connected between resistance R3 and the second input terminal of the first potentiometer;The resistance R1 and resistance R3 is equal,
Resistance R1 is more than resistance R2;
k1`Move to k:
Theory analysis:For analog acquisition link, digital quantization process is generally realized with analog-digital converter, and analog-to-digital conversion
Device be actually using a reference source for standard progress ratio quantization, so during actual acquisition analog-digital converter entrance potential
Maximum is actually equal with a reference source, and proportionality coefficient is generally 1.Change a reference source can realize slope k, reach k1`To k
Migration.
Circuit is realized:After a reference source output is realized one times of amplification in the same direction, passing through resistance (R1 and R3, and R1 two big
It is equal with R3) small resistor (R2) carry out series connection partial pressure to simulation, and small resistor is between two big resistance, i.e. partial pressure in figure
Circuit 1.The voltage at both ends is that a reference source voltage adds a small variation respectively so on small resistorA small variation is subtracted with a reference source voltageThe digital regulation resistance 1 and R2 of rear end carry out parallel connection, so in digital current potential
The exportable voltage range of device centre tap is VaTo VbBetween, output accuracy is (Va-Vb)/n, wherein n are the resolution of potentiometer
Rate.The centre tap of potentiometer 1 is connected to analog-digital converter reference voltage input terminal by emitter following circuit.It can thus pass through
The tap position of controlling potential device 1 achievees the purpose that to change analog-digital converter reference voltage, simple in structure, easy to operate.
Embodiment 3
Such as Fig. 1, on the basis of embodiment 2, second bleeder circuit includes resistance R4, resistance R5 and resistance R6,
The first input end of second potentiometer including the second potentiometer and the second input terminal of the second potentiometer, voltage reference circuit it is defeated
Outlet is sequentially connected in series the first input end of resistance R4 and the second potentiometer, and the output terminal of negater circuit is sequentially connected in series electricity
Hinder the second input terminal of R6 and the second potentiometer, resistance R5 one end be connected to resistance R4 and the second potentiometer first input end it
Between, the resistance R5 other ends are connected between resistance R6 and the second input terminal of the second potentiometer;The resistance R4 and resistance R6
Equal, resistance R4 is more than resistance R5;
b1Move to b:
Theory analysis:For analog acquisition link, when in analog link input port, input is simulates ground, analog-to-digital conversion
The hand over word of device is generally not zero.Said in general definition, the magnitude of voltage that this hand over word inverse being not zero goes out, lacks of proper care for link
Voltage.It is zero, it can be achieved that the correction of intercept to correct offset voltage, i.e., by b1Move to b.
Circuit is realized:A reference source output is realized reversely with subsequent, two are used between a reference source and negative a reference source
Big small resistor (R5) of resistance (R4 and R6, and R4 and R6 are equal) carries out series connection partial pressure, small resistor between two big resistance,
Bleeder circuit 2 i.e. in figure.The voltage at both ends is that a reference source voltage adds a small variation respectively so on small resistorA small variation is subtracted with a reference source voltageThe second potentiometer and R5 of rear end carry out parallel connection, so exist
The exportable voltage range of digital regulation resistance centre tap is VcTo VdBetween, output accuracy is (Vc-Vd)/n, wherein n are current potential
The resolution ratio of device.The centre tap of potentiometer 2 is connected to an input terminal of adder by emitter following circuit.It can thus lead to
The tap position for crossing controlling potential device 2 achievees the purpose that to change link offset voltage, simple in structure, easy to operate.
First potentiometer and the second potentiometer is digital regulation resistance, and digital regulation resistance is reproducible, after adjustment
Resistance value from such environmental effects such as temperature, humidity, pressure, and anti-moistening, shock resistance, service life length.
Digital regulation resistance includes digital end, the output terminal of digital end connection processing device, digital end be used to receiving processor from
Memory reads the digital quantity of the centre tap position of the first potentiometer and the second potentiometer, so as to control the first potentiometer and the
Two potentiometer centre tap positions, it is simple and convenient, it is real-time.
Differential-to-single-ended circuit described in the utility model, level translation circuit, amplifying circuit, add circuit, modulus turn
Change circuit, voltage reference circuit, one times of amplifying circuit, simulation ground, the first emitter following circuit, the first potentiometer, negater circuit, second
Emitter following circuit, the second potentiometer, memory and processor are available circuit, are not described extensively herein.
Exemplified as above is only for example, not forming to the scope of protection of the utility model to the utility model
Limitation, it is every to be belonged to the same or similar design of the utility model within the scope of protection of the utility model.
Claims (6)
1. a kind of automatic calibration circuit, including differential-to-single-ended circuit, level translation circuit and amplifying circuit, difference turns single-ended electricity
Road, level translation circuit and amplifying circuit are sequentially connected in series, it is characterised in that:Further include add circuit, analog to digital conversion circuit,
Voltage reference circuit, one times of amplifying circuit, simulation ground, the first bleeder circuit, the first emitter following circuit, reversely the first potentiometer, electricity
Road, the second bleeder circuit, the second emitter following circuit, the second potentiometer, memory and processor, the amplification circuit output end connect
The input terminal of add circuit is connect, the output terminal of add circuit is sequentially connected in series analog to digital conversion circuit and processor, voltage reference
The output terminal of circuit connects the input of the input terminal of one times of amplifying circuit, the input terminal of the second bleeder circuit, negater circuit respectively
End, the output terminal of one times of amplifying circuit are sequentially connected in series the first bleeder circuit, the first potentiometer and processor, the connection of simulation ground
The input terminal of first bleeder circuit, the output terminal of the first potentiometer are sequentially connected in series the first emitter following circuit and analog to digital conversion circuit
Input terminal, the output terminal of negater circuit connects the input terminal of the second bleeder circuit, and the output terminal of the second bleeder circuit is gone here and there successively
Connection the second potentiometer of connection and processor, the output terminal of the second potentiometer are sequentially connected in series the second emitter following circuit and add circuit
Input terminal, memory connection processing device.
2. automatic calibration circuit as claimed in claim 1, it is characterised in that:First bleeder circuit include resistance R1,
Resistance R2 and resistance R3, the first potentiometer include the first input end of the first potentiometer and the second input terminal of the first potentiometer,
The output terminal of one times of amplifying circuit is sequentially connected in series the first input end of resistance R1 and the first potentiometer, is sequentially connected in series to simulation
The second input terminal of resistance R3 and the first potentiometer is connected, it is defeated that resistance R2 one end is connected to resistance R1 and the first of the first potentiometer
Between entering end, the resistance R2 other ends are connected between resistance R3 and the second input terminal of the first potentiometer.
3. automatic calibration circuit as claimed in claim 2, it is characterised in that:Second bleeder circuit include resistance R4,
Resistance R5 and resistance R6, the second potentiometer include the first input end of the second potentiometer and the second input terminal of the second potentiometer,
The output terminal of voltage reference circuit is sequentially connected in series the first input end of resistance R4 and the second potentiometer, the output of negater circuit
End is sequentially connected in series the second input terminal of resistance R6 and the second potentiometer, and resistance R5 one end is connected to resistance R4 and the second current potential
Between the first input end of device, the resistance R5 other ends are connected between resistance R6 and the second input terminal of the second potentiometer.
4. automatic calibration circuit as claimed in claim 3, it is characterised in that:First potentiometer and the second potentiometer is equal
For digital regulation resistance.
5. automatic calibration circuit as claimed in claim 4, it is characterised in that:The resistance R1 and resistance R3 is equal, resistance
R1 is more than that resistance R2, resistance R4 and resistance R6 are equal, and resistance R4 is more than resistance R5.
6. automatic calibration circuit as claimed in claim 5, it is characterised in that:The digital regulation resistance includes digital end, number
The output terminal of word end connection processing device.
Priority Applications (1)
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CN201721063557.5U CN207337123U (en) | 2017-08-24 | 2017-08-24 | A kind of automatic calibration circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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CN201721063557.5U CN207337123U (en) | 2017-08-24 | 2017-08-24 | A kind of automatic calibration circuit |
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CN207337123U true CN207337123U (en) | 2018-05-08 |
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CN201721063557.5U Active CN207337123U (en) | 2017-08-24 | 2017-08-24 | A kind of automatic calibration circuit |
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- 2017-08-24 CN CN201721063557.5U patent/CN207337123U/en active Active
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