CN207302034U - Processor chips emulator - Google Patents
Processor chips emulator Download PDFInfo
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- CN207302034U CN207302034U CN201721237542.6U CN201721237542U CN207302034U CN 207302034 U CN207302034 U CN 207302034U CN 201721237542 U CN201721237542 U CN 201721237542U CN 207302034 U CN207302034 U CN 207302034U
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Abstract
The utility model discloses a kind of processor chips emulator, including：Monitoring module, processor core and program storage, the monitoring module is connected by debugging passage with user computer, described program memory is connected by the first normal data/address bus with monitoring module, and the monitoring module is connected by the second normal data/address bus with processor core.The utility model is able to record and shows that the code that user program performs every time performs coverage condition.
Description
Technical field
It the utility model is related to a kind of processor chips emulator.
Background technology
There is the user program of User Exploitation in processor chips, in the writing and debug of user program, used work
Tool is usually emulator.Using the emulation chip for including product treatment device chip various functions in emulator, for analog equipment
The work behavior of processor chips, emulation chip and the other components of emulator (program storage, the storage number of storage user program
According to data storage, and Integrated Development Environment on user computer etc.) coordinate the Integrated Development Environment on computer jointly real
The writing, compile, downloading of existing user program, simulation run and every debugging function.
Code implementation coverage is a kind of measurement in user program debugging, test, characterizes whole source code and is performed
The ratio and degree crossed, are the data that user is concerned about very much when debugging and testing user program, while can be used for sending out
Modern code runs winged situation.So user using emulator debug, test user program when, if can be obtained by emulator
Obtain and perform the corresponding code implementation coverage data (from starting to go to the process for stopping performing) every time, to debugging, testing generation
Code, lifting code development, testing efficiency and quality are very helpful.
Utility model content
The technical problem to be solved by the present invention is to provide a kind of processor chips emulator, is able to record and shows use
The code that family program performs every time performs coverage condition, while does not influence the speed that user program performs at full speed, ensures emulator
The uniformity of function, performance and product chips.
In order to solve the above technical problems, the processor chips emulator of the utility model, including：Monitoring module, processor
Core and program storage；
The monitoring module is connected by debugging passage with user computer, and described program memory passes through the first criterion numeral
It is connected according to/address bus with monitoring module, the monitoring module passes through the second normal data/address bus and connects with processor core
Connect.
Integrated Development Environment module is installed on the user computer.The monitoring module is opened by debugging passage with integrated
Hair environment module is connected.
It can in real time record and show in each implementation procedure of user program using the emulator of the utility model and perform
The code of which address, and code perform coverage condition, while do not influence the speed that user program performs at full speed, ensure emulation
The uniformity of device function, performance and product chips, contributes to user to judge that code is actual and performs whether scope meets expection, code
Whether execution entered abnormality processing or unintended areas, and coverage rate that code performs during test etc., facilitates user program
Exploitation, debugging and test, help to improve code development efficiency.
Brief description of the drawings
The utility model is described in further detail with reference to the accompanying drawings and detailed description：
Fig. 1 is the structure diagram of the processor chips emulator.
Embodiment
As shown in Figure 1, the processor chips emulator 1 (i.e. emulator in Fig. 1), including：Monitoring module 4, processing
Device core 3 and program storage 5, and the Integrated Development Environment module 2 on user computer.The monitoring module 4 passes through
Debugging passage 6 is connected with Integrated Development Environment module 2.Described program memory 5 passes through the first normal data/address bus 8
It is connected with monitoring module 4, the monitoring module 4 is connected by the second normal data/address bus 7 with processor core 3.Institute
Stating in monitoring module 4, there is code to perform record.
When user program is out of service in the Integrated Development Environment module 2, Integrated Development Environment module 2 can be downloaded generation
Code, the destination address and code data of personal code work are issued by debugging passage 6 to monitoring module 4, and the monitoring module 4 receives
To it is all issue code after, write by the first normal data/address bus 8 being connected with program storage 5 to program storage 5
The machine code data of access customer code statement.
In the Integrated Development Environment module 2 during user program operation, the processor core 3 by the second normal data/
Address bus 7 sends the destination address of program fetch code to monitoring module 4, and the monitoring module 4 records the destination address
Performed to code therein in record, at the same the destination address by the first normal data for being connected with program storage 5/
Address bus 8 is sent to program storage 5, and the machine code data of 5 return code sentence of program storage are to monitoring module 4, prison
Control module 4 is returned again to performs the code statement to processor core 3, processor core 3.In this way, used code is once performed at full speed
During, all each Codabar code sentence addresses for being fetched execution can all be recorded in code and perform in record, simultaneously because
Destination address has just been sent to program storage 5 by 4 record code address of monitoring module while record, is had no effect on fetching and is held
The capable time, when ensure that user program performs, function and the uniformity of performance and product chips that code fetching performs.
After user program is out of service in the Integrated Development Environment module 2, processor core 3 is also out of service, Bu Huifa
Go out program fetch code operation, the monitoring module 4 returns to its internal storage by debugging passage 6 to Integrated Development Environment module 2
Code perform record, after the completion of return, monitoring module 4 empties code therein and performs record automatically, to be transported next time
Again new code is recorded during row user program and performs address situation.Since code is that the compiling of Integrated Development Environment module 2 produces
And download action is completed, so Integrated Development Environment module 2 is to know the size and address realm of whole code, in this way,
The Integrated Development Environment module 2 can perform this full speed provided in record according to the code of acquisition and perform user program
During the address informations of all executed code statements this be calculated and be shown perform which user program sentence, and foundation
These executed sentences account for the ratio calculation of total code and show code implementation coverage, can also perform note finding code
There is the alarm for providing that code race is flown in implementation procedure during address realm right beyond personal code work in record, prompt personal code work
There is mistake in execution.
In this way, by the above process, the emulator 1 realized can in real time record and show that user program performed every time
The code of which address is performed in journey, and code performs coverage condition, and alerted when code runs and flies, while do not influence to use
The speed that family program performs at full speed, ensures the uniformity of emulator function, performance and product chips.
The Integrated Development Environment module 2 can be standard commercial Integrated Development Environment product, such as KEIL, IAR, MDK
Deng, provided by second development interface realized by the way of patch and download code address surface analysis, obtain generation
Code performs record, shows which user program sentence this performs, code implementation coverage is calculated and displayed, and provides
Code runs the alarm flown over.If self-developing Integrated Development Environment 2, these functions directly can be by upper computer software side
Formula is realized.The monitoring module 4 can be realized using general common processor chips, such as STM32 etc..The processor core 3
FPGA (Field Programmable Gate Array, that is, field programmable gate array) chip can be used to realize, program is deposited
Reservoir 5 can be realized with the logical resource of FPGA, can also be realized with single memory chip.Debugging passage 6 can use
JTAG the or SWD debugging interfaces of standard and instruction are realized, self-defined debugging interface and instruction can also be used to realize.
The utility model is described in detail above by embodiment, but these are not formed to this reality
With new limitation.In the case where not departing from the utility model principle, those skilled in the art can also make many deformations
And improvement, these also should be regarded as the scope of protection of the utility model.
Claims (4)
- A kind of 1. processor chips emulator, it is characterised in that including：Monitoring module, processor core and program storage；The monitoring module is connected by debugging passage with user computer, described program memory by the first normal data/ Address bus is connected with monitoring module, and the monitoring module is connected by the second normal data/address bus with processor core.
- 2. emulator as claimed in claim 1, it is characterised in that：Integrated Development Environment mould is installed on the user computer Block；The monitoring module is connected by debugging passage with Integrated Development Environment module.
- 3. emulator as claimed in claim 1, it is characterised in that：The monitoring module is made of general processor chip.
- 4. emulator as claimed in claim 1, it is characterised in that：The processor core fpga chip is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721237542.6U CN207302034U (en) | 2017-09-26 | 2017-09-26 | Processor chips emulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201721237542.6U CN207302034U (en) | 2017-09-26 | 2017-09-26 | Processor chips emulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN207302034U true CN207302034U (en) | 2018-05-01 |
Family
ID=62439458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201721237542.6U Active CN207302034U (en) | 2017-09-26 | 2017-09-26 | Processor chips emulator |
Country Status (1)
| Country | Link |
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| CN (1) | CN207302034U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807879A (en) * | 2017-09-26 | 2018-03-16 | 上海市信息网络有限公司 | Show the processor chips emulator of code implementation coverage |
| CN108647144A (en) * | 2018-05-10 | 2018-10-12 | 上海市信息网络有限公司 | Emulator and code execute abnormal breakpoint implementing method |
-
2017
- 2017-09-26 CN CN201721237542.6U patent/CN207302034U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107807879A (en) * | 2017-09-26 | 2018-03-16 | 上海市信息网络有限公司 | Show the processor chips emulator of code implementation coverage |
| CN108647144A (en) * | 2018-05-10 | 2018-10-12 | 上海市信息网络有限公司 | Emulator and code execute abnormal breakpoint implementing method |
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