CN207218666U - A kind of 10N systems subtraction count circuit and chip - Google Patents

Abstract

The utility model is applied to technical field of integrated circuits, there is provided a kind of 10N systems subtraction count circuit and chip.In the utility model, 10N system subtraction count circuits replace microcontroller by using lower-cost inversed module, the first frequency division counter module and the second frequency division counter module；Pulse signal is carried out anti-phase and generates rp pulse signal by inversed module；First frequency division counter module is performed from numerical value 9 to the circulation of numerical value 0 according to pulse signal and rp pulse signal subtracts counting, and exports corresponding binary-coded individual position and subtract count results；Second frequency division counter module subtracts count results execution according to a position and subtracts counting from numerical value of N 1 to the circulation of numerical value 0, and exports corresponding binary-coded ten and subtract count results.The 10N system subtraction count circuits realize that cost is low by inversed module, the first frequency division counter module and the second frequency division counter module.

Description

A kind of 10N systems subtraction count circuit and chip

Technical field

The utility model belongs to technical field of integrated circuits, more particularly to a kind of 10N systems subtraction count circuit and chip.

Background technology

Decimal subtraction tally function in electronic watch, sexagesimal subtraction count function or a centesimal system subtraction meter at present Number function is generally realized by microcontroller, but the cost of microcontroller is higher, therefore, 10N systems (N >=1 in electronic watch And be integer, 10N systems include the decimal system and metric multiple system) cost of subtraction count module is also higher.

Therefore, the 10N system subtraction count module reason microcontroller implementations in existing electronic watch and cost to be present high Problem.

Utility model content

The purpose of this utility model is to provide a kind of 10N systems subtraction count circuit and chip, it is intended to solves existing electricity 10N system subtraction count module reason microcontroller implementations in sublist and the problem of cost is high be present.

The utility model is achieved in that a kind of 10N systems subtraction count circuit, the 10N systems subtraction count electricity The input return pulse signal on road, wherein, N is the integer more than or equal to 1, and the 10N systems subtraction count circuit includes：

The pulse signal is subjected to inversed module that is anti-phase and generating rp pulse signal；

Performed according to the pulse signal and the rp pulse signal from numerical value 9 to the circulation of numerical value 0 and subtract counting, and it is defeated Go out the first frequency division counter module that corresponding binary-coded individual position subtracts count results；The first frequency division counter module it is same Phase input and inverting input are connected with the output end and input of the inversed module respectively；

Count results execution is subtracted according to the individual position and subtracts counting from numerical value of N -1 to the circulation of numerical value 0, and exports corresponding two Ten of scale coding subtract the second frequency division counter module of count results；The input of the second frequency division counter module with it is described The output end of first frequency division counter module is connected；

Described ten subtract count results and the individual position subtracts count results and forms subtracting for the 10N systems subtraction count circuit Count results.

Another object of the present utility model, which also resides in, provides a kind of chip for including above-mentioned 10N systems subtraction count circuit.

In the utility model, 10N system subtraction count circuits are counted by using lower-cost inversed module, the first frequency dividing Digital-to-analogue block and the second frequency division counter module replace microcontroller；Pulse signal is carried out anti-phase and generates rp pulse by inversed module Signal；First frequency division counter module is performed from numerical value 9 to the circulation of numerical value 0 according to pulse signal and rp pulse signal subtracts meter Number, and export corresponding binary-coded individual position and subtract count results；Second frequency division counter module subtracts count results according to a position Perform and subtract counting from numerical value of N -1 to the circulation of numerical value 0, and export corresponding binary-coded ten and subtract count results.The 10N System subtraction count circuit realizes that cost is low by inversed module, the first frequency division counter module and the second frequency division counter module.

Brief description of the drawings

Fig. 1 is the structure chart for the 10N system subtraction count circuits that the utility model embodiment provides；

Fig. 2 is the structure chart for the 10N system subtraction count circuits that another embodiment of the utility model provides；

Fig. 3 is that the first frequency division counter module is shown in the 10N system subtraction count circuits that the utility model embodiment provides Example circuit diagram；

Fig. 4 is that the second frequency division counter module is shown in the 10N system subtraction count circuits that the utility model embodiment provides Example circuit diagram；

Fig. 5 is the input signal of 60 system subtraction count circuits and the ripple of output signal that the utility model embodiment provides Shape figure；

Fig. 6 is the second frequency division counter module in the 10N system subtraction count circuits that another embodiment of the utility model provides Exemplary circuit figure；

Fig. 7 is the input signal and output signal for the 100 system subtraction count circuits that the utility model embodiment provides Oscillogram；

Fig. 8 is the exemplary circuit of the first two divided-frequency unit in the first frequency division counter module that the utility model embodiment provides Figure；

Fig. 9 is that the first D inputs showing for two divided-frequency unit in the first frequency division counter module that the utility model embodiment provides Example circuit diagram.

Embodiment

In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining The utility model, it is not used to limit the utility model.

Fig. 1 shows the structure for the 10N system subtraction count circuits that the utility model embodiment provides, for the ease of saying It is bright, the part related to the utility model is illustrate only, details are as follows：

As the preferred embodiment of the utility model one, the input return pulse signal of 10N system subtraction count circuits, its In, N is the integer more than or equal to 1, and 10N system subtraction counts circuit includes inversed module 100, the first frequency division counter module 200 And the second frequency division counter module 300.

Inversed module 100 is used to carry out anti-phase by pulse signal and generate rp pulse signal.

Specifically, inversed module 100 is phase inverter.

First frequency division counter module 200 is used to be performed from numerical value 9 to numerical value 0 according to pulse signal and rp pulse signal Circulation subtracts counting, and exports corresponding binary-coded individual position and subtract count results；First frequency division counter module 200 it is same mutually defeated Enter end and inverting input is connected with the output end and input of inversed module 100 respectively.

Specifically, the first frequency division counter module 200 proceeds by from numerical value 9 subtracts counting, the first frequency division counter module 200 is every Receive a pulse in pulse signal, just perform the counting that once subtracts one, until subtracting count results as after numerical value 0, again from Numerical value 9, which proceeds by, subtracts counting, and so circulation subtracts counting.Since numerical value 9, the counting that subtracts one successively, until subtracting count results and being Numerical value 0, the corresponding binary-coded count results that subtract are during the counting that gradually subtracts one：Numerical value 9, numerical value 8, numerical value 7, numerical value 6, Numerical value 5, numerical value 4, numerical value 3, numerical value 2, numerical value 1 and binary coding corresponding to numerical value 0 subtract count results be followed successively by 1001, 1000、0111、0110、0101、0100、0011、0010、0001、0000。

Second frequency division counter module 300 subtracts for subtracting count results execution according to a position from numerical value of N -1 to the circulation of numerical value 0 Count, and export corresponding binary-coded ten and subtract count results；The input and first of second frequency division counter module 300 The output end of frequency division counter module 200 is connected.

Specifically, the second frequency division counter module 300 is performed from numerical value of N -1 to the circulation of numerical value 0 counting that subtracts one, whenever first Frequency division counter module 200 subtracts since numerical value 9 count up to numerical value 0 after, the second frequency division counter module 300 just performs the meter that once subtracts one Number.Such as：Counting that the execution since numerical value 9 of first frequency division counter module 200 subtracts one, after numerical value 0 is counted up to, the second frequency dividing meter The just counting that subtracts one of the execution since numerical value of N -1 of digital-to-analogue block 300, hereafter, the first frequency division counter module 200 is again since numerical value 9 Counting that execution subtracts one, after numerical value 0 is counted up to again, the second frequency division counter module 300 performs the counting that subtracts one from numerical value of N -2, such as This circulation, until the count results that subtract of the second frequency division counter module 300 are numerical value 0.

Specifically, ten subtract count results and what position subtracted count results composition 10N system subtraction count circuits subtracts counting As a result, i.e., ten decimal values subtracted corresponding to count results subtract the decimal value corresponding to count results for 10N systems Ten, individual position subtracts decimal value corresponding to count results and subtracts decimal value corresponding to count results for 10N systems Individual position.Further specifically, the execution since numerical value 10N-1 of 10N system subtraction count circuits subtracts counting, pulse is often received A pulse in signal, the counting that once subtracts one is just performed, until subtracting count results after numerical value 0, to be opened again from numerical value 10N-1 Beginning execution subtracts counting, and so circulation subtracts counting.Such as：If N=6,10N system subtraction count circuit often receive since numerical value 59 To a pulse, the counting that subtracts one is just performed, until subtract count results as after numerical value 0, execution subtracts counting since numerical value 59 again, So circulation subtracts counting.When it is numerical value 48 to subtract count results, it is 100 that ten, which subtract count results, the decimal number corresponding to it It is worth for 4, individual position subtracts count results as 1000, and the decimal value corresponding to it is 8.

Specifically, the first output end of the first frequency division counter module 200, the second output end, the 3rd output end and the 4th are defeated The multiple output ends for going out end and the second frequency division counter module 300 are the output end of 10N system subtraction count circuits；First frequency dividing 4th output end of counting module 200 is connected with the input of the second frequency division counter module 300；Individual position subtracts in count results Highest bit value, secondary high-order numerical value, secondary low level numerical value and lowest order numerical value pass through the 4th of the first frequency division counter module 200 the respectively Output end, the 3rd output end, the second output end and the output of the first output end, ten multidigit numerical value subtracted in count results pass through the Multiple output ends output of two divided-frequency counting module 300.

In the present embodiment, the frequency division counter module 200 of inversed module 100 and first forms 10 system subtraction count sub-circuits, Inversed module 100, the first frequency division counter module 200 and the second frequency division counter module 300 collectively constitute 10N systems subtraction count electricity Road.

Fig. 2 shows the structure for the 10N system subtraction count circuits that another embodiment of the utility model provides, the first frequency dividing The reset terminal of counting module 200 and the reset terminal of the second frequency division counter module 300 connect and receive reset signal altogether, the first frequency dividing meter The frequency division counter module 300 of digital-to-analogue block 200 and second is resetted according to reset signal.

Fig. 3 shows the first frequency division counter module in the 10N system subtraction count circuits that the utility model embodiment provides 200 exemplary circuit, for convenience of description, the part related to the utility model is illustrate only, details are as follows：

First frequency division counter module 200 includes the first two divided-frequency unit U1, the second two divided-frequency unit U3, the first D inputs two Frequency unit U2, the 2nd D input two divided-frequency unit U4, the first nor gate F1, the second nor gate F2, the 3rd nor gate F3 and first Phase inverter G1.

First two divided-frequency unit U1 clock end CK1 and inversion clock end CKB1 is respectively the first frequency division counter module 200 In-phase input end and inverting input, the first two divided-frequency unit U1 output end Q1 and the first D input two divided-frequency unit U2's Clock end CK2 is connected to the 2nd D input two divided-frequency units U4 clock end CK4, the first two divided-frequency unit U1 reversed-phase output altogether QB1 and the first D inputs two divided-frequency unit U2 inversion clock end CKB2 be connected to altogether the 2nd D input two divided-frequency units U4 it is anti-phase when Clock end CKB4, the first D input two divided-frequency unit U2 output end Q2 and reversed-phase output QB2 respectively with the second two divided-frequency unit U3 Clock end CK3 be connected with inversion clock end CKB3, the first D inputs two divided-frequency unit U2 output end Q2, the second two divided-frequency Unit U3 output end Q3 and the 2nd D input two divided-frequency unit U4 output end Q4 the first inputs with the first nor gate F1 respectively End, the second input and the 3rd input are connected, and the first nor gate F1 output end is with the 2nd D input two divided-frequency units U4's Input D8 is connected, the first D input two divided-frequency units U2 output end Q2 and the second two divided-frequency unit U3 reversed-phase output QB3 is connected with the second nor gate F2 first input end and the second input respectively, the second nor gate F2 output end and Two D input two divided-frequency units U4 output end Q4 is connected with the 3rd nor gate F3 first input end and the second input respectively Connect, the 3rd nor gate F3 output end is connected with the first phase inverter G1 input, the first phase inverter G1 output end and the One D input two divided-frequency units U2 input D7 is connected, the first two divided-frequency unit U1 reset terminal R1, the second two divided-frequency unit U3 reset terminal R3, the first D input two divided-frequency unit U2 reset terminal R2 and the 2nd D input two divided-frequency unit U4 reset terminal R4 The reset terminal to form the first frequency division counter module 200 is connect altogether, and the first two divided-frequency unit U1 output end Q1, the first D input two points Frequency unit U2 output end Q2, the second two divided-frequency unit U3 output end Q3 and the 2nd D input two divided-frequency unit U4 output end Q4 is respectively the first output end, the second output end, the 3rd output end and the 4th output end of the first frequency division counter module 200.

Specifically, the first two divided-frequency unit U1 circuit structures are identical with the second two divided-frequency unit U3 circuit structure, First D input two divided-frequency units U2 circuit structure is identical with the 2nd D input two divided-frequency units U4 circuit structure.

Fig. 4 shows the second frequency division counter module in the 10N system subtraction count circuits that the utility model embodiment provides 300 exemplary circuit, for convenience of description, the part related to the utility model is illustrate only, details are as follows：

N=6 in the present embodiment, i.e., present embodiment illustrates the second frequency division counter module in 60 system subtraction count circuits 300 exemplary circuit.Second frequency division counter module 300 includes the second phase inverter G2, the 3rd two divided-frequency unit U5, the 3rd D inputs Two divided-frequency unit U6, the 4th D input two divided-frequency unit U7 and four nor gate F4.

Second phase inverter G2 input be the second frequency division counter module 300 input, the second phase inverter G2 output End and input are connected with the 3rd two divided-frequency unit U5 clock end CK5 and inversion clock end CKB5 respectively, the 3rd two divided-frequency Unit U5 output end Q5 and the 3rd D input two divided-frequency unit U6 clock end CK6 is connected to the 4th D input two divided-frequency units U7 altogether Clock end CK7, the 3rd two divided-frequency unit U5 reversed-phase output QB5 and the 3rd D input two divided-frequency unit U6 inversion clock End CKB6 is connected to the 4th D input two divided-frequency units U7 inversion clock end CKB7, the 3rd D input two divided-frequency units U6 input altogether End D9 and the 4th D input two divided-frequency units U7 output end Q7 is connected to four nor gate F4 first input ends, the 3rd D inputs two altogether Frequency unit U6 output end Q6 is connected with four nor gate F4 the second input, four nor gate F4 output end and the Four D input two divided-frequency units U7 input D10 is connected, and the 3rd two divided-frequency unit U5 reset terminal R5, the 3rd D input two points Frequency unit U6 reset terminal R6 and the 4th D input two divided-frequency unit U7 reset terminal R7 connects to form the second frequency division counter module altogether 300 reset terminal, the 3rd two divided-frequency unit U5 output end Q5, the 3rd D input two divided-frequency unit U6 output end Q6 and the 4th D Input two divided-frequency unit U7 output end Q7 be respectively the first output end of the second frequency division counter module 300, the second output end and 3rd output end, the 3rd two divided-frequency unit U5 output end Q5, the 3rd D input two divided-frequency unit U6 output end Q6 and the 4th D Input two divided-frequency unit U7 output end Q7 exports ten lowest order subtracted in count results numerical value, secondary high-order numerical value and most respectively High-order numerical value.

Specifically, the complete phase of circuit structure of the 3rd two divided-frequency unit U5 circuit structure and the first two divided-frequency unit U1 Together, the 3rd D input two divided-frequency unit U6 circuit structure and the 4th D input two divided-frequency units U7 circuit structure with the first D The circuit structure for inputting two divided-frequency unit U2 is identical.

Specifically, pulse signal H1, the first two divided-frequency unit U1 that the input of 60 system subtraction count circuits is inputted Output signal Q1, the first D input two divided-frequency unit U2 output signal Q2, the second two divided-frequency unit U3 output signal Q3, 2nd D input two divided-frequency units U4 output signal Q4, the 3rd two divided-frequency unit U5 output signal Q5, the 3rd D inputs two points Frequency unit U6 output signal Q6 and the 4th D input two divided-frequency unit U7 output signal Q7 waveform is as shown in Figure 5.Wherein, High level represents binary coding 1, and low level represents binary coding 0, and waveforms stands one subtract the counting cycle in V1 to V2 sections It is interior it is binary-coded subtract count results, i.e., subtract from numerical value 59 during counting up to numerical value 0 binary-coded subtracts count results.

Fig. 6 shows the second frequency division counter in the 10N system subtraction count circuits that another embodiment of the utility model provides The exemplary circuit figure of module 300, for convenience of description, the part related to the utility model is illustrate only, details are as follows：

N=10 in the present embodiment, i.e., present embodiment illustrates the second frequency division counter module in 100 system subtraction count circuits 300 exemplary circuit figure.Second frequency division counter module 300 includes the 3rd phase inverter G3 and the second frequency division counter submodule 301, the Three phase inverter G3 input be the second frequency division counter module 300 input, the 3rd phase inverter G3 output end and input It is connected respectively with the in-phase input end and inverting input of the second frequency division counter submodule 301, the second frequency division counter submodule 301 the first output end, the second output end, the 3rd output end and the 4th output end exports ten and subtracted in count results most respectively Low level numerical value, secondary low level numerical value, secondary high-order numerical value and highest bit value, the structure and first of the second frequency division counter submodule 301 The structure of frequency division counter module 200 is identical.

Specifically, the circuit structure of the second frequency division counter submodule 301 and the circuit structure of the first frequency division counter module 200 It is identical, the first output end, the second output end, the 3rd output end and the 4th output end of the second frequency division counter submodule 301 The first output end, the second output end, the 3rd output end and the 4th output end of the first frequency division counter module 200 are corresponded to respectively.

Specifically, 100 system subtraction count circuits since numerical value 99, often receive a pulse, just perform and once subtract One counts, until subtracting count results as after numerical value 0, execution subtracts counting since numerical value 99 again, so circulation subtracts counting.When subtracting When count results are numerical value 79, it is 0111 that ten, which subtract count results, and the decimal value corresponding to it is 7, and individual position subtracts counting knot Fruit is 1001, and the decimal value corresponding to it is 9.

Specifically, pulse signal H1, the first two divided-frequency unit U1 that the input of 100 system subtraction count circuits is inputted Output signal Q1, the first D input two divided-frequency unit U2 output signal Q2, the second two divided-frequency unit U3 output signal Q3, 2nd D input two divided-frequency units U4 output signal Q4, the first output end of the second frequency division counter submodule output signal Q1 ', the output signal Q2 ' of the second output end, the output signal Q3 ' of the 3rd output end and the output signal Q4 ' of the 4th output end As shown in Figure 7.Wherein, high level represents binary coding 1, and low level represents binary coding 0, waveforms stands in V1 to V2 sections One subtracts the binary-coded binary system for subtracting count results, i.e., subtracting during counting up to numerical value 0 from numerical value 99 counted in the cycle Coding subtracts count results.

Fig. 8 shows the first two divided-frequency unit U1 in the first frequency division counter module 200 that the utility model embodiment provides Exemplary circuit, for convenience of description, illustrate only the part related to the utility model, details are as follows：

First two divided-frequency unit U1 includes the first CMOS tube M1, the second CMOS tube M2, the 3rd CMOS tube M3, the first PMOS PM1, the second PMOS PM2, the 3rd PMOS PM3, the first NMOS tube NM1, the second NMOS tube NM2, the 3rd NMOS tube NM3, Four phase inverter G4, the 5th phase inverter G5 and the 5th nor gate F5.

5th nor gate F5 output end connects to form the first two divided-frequency unit U1's altogether with the 5th phase inverter G5 input Output end, the first CMOS tube M1 source S 1, the 3rd CMOS tube M3 phase inverter G5 of drain D 3 and the 5th output end connect shape altogether The negative pole N2 of reversed-phase output QB1, the first CMOS tube M1 positive pole P1, the second CMOS tube M2 into the first two divided-frequency unit U1, 3rd CMOS tube M3 positive pole P3 and the 3rd NMOS tube NM3 grid meet the clock end CK1 to form the first two divided-frequency unit U1 altogether, First CMOS tube M1 negative pole N1, the second CMOS tube M2 positive pole P2, the 3rd CMOS tube M3 negative pole N3 and the second PMOS PM2 Grid connect the inversion clock end CKB1 to form the first two divided-frequency unit U1, the first PMOS PM1 grid, the first NMOS tube altogether NM1 grid and the 5th nor gate F5 first input end meet the reset terminal R1 to form the first two divided-frequency unit U1 altogether, and first CMOS tube M1 drain D 1, the 4th phase inverter G4 input, the first NMOS tube NM1 drain electrode and the second NMOS tube NM2 leakage The 3rd PMOS PM3 source electrode, the 4th phase inverter G4 output end, the second CMOS tube M2 source S 2 and the 3rd are extremely connected to altogether PMOS PM3 grid is connected to the second NMOS tube NM2 grid altogether, the second CMOS tube M2 CMOS tube M3's of drain D 2 and the 3rd Source S 3 is connected to the 5th nor gate F5 the second input, the first PMOS PM1 source electrode and the second PMOS PM2 drain electrode altogether It is connected, the second PMOS PM2 source electrode is connected with the 3rd PMOS PM3 drain electrode, the first NMOS tube NM1 source electrode and Two NMOS tube NM2 source electrode is connected to the 3rd NMOS tube NM3 drain electrode altogether, and the first PMOS PM1 drain electrode is connected with power supply, the Three NMOS tube NM3 source electrode is connected with power supply.

Specifically, the frequency of the first two divided-frequency unit U1 output end Q1 output signals be the first two divided-frequency unit U1 when The half of the frequency of clock end CK1 input signals.

Fig. 9 shows the first D inputs two divided-frequency list in the first frequency division counter module 200 that the utility model embodiment provides First U2 exemplary circuit, for convenience of description, the part related to the utility model is illustrate only, details are as follows：

First D input two divided-frequency units U2 includes the 4th CMOS tube M4, the 5th CMOS tube M5, the 6th CMOS tube M6, the 4th PMOS PM4, the 5th PMOS PM5, the 6th PMOS PM6, the 4th NMOS tube NM4, the 5th NMOS tube NM5, the 6th NMOS tube NM6, hex inverter G6, the 7th phase inverter G7 and the 6th nor gate F6.

4th CMOS tube M4 source S 4 is the input D1 that the first D inputs two divided-frequency unit U2, the 6th nor gate F6's Output end and the 7th phase inverter G7 input meet the output end Q2 to form the first D input two divided-frequency units U2 altogether, and the 7th is anti-phase Device G7 output end and the 6th CMOS tube M6 drain D 6 connect the reversed-phase output to form the first D input two divided-frequency units U2 altogether QB2, the 4th CMOS tube M4 positive pole P4, the 5th CMOS tube M5 negative pole N5, the 6th CMOS tube M6 positive pole P6 and the 6th NMOS Pipe NM6 grid meets the clock end CK2 to form the first D input two divided-frequency units U2, the 4th CMOS tube M4 negative pole N4, the 5th altogether CMOS tube M5 positive pole P5, the 6th CMOS tube M6 negative pole N6 and the 5th PMOS PM5 grid connect to form the first D inputs two altogether Frequency unit U2 inversion clock end CKB2, the 4th PMOS PM4 grid, the 4th NMOS tube NM4 grid and the 6th or non- Door F6 first input end connects to form the reset terminal R2 that the first D inputs two divided-frequency unit U2 altogether, the 4th CMOS tube M4 drain D 4, Hex inverter G6 input, the 4th NMOS tube NM4 drain electrode and the 5th NMOS tube NM5 drain electrode are connected to the 6th PMOS altogether PM6 source electrode, hex inverter G6 output end, the 5th CMOS tube M5 PMOS PM6 of source S 5 and the 6th grid connect altogether In the 5th NMOS tube NM5 grid, the 4th PMOS PM4 source electrode is connected with the 5th PMOS PM5 drain electrode, the 5th PMOS Pipe PM5 source electrode is connected with the 6th PMOS PM6 drain electrode, the 4th NMOS tube NM4 source electrode and the 5th NMOS tube NM5 source The 6th NMOS tube NM6 drain electrode is extremely connected to altogether, and the 4th PMOS PM4 drain electrode is connected with power supply, the 6th NMOS tube NM6 source Pole is connected with power supply.

Application advantage based on above-mentioned 10N systems subtraction count circuit in the chips, the utility model additionally provide one kind Include the chip of above-mentioned 10N systems subtraction count circuit.

In the utility model embodiment, 10N system subtraction count circuits are by using lower-cost inversed module, first Frequency division counter module and the second frequency division counter module replace microcontroller；Pulse signal is carried out anti-phase and generated anti-by inversed module Phase pulse signal；First frequency division counter module is performed from numerical value 9 to the circulation of numerical value 0 according to pulse signal and rp pulse signal Subtract counting, and export corresponding binary-coded individual position and subtract count results；Second frequency division counter module subtracts counting according to a position As a result perform and subtract counting from numerical value of N -1 to the circulation of numerical value 0, and export corresponding binary-coded ten and subtract count results. The 10N system subtraction count circuits pass through the realization of inversed module, the first frequency division counter module and the second frequency division counter module, cost It is low.

Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model All any modification, equivalent and improvement made within the spirit and principle of utility model etc., should be included in the utility model Protection domain within.

Claims (9)

1. a kind of 10N systems subtraction count circuit, the input return pulse signal of the 10N systems subtraction count circuit, its In, N is the integer more than or equal to 1, it is characterised in that the 10N systems subtraction count circuit includes：

The pulse signal is subjected to inversed module that is anti-phase and generating rp pulse signal；

Performed according to the pulse signal and the rp pulse signal from numerical value 9 to the circulation of numerical value 0 and subtract counting, and export phase The binary-coded individual position answered subtracts the first frequency division counter module of count results；The first frequency division counter module it is same mutually defeated Enter end and inverting input is connected with the output end and input of the inversed module respectively；

Count results execution is subtracted according to the individual position and subtracts counting from numerical value of N -1 to the circulation of numerical value 0, and exports corresponding binary system Ten the second frequency division counter modules for subtracting count results of coding；The input of the second frequency division counter module and described first The output end of frequency division counter module is connected；

Described ten subtract count results and what the individual position subtracted that count results form the 10N systems subtraction count circuit subtracts counting As a result.

2. 10N systems subtraction count circuit as claimed in claim 1, it is characterised in that the first frequency division counter module The reset terminal of reset terminal and the second frequency division counter module connects and receives reset signal altogether, the first frequency division counter module and The second frequency division counter module is resetted according to the reset signal.

3. 10N systems subtraction count circuit as claimed in claim 2, it is characterised in that the first frequency division counter module First output end, the second output end, the 3rd output end and the 4th output end and the second frequency division counter module it is multiple defeated Go out output end of the end for the 10N systems subtraction count circuit；4th output end of the first frequency division counter module with it is described The input of second frequency division counter module is connected；The individual position subtracts highest bit value in count results, secondary high-order numerical value, secondary Low level numerical value and lowest order numerical value pass through the 4th output end of the first frequency division counter module, the 3rd output end, second respectively Output end and the output of the first output end, described ten multidigit numerical value subtracted in count results pass through the second frequency division counter module Multiple output ends output.

4. 10N systems subtraction count circuit as claimed in claim 3, it is characterised in that the first frequency division counter module bag Include the first two divided-frequency unit, the second two divided-frequency unit, the first D input two divided-frequencies unit, the 2nd D input two divided-frequencies unit, first Nor gate, the second nor gate, the 3rd nor gate and the first phase inverter；

The clock end of the first two divided-frequency unit is respectively the same mutually defeated of the first frequency division counter module with inversion clock end Enter end and inverting input, the output end of the first two divided-frequency unit and the clock end of the first D input two divided-frequency units It is connected to the clock end of the 2nd D input two divided-frequency unit altogether, the reversed-phase output of the first two divided-frequency unit and described the The inversion clock end of one D input two divided-frequency units is connected to the inversion clock end of the 2nd D input two divided-frequency unit altogether, and described the The output end and reversed-phase output of one D input two divided-frequency units respectively with the clock end of the second two divided-frequency unit and it is anti-phase when Zhong Duan is connected, the output end of the first D input two divided-frequency unit, the output end of the second two divided-frequency unit and described the The first input end with first nor gate, the second input and the 3rd are defeated respectively for the output end of two D input two divided-frequency units Enter end to be connected, the output end of first nor gate is connected with the input of the 2nd D input two divided-frequency units, described The output end of first D input two divided-frequency units and the reversed-phase output of the second two divided-frequency unit are respectively with described second or non- The first input end and the second input of door are connected, the output end of second nor gate and the 2nd D input two divided-frequencies The output end of unit is connected with the first input end of the 3rd nor gate and the second input respectively, the 3rd nor gate Output end be connected with the input of first phase inverter, the output end of first phase inverter and the first D are inputted The input of two divided-frequency unit is connected, the reset of the reset terminal of the first two divided-frequency unit, the second two divided-frequency unit The reset terminal at end, the reset terminal of the first D input two divided-frequency units and the 2nd D input two divided-frequency units connects to form institute altogether State the reset terminal of the first frequency division counter module, the output end of the first two divided-frequency unit, the first D input two divided-frequency units Output end, the output end of the second two divided-frequency unit and the 2nd D input two divided-frequency unit output end be respectively institute State the first output end, the second output end, the 3rd output end and the 4th output end of the first frequency division counter module.

5. 10N systems subtraction count circuit as claimed in claim 3, it is characterised in that the N=6, the second frequency dividing meter Digital-to-analogue block include the second phase inverter, the 3rd two divided-frequency unit, the 3rd D inputs two divided-frequency unit, the 4th D input two divided-frequency units and Four nor gate；

The input of second phase inverter be the second frequency division counter module input, the output of second phase inverter End and input are connected with the clock end of the 3rd two divided-frequency unit and inversion clock end respectively, the 3rd two divided-frequency list The clock end of output end and the 3rd D input two divided-frequency unit of member be connected to altogether the 4th D inputs two divided-frequency unit when Zhong Duan, the inversion clock end of the reversed-phase output and the 3rd D input two divided-frequency units of the 3rd two divided-frequency unit connect altogether In the inversion clock end of the 4th D input two divided-frequency units, the input of the 3rd D input two divided-frequency unit and described the The output end of four D input two divided-frequency units is connected to the four nor gate first input end altogether, and the 3rd D inputs two divided-frequency list First U6 output end is connected with the second input of the four nor gate, the output end of the four nor gate and described the The input of four D input two divided-frequency units is connected, and reset terminal, the 3rd D of the 3rd two divided-frequency unit input two points The reset terminal of the reset terminal of frequency unit and the 4th D input two divided-frequency units connects to form the second frequency division counter module altogether Reset terminal, the output end of the 3rd two divided-frequency unit, the output end of the 3rd D input two divided-frequency units and the 4th D The output end for inputting two divided-frequency unit is respectively the first output end of the second frequency division counter module, the second output end and the 3rd Output end, the first output end, the second output end and the 3rd output end of the second frequency division counter module export described ten respectively Position subtracts lowest order numerical value, secondary high-order numerical value and highest bit value in count results.

6. 10N systems subtraction count circuit as claimed in claim 4, it is characterised in that the N=10, second frequency dividing Counting module includes the 3rd phase inverter and the second frequency division counter submodule, and the input of the 3rd phase inverter is described second point The input of frequency counting module, the output end and input of the 3rd phase inverter respectively with the second frequency division counter submodule In-phase input end be connected with inverting input, the first output end of the second frequency division counter submodule, the second output end, 3rd output end and the 4th output end export described ten lowest order subtracted in count results numerical value, secondary low level numerical value, secondary respectively High-order numerical value and highest bit value, the structure of the structure of the second frequency division counter submodule and the first frequency division counter module It is identical.

7. 10N systems subtraction count circuit as claimed in claim 4, it is characterised in that the first two divided-frequency unit includes First CMOS tube, the second CMOS tube, the 3rd CMOS tube, the first PMOS, the second PMOS, the 3rd PMOS, the first NMOS tube, Second NMOS tube, the 3rd NMOS tube, the 4th phase inverter, the 5th phase inverter and the 5th nor gate；

The output end of 5th nor gate connects to form the first two divided-frequency unit altogether with the input of the 5th phase inverter Output end, the output end of the source electrode of first CMOS tube, the drain electrode of the 3rd CMOS tube and the 5th phase inverter is total to Connect the reversed-phase output to form the first two divided-frequency unit, the positive pole of first CMOS tube, second CMOS tube it is negative The grid of pole, the positive pole of the 3rd CMOS tube and the 3rd NMOS tube connects the clock to form the first two divided-frequency unit altogether End, the negative pole of first CMOS tube, the positive pole of second CMOS tube, the negative pole and described second of the 3rd CMOS tube The grid of PMOS connects the inversion clock end to form the first two divided-frequency unit altogether, the grid of first PMOS, described The first input end of the grid of first NMOS tube and the 5th nor gate connects the reset to form the first two divided-frequency unit altogether End, the draining of first CMOS tube, the drain electrode and described second of the input of the 4th phase inverter, first NMOS tube The drain electrode of NMOS tube is connected to the source electrode of the 3rd PMOS, output end, second CMOS tube of the 4th phase inverter altogether Source electrode and the grid of the 3rd PMOS be connected to the grid of second NMOS tube altogether, the drain electrode of second CMOS tube with The source electrode of 3rd CMOS tube is connected to the second input of the 5th nor gate, the source electrode of first PMOS and institute altogether The drain electrode for stating the second PMOS is connected, and the source electrode of second PMOS is connected with the drain electrode of the 3rd PMOS, institute State the source electrode of the first NMOS tube and the source electrode of second NMOS tube and be connected to the drain electrode of the 3rd NMOS tube altogether, described first The drain electrode of PMOS is connected with power supply, and the source electrode of the 3rd NMOS tube is connected with power supply.

8. 10N systems subtraction count circuit as claimed in claim 4, it is characterised in that the first D inputs two divided-frequency unit Including the 4th CMOS tube, the 5th CMOS tube, the 6th CMOS tube, the 4th PMOS, the 5th PMOS, the 6th PMOS, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, hex inverter, the 7th phase inverter and the 6th nor gate；

The source electrode of 4th CMOS tube be the first D input two divided-frequency unit input, the 6th nor gate it is defeated The input for going out end and the 7th phase inverter connects to form the output end that the first D inputs two divided-frequency unit altogether, and the described 7th The drain electrode of the output end of phase inverter and the 6th CMOS tube connects the anti-phase output to form the first D inputs two divided-frequency unit altogether End, the positive pole of the 4th CMOS tube, negative pole, the positive pole and the described 6th of the 6th CMOS tube of the 5th CMOS tube The grid of NMOS tube connects the clock end to form the first D input two divided-frequency unit altogether, the negative pole of the 4th CMOS tube, described The grid of the positive pole of 5th CMOS tube, the negative pole of the 6th CMOS tube and the 5th PMOS connects to form the first D altogether Input the inversion clock end of two divided-frequency unit, the grid of the 4th PMOS, the grid of the 4th NMOS tube and described the The first input end of six nor gates connects the reset terminal to form the first D inputs two divided-frequency unit altogether, the 4th CMOS tube Drain electrode, the input of the hex inverter, the drain electrode of the 4th NMOS tube and the drain electrode of the 5th NMOS tube are connected to altogether The source electrode of 6th PMOS, the output end of the hex inverter, the source electrode and the described 6th of the 5th CMOS tube The grid of PMOS is connected to the grid of the 5th NMOS tube, source electrode and the 5th PMOS of the 4th PMOS altogether Drain electrode is connected, and the source electrode of the 5th PMOS is connected with the drain electrode of the 6th PMOS, the 4th NMOS tube Source electrode and the source electrode of the 5th NMOS tube are connected to the drain electrode of the 6th NMOS tube, drain electrode and the electricity of the 4th PMOS altogether Source is connected, and the source electrode of the 6th NMOS tube is connected with power supply.

9. a kind of chip, it is characterised in that the chip includes the 10N system subtraction counts described in any one of claim 1 to 8 Circuit.