CN207217541U - Mos transistor - Google Patents

Mos transistor Download PDF

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Publication number
CN207217541U
CN207217541U CN201720578231.XU CN201720578231U CN207217541U CN 207217541 U CN207217541 U CN 207217541U CN 201720578231 U CN201720578231 U CN 201720578231U CN 207217541 U CN207217541 U CN 207217541U
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doped region
doped
opening
main surface
region
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G·M·格利瓦纳
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

It the utility model is related to MOS transistor.MOS transistor includes：Semiconductor substrate；First doped region, is overlayed on above Semiconductor substrate, there is main surface；Second doped region, extend the first distance into the first doped region；3rd doped region, extend the first distance into the first doped region, separated with the second doped region；The Part I of first doped region, in second and the 3rd between doped region, along the first distance adjacent second and the 3rd doped region；And coordination electrode, extend the first distance into the Part II of the first doped region from main surface, neighbouring Part I and in second and the 3rd between doped region, form channel region, Part I is crossed from the second doped region reach the 3rd doped region for electric current, electric current in channel region extends through Part I, and channel region passes through the distance of Part I Longitudinal extending first.The technical problem of solution is to provide the big grid width for the relatively small area for occupying semiconductor material surface.The technique effect of realization is to provide improved MOS transistor.

Description

MOS transistor
Technical field
The utility model relates generally to electronic device, more specifically, is related to semiconductor and semiconductor structure.
Background technology
Past, semi-conductor industry form MOS transistor using various method and structures.In some applications, MOS crystal Pipe needs have big channel width, to realize desired current capacity.For the transistor with transverse current, the crystal Pipe is formed with grid, and the grid has grid length between the source and drain, so as to cause between the source and drain Transverse current flows.In order to provide expectation electric current ability, grid has channel width, table of the channel width across semi-conducting material The horizontal-extending relatively large distance in face.
Vertical current transistor typically is formed with groove type grid, and wherein grid length is formed along gate lateral wall The vertical electric current for the drain electrode being flow to from source electrode along the material vertical adjacent with gate lateral wall on transistor back surface.For Offer expectation electric current ability, groove type grid are formed with grid width, the grid width equally across semiconductor material The horizontal-extending relatively large distance in surface of material.
Reduced as current requirements improve with operating voltage, the demand of larger grid width is continuously increased for forming crystalline substance The amount of the silicon area of body pipe.For for given semiconductor area, cost is higher and feature reduces.
Therefore, it is desirable to be provided with occupying the big grid width of the relatively small area on the surface of semi-conducting material method and/or Structure.
Utility model content
The technical problem that the utility model solves is to provide the big of the relatively small area on the surface for occupying semi-conducting material Grid width.
According to one side of the present utility model, there is provided a kind of MOS transistor, including：Semiconductor substrate；First doping Area, first doped region are covered in above the Semiconductor substrate, and first doped region has main surface；Second doping Area, second doped region extend the first distance into first doped region；3rd doped region, the 3rd doped region are basic On extend first distance into first doped region, the 3rd doped region is spaced apart with second doped region；Institute The Part I of the first doped region is stated, the Part I is positioned between second doped region and the 3rd doped region, The Part I of first doped region adulterates along adjacent second doped region of the described first distance and the described 3rd Area；And the coordination electrode of MOS transistor, the coordination electrode substantially from the main surface to first doped region Extend substantially described first distance in two parts, the coordination electrode is disposed adjacent to described the of first doped region A part and between second doped region and the 3rd doped region, wherein the coordination electrode is configured to form ditch Road area, it is horizontally through the Part I of first doped region from second doped region for electric current and reaches described Three doped regions, wherein the electric current in the channel region extends through the Part I of first doped region, and First distance described in the channel region through the Part I Longitudinal extending of first doped region.
In one embodiment, the coordination electrode has along between second doped region and the 3rd doped region Direction and the grid length extended laterally, and along the described first distance and the width that extends in first doped region.
In one embodiment, the coordination electrode is not covered in above the main surface of first doped region.
In one embodiment, first doped region, second doped region and the coordination electrode form three side shapes Shape, three side shape are extended in first doped region, wherein second doped region is formed in the shape of three side Side, the 3rd doped region form the opposite side of three side shape, and the coordination electrode forms the company of three side shape Side is connect, and the Part I of first doped region is extended in the opening of three side shape, wherein the opening Including by the space of three side-closeds of three side shape.
In one embodiment, first doped region, second doped region and the coordination electrode are formed in opening In, the opening is formed in first doped region.
According to one side of the present utility model, there is provided a kind of MOS transistor, including：First doped region, described first mixes Miscellaneous area has the first main surface and the second main surface, and the second main surface is oriented to relative with the described first main surface；Open Mouthful, described be open extends certain distance into first doped region；Second doped region, second doped region extend to described In opening；3rd doped region, the 3rd doped region are extended in the opening and are spaced apart with second doped region；With And it is formed the coordination electrode of the MOS transistor of the 4th doped region, the 4th doped region is extended in the opening And it is positioned between second doped region and the 3rd doped region, the coordination electrode is configured to form in source area The channel region extended laterally between drain region, the coordination electrode extend the first distance and neighbour into first doped region The channel region is connect, the coordination electrode is formed with grid length and grid width, and the grid length is substantially flat Row extends and also extended into substantially perpendicular to the described first main surface in the described first main surface extension, the grid width In first doped region of the neighbouring channel region.
In one embodiment, the coordination electrode includes grid width, and the grid width is substantially from described first Main surface extends the distance into first doped region.
According to one side of the present utility model, there is provided a kind of MOS transistor, including：First doped region, described first mixes Miscellaneous area has the first main surface and the second main surface, and the second main surface is oriented to relative with the described first main surface；The Two doped regions, second doped region is between the described first main surface and the second main surface into first doped region Extend the first distance；3rd doped region, the 3rd doped region substantially extend into first doped region described first away from From the 3rd doped region is spaced apart with second doped region；The Part I of first doped region, the Part I It is positioned between second doped region and the 3rd doped region, the Part I of first doped region is along described Adjacent 3rd doped region of first distance；And the coordination electrode of MOS transistor, the coordination electrode extend to described first In doped region, the coordination electrode is configured to form raceway groove, and the raceway groove has channel width and channel length, the raceway groove Width substantially extends the first distance between the described first main surface and the second main surface, and the channel length is substantially Parallel to the described first main surface extension, wherein the channel width is more than the channel length.
In one embodiment, the coordination electrode includes grid conductor, and the grid conductor has parallel to described Length on the direction on the first main surface, wherein the length is less than the depth that the coordination electrode enters in first doped region Degree.
According to one side of the present utility model, there is provided a kind of MOS transistor, including：Doped semiconductor materials, it is described to mix Miscellaneous semi-conducting material is positioned in first master with the first main surface and with the second main surface, the second main surface On the opposite side on surface；The first opening in the doped semiconductor materials；The first doped region in the described first opening； The second opening in the doped semiconductor materials；The second doped region in the described second opening, wherein the doping half A part for conductor material is arranged between first doped region and second doped region；In the doped semiconductor materials In the 3rd opening, wherein it is described 3rd opening be positioned at it is described first opening it is described second opening between；And described The 3rd doped region in 3rd opening, wherein the grid conductor of the MOS transistor is formed by the 3rd doped region, the 3rd doped region The part of the neighbouring doped semiconductor materials simultaneously passes through insulator and the part spaced apart, the 3rd doped region quilt It is configured to form channel region in the part of the doped semiconductor materials, wherein the channel region has substantially from institute The described first main surface of doped semiconductor materials is stated towards the described second main surface extension one of the doped semiconductor materials The width of set a distance.
The technique effect that the utility model is realized is to provide improved MOS transistor.
Brief description of the drawings
Fig. 1 shows the reality of the part according to the semiconductor devices of the present utility model including one or more transistors Apply the amplification view of the example of scheme；
Fig. 2A is shown in the example according to the embodiment of the present utility model in the method for forming semiconductor devices Some stage at Fig. 1 semiconductor devices plan；
Fig. 2 B show the cross-section parts of the semiconductor devices according to Fig. 2A of the present utility model；
Fig. 3 A- Fig. 8 B are shown according to of the present utility model in the semiconductor device formed according to Fig. 1 of the present utility model The various plans and sectional view of the semiconductor devices of Fig. 1 at each stage in the example of the embodiment of the method for part；
Fig. 9 shows the semiconductor device of the alternate embodiment according to the semiconductor devices of the present utility model for Fig. 1 The amplification view of the example of the embodiment of a part for part；
Figure 10 A are shown in the example according to the embodiment of the present utility model in the method for forming semiconductor devices Some stage at Fig. 9 semiconductor devices plan；
Figure 10 B show the cross-section parts of the semiconductor devices according to Figure 10 A of the present utility model；
Figure 11 A- Figure 17 B show the implementation according to the method for the present utility model in the semiconductor devices for forming Fig. 9 The various plans and sectional view of the semiconductor devices of Fig. 9 at each stage in the example of scheme.
To make illustrative clarity concise, the element in figure is not necessarily drawn to scale, and some elements are perhaps to carry out schematic Explanation and be exaggerated, and unless specified otherwise herein, the otherwise same reference numerals instruction identical element in different figures.This Outside, for simplicity of description, description and the details of known steps and element can be omitted.As used herein, current carrying element or current-carrying electricity Pole means the element for carrying the electric current by device of device, the source electrode of such as MOS transistor or drain electrode or bipolar transistor The emitter stage or colelctor electrode of pipe or the negative electrode or anode of diode, and control element or coordination electrode mean the control of device By the element of the electric current of device, the grid of such as MOS transistor or the base stage of bipolar transistor.An in addition, current-carrying Element can be carried in one direction by the electric current of device, such as carry the electric current into device, and the second current carrying element can carry Send in opposite direction by the electric current of device, such as carry the electric current for leaving device.Although device can be described herein For some N-channels or P-channel device or some N-types or p-type doped region, but one of ordinary skill in the art will be understood that, root It is also possible according to complementary device of the present utility model.One of ordinary skill in the art understands that conduction type refers to pass through it The mechanism conducted, such as conducted by hole or electronics, therefore, conduction type does not refer to doping concentration and refers to adulterate class Type, such as p-type or N-type.It will be understood by those of skill in the art that the phrase related to circuit operation used herein " ... period ", " ... simultaneously " and " when ... " and not exactly censure some action after initiation action Occur immediately, and refer to there may be some smaller but rational delays between the reaction that initial actuating is triggered, such as respectively Kind propagation delay.In addition, phrase " ... simultaneously " refer to one section of some action at least in initiation action time-continuing process Occur in time.It is expected close to statement value or the ginseng of position that the use of word " general " or " substantially " means that the value of element has Number.However, it is definitely all the time statement value or the little deviation of position in the presence of obstruction value or position as known in the art.This Field is it is recognized that for up at least 10 (10%) are (and for doping content of semiconductor, up to 20 percent (20%) legitimate skew that deviation) is with definitely dreamboat differs as mentioned.On signal condition in use, term " coming into force " means the effective status of signal, and term " failure " means the disarmed state of signal.The actual voltage value of signal is patrolled State (such as " 1 " or " 0 ") is collected to depend on using positive logic or negative logic.Therefore, if using positive logic, High voltage or high logic can come into force, if using negative logic, low-voltage or low logic can come into force；And if used Positive logic, then low-voltage or low state can fail, if using negative logic, high voltage or high logic can fail.At this Wen Zhong, arranged using positive logic, but it will be understood by those skilled in the art that, it can also be arranged using negative logic.Claims and/ Or term " first " in embodiment, " second ", " the 3rd " etc. are used for area (as being used in a part for element title) Point similar component, and not necessarily describe the time it is upper, spatially, in grade or any other mode order.It should be appreciated that such as The term that this is used is interchangeable in the appropriate case, and the embodiment described herein can be with except described herein or illustrate Other outside bright sequentially operate.Mention " embodiment " or " embodiment ", it is meant that describe with reference to the embodiment Specific feature, structure or characteristic be included at least one embodiment of the present utility model in.Therefore, lead in this specification The phrase " in one embodiment " that diverse location in occurs, is not necessarily all referring to same embodiment, but some In the case of, it is possible to refer to same embodiment.In addition, as clear to one of ordinary skill in the art, at one or more In individual embodiment, specific features, structure or characteristic can combine in any suitable manner.In order to which accompanying drawing clearly shows that, device The doped region of structure is shown as the turning with substantially linear edge and accurate angle.However, those skilled in the art Member understands, due to the diffusion and activation of dopant, the edge of doped region generally can not be straight line and turning can not be accurate Angle.
In addition, present specification shows a kind of cellular design to replace monolithic design, and in the cellular design, body area It is multiple cells, in monolithic design, body area is made up of the single region formed with elongated pattern (generally with serpentine pattern). However, this specification is intended to apply to both honeycomb fashion implementation and single substrate implementation.
The embodiment for suitably illustrating and describing can hereafter be lacked to any element not specifically disclosed herein, and And/or person can implement in the case where lacking any element not specifically disclosed herein.
Embodiment
Fig. 1 is shown including one or more transistors such as part for the semiconductor devices 30 of transistor 77 or 78 The amplification view of the example of embodiment.Fig. 1 shows the exemplary 30 of transistor 77 and 78, the two crystal Pipe is formed transistor unit, and the transistor unit is interconnected to form multiple-unit transistor.However, the technology of this area Personnel should be appreciated that any one of transistor 77 and 78 or both is formed as single transistor.In addition, embodiment can So that including device 30, the device is configured as including one or more transistors such as transistor 77 and/or 77, as bigger Multiple-unit transistor.The embodiment of transistor 77 can include source configuration 79, drain electrode structure 81 and grid structure 82.One In a little embodiments, each transistor can include multiple grid structures 82 or 83.The embodiment of transistor 78 can include Source configuration 80, drain electrode structure 81 and grid structure 83.In some embodiments, grid structure 82 and 83 can be substantially phase As, and source configuration 79 and 80 can be essentially similar.In embodiments, drain electrode structure 81 can be configured as crystal The public drain electrode of both pipes 77 and 78.See as discussed further below, the embodiment of transistor 77 and 78 can be configured To form channel region, the channel region has the width in the plane for the page for extending substantially into Fig. 1, and is configured with Channel length, the channel length between drain electrode structure 81 and corresponding source configuration 79 and 80 along Fig. 1 the page plane base Extended transversely with this.The general diagram of one non-restrictive illustrative embodiment of channel region is by dashed box 86 with general Mode is shown.Channel region promotes to flow to drain region from source area through channel region by the electric current of the channel region, such as passes through arrow First 84 show in typical fashion.
Fig. 2A shows the device 30 at some stage in the example of the embodiment in the method for forming device 30 Plan.Fig. 2 B show the hatching 2B-2B along Fig. 2A of device 30 cross-section parts.This description with reference to Fig. 1, Fig. 2A and Fig. 2 B.In embodiments, device 30 can be formed in Semiconductor substrate 32.Partly led for example, substrate 32 can be silicon Body substrate, its script are a parts for Silicon Wafer.Doped region 35 can be formed as being covered in above substrate 32.In some embodiment party In case, optional insulator layer 33 can be formed between substrate 32 and doped region 35.Layer 33 be formed as silica or some Other well-known insulators, such as silicon nitride etc..Doped region 35 is formed as on substrate 32 or cover it face Doped epitaxial layer.In other embodiments, area 35 is formed as the doped region in epitaxial layer, or is formed as substrate 32 Interior doped region.
Opening 36 can be formed in doped region 35, and extended distance or depth 37 into area 35.For example, opening 36 can From the first main surface in area 35 or main surface 34 into area 35 extended distance 37.In some embodiments, opening 36 can be complete Ground is formed through area 35, and in other embodiments, depth 37 is formed as the thickness in just less than area 35.For example, away from There can be various embodiments from 37, wherein distance 37 can be greater than about 20 (20) microns, or be smaller than about 300 (300) Micron, it can either be more than the 50% of the thickness in area 35 or be formed as 95% of the thickness less than area 35, or therebetween Some depth.Source configuration 79 and 80, grid structure 82 and 83 and drain electrode structure can be wherein formed by remove area 35 81 part forms opening 36.Therefore, opening 36 can be considered as multiple openings, these openings can be opened including at least three Mouthful, it is open namely for the one or more of part that wherein form grid structure, for wherein to form drain electrode structure Part one or more openings, and one or more openings of the part for wherein to form source electrode.Multiple openings It can together be formed, or can be formed in two or more operations in one operation.Opening 36 includes wherein wanting shape Into the part of grid structure 82 opening 38 and 39 and wherein to be formed grid structure 83 part opening 40.The portion in area 35 Divide the opening 38-40 for the channel region for remaining adjacent to wherein to be formed device 30.For example, in some embodiments, the post in area 35 56 and 57 may remain between respective openings 38 and 39 and opening 40, so as to allow device 30 to form the portion through post 56 and 57 The channel region divided.Channel region is formed in the part of the adjacent openings 38-40 in Hai Ke areas 35 opposite side, such as the frame 86 in Fig. 1 Shown in arrow 84.
Fig. 3 A show the device 30 at the follow-up phase in the example of the embodiment in the method for forming device 30 Plan, and Fig. 3 B show the hatching 3B-3B along Fig. 3 A of device 30 cross-section parts.Embodiment can be with Including the gate insulator 42 (Fig. 1) for the grid conductor 46 (Fig. 1) for forming grid structure 82-83.For example, embodiment can be with Including forming insulator 41 along the side wall of opening 36.The remainder of opening 36 can be filled with doped semiconductor materials 43, example Such as N doped semiconductor materials.In an exemplary embodiment, insulator 41 can by the expose portion in area 35 is aoxidized come Formed, or can be formed by depositing various insulating materials such as silicon nitride or other well-known insulating materials. Doped semiconductor materials 43 are formed as DOPOS doped polycrystalline silicon or other doped semiconductor materials.Embodiment can include material 43 It is n-type doping polysilicon.Area 35 can have embodiment, and wherein area 35 is formed as p-type semiconductor material.
Fig. 4 A show the device 30 at the later phases in the example of the embodiment in the method for forming device 30 Plan, Fig. 4 B show the hatching 4B-4B along Fig. 4 A of device 30 cross-section parts.Can be by the part of material 43 Remove, a part for material 43 is left in opening 38-40 as grid conductor 46.The removal part of material 43 forms and extended to Opening 49 in area 35.Conductor 46 is formed with grid length 47 and the substantially grid width of distance 37.This area It will be appreciated by the skilled person that grid length 47 can be configured as forming raceway groove in the part of the proximity conductor 46 in area 35, should Raceway groove has the channel length similar to length 47 and the channel width similar to the width of conductor 46.Conductor 46 also has thickness 52.Thickness 52 can extend perpendicular to electric current, it will be appreciated by those of skill in the art that thickness 52 does not interfere with the length of raceway groove The length or width of degree and/or width or grid conductor (also commonly referred to as grid length and/or grid width).
Then, in embodiments, gate insulator 42 can be formed around conductor 46.In some embodiments, may be used Insulator 42 is formed by being aoxidized to the part of conductor 46 and area 35.In other embodiments, insulating materials can be made Deposited along conductor 46.In some embodiments, the part of the side along conductor 46 of insulator 41 can be left insulation The part of body 42.
Fig. 5 A show the device 30 at the later phases in the example of the embodiment in the method for forming device 30 Plan, Fig. 5 B show the hatching 5B-5B along Fig. 5 A of device 30 cross-section parts.In some embodiments In, doped region 51 can be formed along the side wall of opening 49.Insulator 50 can be formed as being covered in the side wall of doped region 51 Face.Some embodiments can include the side wall along opening 49 and be sunk in some embodiments along the bottom of the opening Product doped semiconductor materials, such as DOPOS doped polycrystalline silicon, then aoxidize to the part of doped semiconductor materials, are mixed so as to cause Debris is spread out in the peripheral part in area 35, is consequently formed doped region 51.Or some embodiments can include along The side wall and bottom deposit doped semiconductor materials of opening 49, such as DOPOS doped polycrystalline silicon, doping material is removed from the bottom of opening 49 Material, is then aoxidized to the part of doped semiconductor materials, so as to cause dopant to be spread out to the peripheral part in area 35 In, it is consequently formed doped region 51.
Insulator 50 is formed in the side wall in oxidation operation Hai Ke areas 51.
The part in area 51 helps serve as the source electrode of device 30.
Fig. 6 A show the device 30 at the later phases in the example of the embodiment in the method for forming device 30 Plan, Fig. 6 B show the hatching 6B-6B along Fig. 6 A of device 30 cross-section parts.In some embodiments In, insulator 54 and 55 is formed as the part of adjacent insulators 42 and the end of conductor 46.In some embodiments, can incite somebody to action Insulator 50 removes.Embodiment can include forming insulator 54 and 55 in the following manner：The deposition insulation in opening 49 Body 71, such as the chemical vapor deposition of oxide or other insulated semiconductor materials (CVD), then will be heavy as shown in dotted line 53 The part of long-pending insulator removes, so as to leave insulator 54 and 55.The part of insulator 71 is removed and also can remove insulator 50 or part thereof.The remainder of opening 49 in source configuration 79 and 80 is shown as opening 59, and in drain electrode structure 81 The remainder of opening 49 be shown as opening 58.
Fig. 7 A show the device 30 at the later phases in the example of the embodiment in the method for forming device 30 Plan, Fig. 7 B show the hatching 7B-7B along Fig. 7 A of device 30 cross-section parts.Can be by extra doped region 60 form in the side wall and adjacent area 51 of opening 59.Doped region 61 is formed as abutting the insulator in source configuration 79-80 54, and doped region 62 may be formed on the inside of the opening 58 in drain electrode structure 81.Formed area 62 cause reduce opening 58 and Forming area 60-61 then causes to reduce opening 59, so as to form respective openings 63 and 64.Projection 65 may be alternatively formed to out of opening 64 Extended to through doped region 51 and 60 in the adjacent part in area 35 or at least adjacent part of exposed region 35.Doped region 60 together with Area 51 contributes to form the source area of structure 79 and 80 together, and doped region 62 and 61 helps to form the drain electrode of structure 81 Area.
Forming the example of the embodiment of area 60-62 method can include doped semiconductor materials depositing to opening 59 In, then the interior section of doped semiconductor materials is removed, so as to stay on the side of opening 59 and incite somebody to action by area 60 and 61 Area 62 is stayed on the side of opening 58 of structure 81.For example, doped polycrystalline silicon semiconductor material filling opening 59 can be used, and can The part of doped polycrystalline silicon semiconductor material is removed and leaves doped region 60-62.Remove doped polycrystalline silicon semiconductor material Projection 65 is formed available for by removing the part in area 51 and 60.
Fig. 8 A show the device 30 at the later phases in the example of the embodiment in the method for forming device 30 Plan, Fig. 8 B show the hatching 8B-8B along Fig. 8 A of device 30 cross-section parts.Can be along projection 65 Side wall form doped region 68, and the phase in the area can be extended in the adjacent part in area 35 or at least abutted from doped region 68 Adjacent part forms extra doped region 69.In an exemplary embodiment, doped region, example can be formed along the side wall of opening 64 As represented by the dashed line 66.Hereafter, device 30 is thermally processable, such as undergoes annealing process, so as to by the part of dopant from Area 68 is diffused into area 35 and/or into area 60,61 and 62, is consequently formed area 69.Area 69 help to be formed with transistor 77 and The low resistance electrical connection in 78 body area.
It can be N-type semiconductor material that embodiment, which can include area 51,.In embodiments, area 51 can be formed and area 35 Adjacent part P-N junction.P-N junction can into area 35 extended distance 37.Area 62, which can have, to be the reality of N-type semiconductor material Apply scheme.Embodiment can include the formation of area 62 and the P-N junction of the adjacent part in area 35.The P-N junction can prolong into area 35 Stretch distance 37.Area 51, which can have, to be the embodiment of heavily doped N-type silicon.The embodiment in area 35 can be that P-type silicon is relatively lightly doped. Area 69 may include to be the embodiment of heavily doped P-type silicon.
Referring back to Fig. 1, conductor material can be formed in opening 63 and 64, to provide source conductor in opening 64 74 and drain conductor 75 is provided in the opening 63.In some embodiments, conductor 74 and 75 may extend into the surface in area 35 Outside plane, to advantageously form the electrical connection with conductor 74-75.Although omitted to simplify accompanying drawing from Fig. 1, conductor 46 can be connected by covering the superincumbent conductor layer that is not shown, such as be connected by the layer of Multi-Layer Metal System, and can To be connected to gate pads therefrom.
Those skilled in the art will be appreciated from the foregoing, and the embodiment of device 30 can include grid conductor 46, The grid conductor can be configured with the grid length on the main surface (such as surface 34) that can be substantially parallel to device 30 (such as length 47).Structure 82 can also be formed with grid width, and the grid width extends into the semi-conducting material of device 30 Certain distance (such as extended distance 37 into area 35) is simultaneously also essentially perpendicular to electric current extension.
In addition, the embodiment of transistor 77 and/or 78 can be configured to form between source area and drain region Electric current channel region, wherein electric current is arranged essentially parallel to the main surface in area 35, and the substantially parallel electric current is along base Channel width in sheet perpendicular to the electric current extends and extended in the material in area 35.
It will be understood by those of skill in the art that in embodiments, the grid of device 30 can carry out shape in the following way Into：Opening is formed in area 35, forms insulator in the side wall of the opening, and in opening and adjacent insulator is formed and mixed Miscellaneous semi-conducting material.In embodiments, the source electrode of device 30 and drain electrode can also be formed in the following way：Grid is compared in formation Be open broader corresponding source electrode and drain openings, and forms doped semiconductor materials in the opening so that in drain openings Doped semiconductor materials face the doped semiconductor materials in source contact openings, and the doped semiconductor materials in gate openings exist Between source contact openings and drain openings.
From foregoing teachings, it will be understood by those of skill in the art that the embodiment of transistor can include extending to Source area in semi-conducting material.Drain region is extended in semi-conducting material, and a part for wherein semi-conducting material is arranged on source Separated between polar region and drain region and by both.Grid (including grid conductor and gate insulator) extends to semiconductor material In material, and the part of the adjacent semi-conducting material.In embodiments, source electrode can be configured to a side of adjacent gate Or a corner of the neighbouring grid, and drain and can be configured to the side or the different angles of the neighbouring grid of adjacent gate Fall.Embodiment can include the drain electrode for being basically parallel to source electrode and extending in semi-conducting material.In some embodiments, Grid is not covered in above the surface of the semi-conducting material, and is formed as extending in semi-conducting material.In embodiments, source Polar region, drain region and grid can form three side shapes, and the three sides shape extends to semiconductor material from the surface of semi-conducting material In material, wherein the side that drain electrode is formed in three side shapes, source electrode forms the opposite side of three side shapes, and grid forms three side shapes Connecting side, and semi-conducting material is extended in the opening of the three sides shape.It is U-shaped that embodiment, which can include three side shapes, Wherein grid is extended in the opening of the U-shaped in the bottom of U-shaped and semi-conducting material.
Fig. 9, which is shown, to be one of the semiconductor devices 100 of the alternate embodiment of the device 30 described in Fig. 1-Fig. 8 The amplification view of the example for the embodiment divided.In embodiments, it is for example brilliant to include one or more transistors for device 100 Body pipe 185 or 186.Fig. 9 shows the exemplary of transistor 185 and 186, and the two transistors are formed crystal Pipe unit, the transistor unit are interconnected to form multiple-unit transistor.In addition, embodiment can include device 100, institute State device to be configured as including one or more transistors such as transistor 185 and/or 186, as more most cell transistor. However, it will be understood by those of skill in the art that any one of transistor 185 and 186 or both and/or device 100 can shapes As single transistor.The embodiment of transistor 185 can include source configuration 102, drain electrode structure 104 and grid structure 103.The embodiment of transistor 186 can include source configuration 108, grid structure 107 and drain electrode structure 104.In embodiment party In case, drain electrode structure 104 can be configured as the public drain electrode of both transistors 185 and 186.See as discussed further below , the embodiment of transistor 185 and 186 can be configured to form channel region, and the channel region, which has, extends substantially into Fig. 9's Width in the plane of the page, and channel length is configured with, the channel length is in corresponding source configuration 102 and 108 The plane of the page between drain electrode structure 104 along Fig. 9 substantially transversely extends.Embodiment can include device 100 Be configured to be formed as channel width substantially to extend certain distance into device 100 from the surface of device 100, the distance with The distance that source configuration 102 extends into device 100 is substantially the same.One non-restrictive illustrative of channel region is implemented The general diagram of scheme 106 is shown at the surface of device 100 with general fashion by dashed box.Channel region promotes to pass through the ditch The electric current in road area flow to drain region from source area through channel region, as by arrow 105 in typical fashion shown in.
Figure 10 A show the device at some stage in the example of the embodiment in the method for forming device 100 100 plan.Figure 10 B show the hatching 10B-10B along Figure 10 A of device 100 cross-section parts.This description ginseng Fig. 9, Figure 10 A and Figure 10 B are examined.In embodiments, device 100 can be formed in Semiconductor substrate 112.In an example In property embodiment, substrate 112 can be substantially the same with substrate 32.Doped region 114 can be formed as being covered in substrate Above 112.In some embodiments, optional insulator layer 113 can be formed between substrate 112 and doped region 114.One In a little embodiments, area 114 can be substantially the same with area 35.It is basic that embodiment, which can include area 113 and area 33, Upper identical.
In embodiments, opening 117 and 118 can be formed in doped region 114, and the extended distance into area 114 Or depth 119.For example, opening 117 and 118 can from the first main surface in area 114 or main surface 115 into area 114 extended distance 119.In some embodiments, opening 117 and 118 can be formed completely through area 115, and in other embodiments, Depth 119 is formed as the thickness in just less than area 114.For example, distance 119 can have various embodiments, wherein distance 119 can be greater than about 20 (20) microns, are either smaller than about 300 (300) microns or can be more than the thickness in area 114 50%, either it is formed as 95% or some depth therebetween of the thickness less than area 114.Can be by removing area 114 The part of source configuration 102 and 108 wherein to be formed to form opening 117 and 118.In embodiments, the He of source configuration 102 108 will be formed in respective openings 117 and 118.The distance spaced apart of opening 117 and 118 is enough between opening 117 and 118 Form drain electrode structure 104 and grid structure 103 and 107.
Figure 11 A show the device at the follow-up phase in the example of the embodiment in the method for forming device 100 100 plan, Figure 11 B show the hatching 11B-11B along Figure 11 A of device 100 cross-section parts.Embodiment It can be included in opening 117 and 118 and form doped semiconductor area 121.In embodiments, area 121 can be used as transistor 185th, 186 body area.In embodiments, area 121 is formed as doping concentration and partly led less than the p-type of doping concentration in area 114 Body material.Area 121 can by opening 117 and 118 deposition materials formed, or by epitaxial growth or it can be passed through He forms known technology.The part in area 121 can have the embodiment in the body area for forming transistor 185 and 186.
Opening 122 can be formed in area 121, then be filled with doped semiconductor materials to form doped semiconductor area 123.For the simplification of accompanying drawing and explanation, opening 122 is shown as in transistor 185, and area 123 is shown as in crystal In pipe 186, however, opening 122 is formed in both transistors 185 and 186, and area 123 is subsequently formed at the He of transistor 185 In both 186.Area 121 and/or 123 can have the embodiment of wherein their extended distances 119 substantially into area 114.It is real The scheme of applying can include at least a portion of a part of source area that can form transistor 185 and 186 in area 123.Area 123 can So that with embodiment, the embodiment is formed as N-type region of the doping concentration more than the doping concentration in area 114, or can have Embodiment, the embodiment are formed as N-type region of the doping concentration no more than the doping concentration in area 114.
Figure 12 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 12 B show the hatching 12B-12B along Figure 12 A of device 100 cross-section parts.It can incite somebody to action Opening 127 forms the position that grid structure 103 and 107 is formed in area 114.Opening 127 is prolonged from surface 115 into area 114 Stretch certain distance.In embodiments, the distances that extend into area 114 of opening 127 and the distance that extends into area 123 be substantially It is identical, such as distance 119.Opening 127 extends laterally across area 121 and terminated near area 123.In some embodiments, Opening 127 can extend transverse to adjacent area 123.Then, insulator 130 can be formed along the side wall of opening 127.Insulator 130 can help to be formed the gate insulator of transistor 185 and 186.In order to simplify accompanying drawing, in the transversal face of transistor 185 Opening 127 is shown in point together with insulator 130, to show the formation of opening 127, however, opening 127 is also formed in transistor In 186, as shown in the line labeled as 127, these lines show the neighboring of opening 127.The remainder of opening 127 can fill There are doped semiconductor materials, to form doped region 133.Area 133 can have the embodiment party for being formed n-type doping semi-conducting material Case.Embodiment can include the doping concentration of the doping concentration more than area 114 in area 133.Area 133, which can also have, is doped to p-type The embodiment of semi-conducting material.
Figure 13 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 13 B show the hatching 13B-13B along Figure 13 A of device 100 cross-section parts.Figure 13- Figure 17 includes the step in method, and methods described may also include the optional embodiment to form device 100, the optional implementation Scheme includes the grid structure with dhield grid configuration.In some embodiments, such as not dhield grid type is included The embodiment of gauge structure, area 133 (Figure 12) can be used as the grid conductor of grid structure 103 and 107.Institute in Figure 13-Figure 17 The other parts for the step of showing can also be used for the method to form unmasked grid structure.
, can be by the part in area 133 for the optional embodiment of the transistor 185 and 186 including dhield grid conductor Remove, so as to form opening 188 in area 133, and leave the part in area 133 as grid conductor 134.For accompanying drawing and The simplification of explanation, opening 188 is shown as in a part of the grid structure 103 of transistor 185, without in transistor In 186, however, opening 188 may be formed in both transistors 185 and 186.The embodiment of grid conductor 134 is formed as It is located towards area 123 laterally (all such as parallel to surface 115) to extend in such as area 121, is used for device 100 to be formed Channel region.Conductor 134 is also vertically extended in area 114.
Shielding insulation body 136 can be formed in opening 188, to be led in conductor 134 with the optional shielding that will be subsequently formed Insulation is provided between body.In one embodiment, insulator 136 can by low-pressure chemical vapor deposition (LPCVD) operate come Formed.Insulator 136 can be silica or other kinds of insulating material.Embodiment can be included in insulator 136 Inside in formed opening 138, to receive shielded conductor.The external boundary of opening 138 is shown by line 137.Opening 138 can be in shape Into insulator 136 operation during formed, such as pass through be completely filled with insulator 136 opening 188 before stop formed Technique and formed.Or opening 138 can be used as single program to be formed, to form opening in insulator 136.For accompanying drawing With the simplification of explanation, insulator 136 and opening 138 are shown as in a part of the grid structure 103 of transistor 185, Without in transistor 186, however, insulator 136 and opening 138 are subsequently formed at transistor 185 and 186 in both.
Figure 14 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 14 B show the hatching 14B-14B along Figure 14 A of device 100 cross-section parts.It can incite somebody to action Conductor material is formed in opening 138, to form shielded conductor 135.Conductor material be formed as doped polycrystalline silicon materials or its His type conductor material.Embodiment can include leading to be formed by the way that doped semiconductor materials are deposited in opening 138 Body material.
In embodiments, it is executable to operate to expand the size in area 123.For example, the dopant material from area 123 is mixed Debris can spread into the part neighbouring with area 123 in area 114, to increase the width in area 123, such as by with identical with area 123 Conduction type doped region 131 shown in.
In addition, opening 142 can be formed to the position that drain electrode structure 104 is formed in area 114.Opening 142 is by reference number The line of the external boundary of the instruction opening 142 of word mark is shown.Opening 142 may be positioned laterally between grid structure 103 and 107. Conductor material can be formed in opening 142, to form drain conductor 143.Conductor material is formed as doped polycrystalline silicon materials Or other types conductor material.Embodiment can include can be by the way that doped semiconductor materials be deposited in opening 142 come shape Into conductor material.Opening 142 and conductor 143 are extended in area 114 from surface 115.In embodiments, opening 142 and conductor 143 can substantially into area 114 extended distance 119.
Embodiment, which can be included in source configuration 103 and 107, forms doped region 165 (Figure 16 A).In some embodiment party In case, opening 124 can be formed in area 123.The embodiment of opening 124 can help to form source electrode, be used for and source Area transistor 185 and 186 is electrically connected.Optional embodiment can include being formed as opening 124 to include projection 179, The projection extends through area 123 with a part at least exposed region 121.Projection 179 is shown in typical fashion by a dotted line.Projection 179 opening can then contribute to be formed the body contact of transistor 185 and 186.Opening 124 and/or projection 179 can be with openings 142 form simultaneously, or can be formed with different operating.
Figure 15 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 15 B show the hatching 15B-15B along Figure 15 A of device 100 cross-section parts.It can incite somebody to action Opening 145 is formed in conductor 143, and the low resistance contact with conductor 143 is formed to contribute to.Opening 145 can have substantially Extended distance 119 is to contribute to the embodiment to form low resistance contact in conductor 801 143.
Furthermore it is possible to form doped semiconductor materials along the side wall and projection 179 of opening 124, will be helpful to being formed Form the doped region 165 (Figure 16 A) in area 166.In some embodiments, it is identical conduction type in conductor 135 and area 165 In embodiment, the doped semiconductor materials for forming area 166 can be deposited during being operated with the identical of shielded conductor 135.At it In his embodiment, the part in area 165 can be removed, but do not remove projection 179 extend in area 121 or it is adjacent therewith The part of end portion office, so as to leave doped region 166.
In embodiments, insulator 130 can be configured to extend laterally across area 121, and its end separates small with area 123 Distance so that and the part of proximity 123 interior in area 121 of conductor 134 can be formed between area 123 in the part in area 121 With the channel region between insulator 130, and the channel region is set to extend through area 121, as shown in dotted line frame 106.At one In embodiment, the part retained as grid conductor 134 in area 133 can be configured as extending in area 121, and substantially Shang Yu areas 123 are spaced apart with the thickness of insulator 130, therefore, can be formed the channel region in area 121, as frame 106 Probably shown along the part of the side of insulator 130.
Transistor 185 and 186 can have embodiment, and wherein conductor 134 can be configured to form channel region (by dotted line Frame 106 is probably shown), the channel region has the width in the plane for the page for extending substantially into Figure 15 A, and is configured as With channel length, the channel length between drain electrode structure 104 (Fig. 9) and corresponding source configuration 103 and 107 (Fig. 9) along The plane of Figure 15 A page substantially transversely extends.Although the it will be understood by those of skill in the art that thickness of conductor 134 141 can be perpendicular to electric current, but thickness 141 has no influence to the length and width of raceway groove.It will be understood by those of skill in the art that The plane of the width of conductor 134 is substantially perpendicular to electric current, and the plane of the thickness of conductor 134 is also perpendicularly to electric current, but simultaneously Do not influence channel width.
Figure 16 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 16 B show the hatching 16B-16B along Figure 16 A of device 100 cross-section parts.Can be with Perform and operate so that the dopant of the dopant material from area 165 is diffused into the part of proximity 165 in area 121, so as to Doped region 166 is formed in area 121.Area 165 and/or 166 can help to be formed the body contact zone of transistor 185 and 186.From prominent The dopant of the material part of the adjacent area 131 in 179 is played by the material counter-doping in area 131, so that in the adjoining of projection 179 Area 165 is left in the part in area 121.In some embodiments, the dopant in the area 165 of the proximity 121 from projection 179 A part extend in area 121 and form doped region 166.In another embodiment, angled implant can be used Form area 166.
Figure 17 A are shown at another follow-up phase in the example of the embodiment in the method for forming device 100 The plan of device 100, Figure 17 B show the hatching 17B-17B along Figure 17 A of device 100 cross-section parts.Can be Contact openings 147 are formed in conductor 134, and can form contact openings 146 in shielded conductor 135, to advantageously form and The low resistance of grid conductor and shielded conductor electrically connects.Opening 146 and 147 is formed as exposing the surface of conductor 134 and 135, Or alternatively, it is formed as extending in the material in the area of respective conductors 134 and 135, to form large area, for carrying out electricity Connection.Embodiment can include the extended distance 119 substantially into respective conductors 134 and 138 of opening 146 and 147.
Referring back to Fig. 9, source electrode material 161 can be formed in opening 124, to be formed and the low resistance in area 123 electricity Connection, as the source electrode of device 100, and the contact of the area 164-165 in the body area for passing through device 100 is formed and area 121 Low resistance electrically connects.Embodiment, which may additionally include, forms gate electrode material 154 in opening 147, to be formed and conductor 134 Low resistance electrically connects, the grid as device 100.Embodiment, which can be included in opening 146, forms bucking electrode material 159, electrically connected with being formed with the low resistance of shielded conductor 135.Some embodiments, which can be included in opening 145, forms drain electrode Electrode material 162, electrically connected with being formed with the low resistance in area 143, the drain electrode as device 100.In other embodiments, area 143 drain electrode materials that may be connected on the basal surface of substrate 112, to form the drain electrode of device 100.At some In embodiment, material 154,159,161 and 162 can be metallic conductor.
It can be N-type semiconductor material that embodiment, which can include area 123,.In embodiments, area 123 can be device 100 Source area a part.The embodiment in area 131 is formed as p-type semiconductor material.In embodiments, area 131 can be The part in the body area of device 100.In embodiments, area 123 can form the P-N junction with the adjacent part in area 131.P-N Knot can into area 114 extended distance 119.Area 143, which can have, to be the embodiment of N-type semiconductor material.In embodiment In, area 143 can be a part for the drain region of device 100.Embodiment can include the formation of area 143 and the adjacent portions in area 114 The P-N junction divided.The P-N junction can into area 35 extended distance 119.
From all foregoing teachings, it will be understood by those of skill in the art that the example of the embodiment of MOS transistor can With including Semiconductor substrate, such as substrate 32 and/or substrate 12；First doped region, such as area 35 and/or 114, first doping Area is covered in above Semiconductor substrate, and first doped region has main surface；
Any one in second doped region, such as area 51,60 or 79, second doped region extend first into the first doped region Distance；Any one in 3rd doped region, such as area 61,62 or 87, the 3rd doped region substantially extends into the first doped region First distance, the 3rd doped region are spaced apart with the second doped region；
The Part I of first doped region, such as part 86, the Part I are positioned at the second doped region and the 3rd doping Between area, the Part I of first doped region abuts the second doped region and the 3rd doped region along the first distance；And
The coordination electrode of MOS transistor, for example, any one in electrode 46 and/or 134, the coordination electrode is substantially from master Surface extends substantially the first distance into the Part II of the first doped region, and the coordination electrode is disposed adjacent to the first doping The Part I in area and between the second doped region and the 3rd doped region, wherein the coordination electrode is configured to form raceway groove Area, it is horizontally through the Part I of the first doped region from the second doped region for electric current and reaches the 3rd doped region, wherein the ditch Electric current in road area extends through the Part I of the first doped region, and the channel region passes through the Part I of the first doped region The distance of Longitudinal extending first.
In embodiments, coordination electrode can have along the direction between the second doped region and the 3rd doped region and transverse direction The grid length of extension, and can be along the first distance and the width that extends in the first doped region.
Another embodiment, which can include coordination electrode, can not be covered in above the main surface of the first doped region.
Embodiment, which can include the first doped region, the second doped region and coordination electrode, can form three side shapes, three side Shape is extended in the first doped region, wherein the side that the second doped region is formed in three side shapes, the 3rd doped region forms three sides The opposite side of shape, coordination electrode forms the connecting side of three side shapes, and the Part I of the first doped region extends to three sides In the opening of shape, wherein the opening is included by the space of three side-closeds of three side shapes.
For example, three side shapes may be substantially perpendicular to the plane extension on the first main surface.
Another embodiment, which can include the first doped region, the second doped region and coordination electrode, can form in the opening, The opening is formed in the first doped region.
It is to be appreciated by one skilled in the art that forming the example of the embodiment of the method for MOS transistor can include The first doped region, such as area 35 and 114 are provided, first doped region has the first main surface and the second main surface, second master Surface is oriented to relative with the first main surface；
Opening is formed, for example, opening 36 and/or 127 or 133, the opening extends certain distance into the first doped region；Shape Into the second doped region, second doped region is extended in opening；The 3rd doped region is formed, the 3rd doped region is extended in opening And it is spaced apart with the second doped region；And
The coordination electrode of MOS transistor is formed to be extended to out as the 4th doped region, such as area 46, the 4th doped region In mouthful and it is positioned between the second doped region and the 3rd doped region, the coordination electrode is configured to form in source area and drain electrode The channel region extended laterally between area, the coordination electrode extend the first distance and adjacent channel region into the first doped region, should Coordination electrode is formed with grid length and grid width, and the grid length is arranged essentially parallel to the first main surface extension, The grid width extends and also extended into the first doped region of neighbouring channel region substantially perpendicular to the first main surface.
The embodiment of method can include channel region being formed as adjacent second doped region and the 3rd doped region.
The another embodiment of method can include the second doped region being formed as the source electrode that extends in the first doped region Area, the drain region that the 3rd doped region is formed as extending in the first doped region, and formed and be arranged on the second doped region and the Channel region between three doped regions, the wherein coordination electrode are configured to form raceway groove, for electric current from the second doped region direction 3rd doped region lateral flow, the raceway groove extend also along the depth of coordination electrode.
In embodiments, method can include forming coordination electrode, to be formed between source area and drain region laterally Ground and the channel region essentially continuously extended.
Embodiment can include being formed as coordination electrode to include grid width, and the grid width is substantially from the first master Surface extends certain distance into the first doped region.
It is to be appreciated by one skilled in the art that the example of the embodiment of MOS transistor can include the first doped region, Such as one of area 35 and/or 14, first doped region have the first main surface and the second main surface, the second main surface is positioned Into relative with the first main surface；Second doped region, such as area 69 and/or area 31, second doped region is on the first main surface and the Extend the first distance into the first doped region between two main surfaces；3rd doped region, such as area 51 and/or 143, the 3rd doping Area substantially extends the first distance into the first doped region, and the 3rd doped region is spaced apart with the second doped region；
The Part I of first doped region, for example, the part in area 86 and/or 114, the Part I are positioned at the second doping Between area and the 3rd doped region, the Part I of first doped region abuts the 3rd doped region along the first distance；And
The coordination electrode of MOS transistor, the coordination electrode are extended in the first doped region, and the coordination electrode is configured as shape Into raceway groove, the raceway groove has channel width and channel length, and the channel width is substantially on the first main surface and the second main surface Between extend the first distance, the channel length is arranged essentially parallel to the first main surface extension, and wherein channel width is more than raceway groove length Degree.
Another embodiment can include the 4th doped region, such as area 121, the 4th doped region be formed as substantially to Extend the first distance in first doped region, the 4th doped region abuts the second doped region and is arranged on the second doped region and first Between the Part I of doped region, wherein raceway groove basically laterally prolongs along the interface of the second doped region and the 4th doped region Reach in the 4th doped region, and along the interface of the second doped region and the 4th doped region substantially longitudinally extend first away from From.
The Part I that embodiment can include the first doped region can abut the second doped region, and coordination electrode can It is configured as turning into channel shape into the Part I for extending laterally across the first doped region, and is formed as the base into the first doped region The first distance is longitudinally extended on this.
In embodiments, coordination electrode can include grid conductor, and the grid conductor has parallel to the first main table Length on the direction in face, the wherein length are less than the depth that coordination electrode enters in the first doped region.
Embodiment, which can include electric current, can extend laterally across the Part I of the first doped region, and longitudinally through The Part I of first doped region extends the first distance.
In embodiments, the grid of MOS transistor can form channel region, the channel region to the first doped region first Extend the first distance in part, and the certain length of grid is extended laterally between the second doped region and the 3rd doped region.
It will be understood by those of skill in the art that the method for forming MOS transistor can include providing doped semiconductor material Material, the doped semiconductor materials are positioned in first with the first main surface and with the second main surface, the second main surface On the opposite side on main surface；The first opening is formed in doped semiconductor materials, such as is open 117；Formed in the first opening First doped region, such as area 123；The second opening is formed in doped semiconductor materials, such as is open 142；In the second opening The second doped region, such as area 143 are formed, a part for wherein doped semiconductor materials is arranged on the first doped region and the second doping Between area；The 3rd opening is formed in doped semiconductor materials, such as is open 127, wherein the 3rd opening is positioned at the first opening Between the second opening；And
The 3rd doped region, such as area 134 are formed in the 3rd opening, wherein the 3rd doped region forms the grid of MOS transistor Pole conductor, this includes forming the part of neighbouring doped semiconductor materials and by the 3rd doping of insulator and the part spaced apart Area, the 3rd doped region are configured to form channel region in the part of doped semiconductor materials, and wherein channel region has basic On the second main surface extension certain distance from the first main surface of doped semiconductor materials towards doped semiconductor materials width Degree.
The embodiment of method can include being formed as the first doped region to extend the first distance into the first opening, and 3rd doped region is formed as substantially to extend the first distance into the 3rd opening.
Embodiment can include the part that the 3rd opening shape is turned into adjacent doped semiconductor materials.
In embodiments, method can include being formed as being covered in above Semiconductor substrate by doped semiconductor materials.
Another embodiment can include being formed as all having by the first doped region, the second doped region and the 3rd doped region Identical conduction type.
Embodiment can include being formed as doped semiconductor materials into having the first conduction type, in the first opening shape Into the 4th doped region with the second conduction type, and the first doped region is formed in the 4th doped region, wherein the first doping Area, the second doped region and the 3rd doped region have the first conduction type.
It will be understood by those of skill in the art that the example of the embodiment of MOS transistor can include：
First doped region, first doped region have the first main surface and the second main surface, and the second main surface is positioned Into relative with the first main surface；
Opening, the opening extend certain distance into the first doped region；
Second doped region, second doped region are extended in opening；
3rd doped region, the 3rd doped region are extended in opening and are spaced apart with the second doped region；And
The coordination electrode of MOS transistor, the coordination electrode are formed the 4th doped region, and the 4th doped region extends to out In mouthful and it is positioned between the second doped region and the 3rd doped region, the coordination electrode is configured to form in source area and leakage The channel region extended laterally between polar region, the coordination electrode extend the first distance and adjacent channel region into the first doped region, The coordination electrode is formed with grid length and grid width, and the grid length is arranged essentially parallel to the first main surface and prolonged Stretch, the grid width extends and also extended into the first doped region of neighbouring channel region substantially perpendicular to the first main surface.
Another embodiment can include grid width, and the grid width is substantially from the first main surface to the first doped region Middle extension certain distance.
It is to be appreciated by one skilled in the art that the example of the embodiment of MOS transistor can include：
Doped semiconductor materials, the doped semiconductor materials are with the first main surface and with the second main surface, and this Two main surfaces are positioned on the opposite side on the first main surface；
First opening, first opening is in doped semiconductor materials；
First doped region, first doped region is in the first opening；
Second opening, second opening is in doped semiconductor materials；
Second doped region, in the second opening, a part for wherein doped semiconductor materials is set second doped region Between the first doped region and the second doped region；
3rd opening, for the 3rd opening in doped semiconductor materials, the wherein the 3rd opening is positioned in the first opening Between the second opening；And
3rd doped region, for the 3rd doped region in the 3rd opening, wherein the 3rd doped region forms the grid of MOS transistor Pole conductor, the 3rd doped region is adjacent to the part of doped semiconductor materials and by insulator and the part spaced apart, and this Three doped regions are configured to form channel region in the part of doped semiconductor materials, and wherein channel region has substantially from doping Width of the first main surface of semi-conducting material towards the second main surface extension certain distance of doped semiconductor materials.
In view of above-mentioned full content, it is evident that disclose a kind of novel Apparatus and method for.Among others features, in addition to The grid of MOS transistor, such as grid conductor are formed, its is necessarily there is the surface for being arranged essentially parallel to transistor and transverse direction The length of extension, and with the width in the body area for extending longitudinally into transistor and/or drift region.Therefore, channel region It is same that there is the width extended longitudinally into channel region, even if electric current is arranged essentially parallel to being formed with for semi-conducting material The main surface lateral flow of drift region.Grid width and channel width are formed as into Longitudinal extending with the length extended laterally Degree, reduce the surface area occupied by transistor of semi-conducting material.Therefore, can be formed in the given area of semi-conducting material More transistors, so as to reduce the cost of the device using MOS transistor.
Although the theme of this specification, this theory are described by specific preferred embodiment and exemplary The aforementioned figures of bright book and description depict only the Typical non-limiting example of the embodiment of theme, therefore will be not foregoing Accompanying drawing and description, which are considered as, limits its scope, and to those skilled in the art, many alternatives and modification all will be aobvious and easy See.Although device 30 and 100 is shown as the transverse current device on the top surface of device with drain electrode connection, this Field is connected alternately through the basal surface of substrate 32 and/or 112 it will be appreciated by the skilled person that draining.In device 30 In embodiment, it is convenient to omit opening 63, and area 62 extends in substrate 32 and passed therethrough.The reality of device 100 The scheme of applying can include omitting opening 145 and area 143 is extended into and through substrate 112.
All claim of following article is reflected that the feature that each side of the present utility model has can be less than and disclose above Single embodiment all features.So all claim hereafter stated is expressly incorporated in specific embodiment party hereby In formula, and each claim all represents independent embodiments of the present utility model in itself.In addition, while characterized as some Embodiment includes some features included in other embodiments, does not include other features wherein included, but this area but It will be appreciated by the skilled person that the combination of the feature of different embodiments is intended to belong to the scope of the utility model, and it is intended to shape Into different embodiments.

Claims (10)

1. a kind of MOS transistor, including：
Semiconductor substrate；
First doped region, first doped region are covered in above the Semiconductor substrate, and first doped region has main table Face；
Second doped region, second doped region extend the first distance into first doped region；
3rd doped region, the 3rd doped region substantially extend first distance into first doped region, and described Three doped regions are spaced apart with second doped region；
The Part I of first doped region, the Part I are positioned at second doped region and the 3rd doped region Between, the Part I of first doped region abuts second doped region and the described 3rd along the described first distance Doped region；And
The coordination electrode of MOS transistor, the coordination electrode substantially from the main surface to first doped region second Extend substantially described first distance in part, the coordination electrode is disposed adjacent to described the first of first doped region Partly and between second doped region and the 3rd doped region, wherein the coordination electrode is configured to form raceway groove Area, it is horizontally through the Part I of first doped region from second doped region for electric current and reaches the described 3rd Doped region, wherein the electric current in the channel region extends through the Part I of first doped region, and institute State the first distance described in channel region through the Part I Longitudinal extending of first doped region.
2. MOS transistor according to claim 1, wherein the coordination electrode have along second doped region with it is described Direction between 3rd doped region and the grid length extended laterally, and extend to described first along the described first distance and mix Width in miscellaneous area.
3. MOS transistor according to claim 1, wherein the coordination electrode is not covered in the institute of first doped region State above main surface.
4. MOS transistor according to claim 1, wherein first doped region, second doped region and the control Electrode processed forms three side shapes, and three side shape is extended in first doped region, wherein second doped region is formed Side in the shape of three side, the 3rd doped region form the opposite side of three side shape, and the coordination electrode is formed The connecting side of three side shape, and the Part I of first doped region extends to the opening of three side shape In, wherein the opening is included by the space of three side-closeds of three side shape.
5. MOS transistor according to claim 1, wherein first doped region, second doped region and the control Electrode processed is formed in the opening, and the opening is formed in first doped region.
6. a kind of MOS transistor, including：
First doped region, first doped region have the first main surface and the second main surface, and the second main surface is positioned Into relative with the described first main surface；
Opening, described be open extend certain distance into first doped region；
Second doped region, second doped region are extended in the opening；
3rd doped region, the 3rd doped region are extended in the opening and are spaced apart with second doped region；And
It is formed the coordination electrode of the MOS transistor of the 4th doped region, the 4th doped region extends to the opening In and be positioned between second doped region and the 3rd doped region, the coordination electrode is configured to form in source electrode The channel region extended laterally between area and drain region, the coordination electrode extend into first doped region first distance and The adjacent channel region, the coordination electrode are formed with grid length and grid width, and the grid length is substantially Parallel to the described first main surface extension, the grid width extends substantially perpendicular to the described first main surface and also extended Into first doped region of the neighbouring channel region.
7. MOS transistor according to claim 6, wherein the coordination electrode includes grid width, the grid width Substantially extend the distance into first doped region from the described first main surface.
8. a kind of MOS transistor, including：
First doped region, first doped region have the first main surface and the second main surface, and the second main surface is positioned Into relative with the described first main surface；
Second doped region, second doped region are mixed between the described first main surface and the second main surface to described first Extend the first distance in miscellaneous area；
3rd doped region, the 3rd doped region substantially extend first distance into first doped region, and described Three doped regions are spaced apart with second doped region；
The Part I of first doped region, the Part I are positioned at second doped region and the 3rd doped region Between, the Part I of first doped region abuts the 3rd doped region along the described first distance；And
The coordination electrode of MOS transistor, the coordination electrode are extended in first doped region, and the coordination electrode is configured To form raceway groove, the raceway groove has channel width and channel length, and the channel width is substantially on the described first main surface Extending the first distance between the described second main surface, the channel length is arranged essentially parallel to the described first main surface extension, Wherein described channel width is more than the channel length.
9. MOS transistor according to claim 8, wherein the coordination electrode includes grid conductor, the grid conductor With the length on the direction parallel to the described first main surface, wherein the length is less than described in coordination electrode entrance Depth in first doped region.
10. a kind of MOS transistor, including：
Doped semiconductor materials, the doped semiconductor materials are with the first main surface and with the second main surface, and described Two main surfaces are positioned on the opposite side on the described first main surface；
The first opening in the doped semiconductor materials；
The first doped region in the described first opening；
The second opening in the doped semiconductor materials；
The second doped region in the described second opening a, wherein part for the doped semiconductor materials is arranged on described first Between doped region and second doped region；
In the doped semiconductor materials the 3rd opening, wherein it is described 3rd opening be positioned at it is described first opening with it is described Between second opening；And
The 3rd doped region in the described 3rd opening, wherein the grid conductor of the MOS transistor is formed by the 3rd doped region, 3rd doped region is adjacent to the part of the doped semiconductor materials and by insulator and the part spaced apart, and described Three doped regions are configured to form channel region in the part of the doped semiconductor materials, wherein the channel region has Substantially from the described first main surface of the doped semiconductor materials towards second master of the doped semiconductor materials Surface extends the width of certain distance.
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US10461028B2 (en) 2016-07-22 2019-10-29 Semiconductor Components Industries, Llc Semiconductor device including a vertical one-time programmable fuse that includes a conductive layer and a resistive material and a method of making the same

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US9466708B2 (en) 2013-03-15 2016-10-11 Semiconductor Components Industries, Llc Method of forming a transistor and structure therefor

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CN116648051A (en) * 2023-05-26 2023-08-25 长鑫存储技术有限公司 semiconductor structure and memory
CN116648051B (en) * 2023-05-26 2024-05-14 长鑫存储技术有限公司 Semiconductor structure and memory

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