CN207200605U - The more motor real-time control platforms of modularization based on DSP and FPGA - Google Patents

Abstract

The utility model discloses the more motor real-time control platforms of the modularization based on DSP and FPGA, core control panel, the analog signalses being made up of DSP and CPLD are nursed one's health and formed with sampling plate, communication board, the multiplex coding device process plate based on FPGA, the pwm pulse plate based on FPGA, power panel, bus board, IGBT drive circuit plate, and DSP core control panel is connected by bus board with communication board, analog signalses conditioning with sampling plate, encoder plate, pwm pulse plate；The pwm signal of pwm pulse plate, which exports, gives IBGT drive circuit boards；220V alternating current input power supplyings are converted into 5V by power panel, ± 15V, 24V isolated supplies are exported and powered to other control panels.The utility model can make the control of more motors have the characteristics that gathered data speed is fast, accuracy is high and compatible good.

Description

The more motor real-time control platforms of modularization based on DSP and FPGA

Technical field

The more motor real-time control platforms of modularization based on DSP and FPGA are the utility model is related to, belong to power electronics control Technical field processed.

Background technology

With China's national defense demand and industrial expansion in recent years, to the gradual of various mechanical performances and product quality requirement Improve, only the control for a motor can not meet the needs of modern high technology development in some occasions, and need People control multiple electric motors simultaneously, allow its preferably coordinated operation, such as in order to establish carrier-borne aircraft warship face landing platform, it is necessary to more Free degree motion platform system；The control of depopulated helicopter usually requires 6-dof motion platform；Servounit machining control System generally has multiple axles to need SERVO CONTROL etc..The demand of multi-motor coordination control increasingly highlights.Mould based on DSP and FPGA The more motor real-time control platforms of blockization support the synchronous drive control of up to 6 motors, and supported motor type is various, such as Threephase asynchronous machine, stepper motor, common permanent magnet DC motor, brshless DC motor, permagnetic synchronous motor, switching magnetic-resistance electricity Machine, axial magnetic field Magneticflux-switching type magneto etc..In addition, the more motor real-time control platforms of modularization based on DSP and FPGA Possess versatility, arithmetic speed and precision are high, memory data output is big, available resources can flexible expansion the advantages that, plate repeats The characteristics of utilization rate is high, it is substantially shorter the construction cycle.

Utility model content

The purpose of this utility model is to design the modularization multi_motor control platform based on DSP and FPGA, can be supported more Kind of motor type, and support the control in real time simultaneously of more motors, can carry out the mathematical operation of complexity, realize high performance control and Interface function.

Technical solution of the present utility model is：

Modularization multi_motor control platform based on DSP and FPGA, it can be compiled with scene by digital signal processor (DSP) The core control panel of journey gate array (CPLD) composition, analog signalses conditioning are compiled with sampling plate, communication board, the multichannel based on FPGA Code device process plate, the pwm pulse plate based on FPGA, power panel, bus board, insulated gate bipolar transistor (IGBT) driving electricity Road plate composition, it is characterised in that the core control panel of DSP, CPLD composition passes through bus board (data/address bus, address bus, control Signal etc.) and analog signalses conditioning be connected with sampling plate, encoder plate, pwm pulse plate；The pwm signal output of pwm pulse plate Give IGBT drive circuit plate；220V alternating current input power supplyings are converted into 5V, ± 15V, 24V isolated form out-put supply to it by power panel Its control panel is powered.

DSP is using TI company's Ts MS320C28346 Floating-point DSPs controller as master controller chip, main completion motor control Algorithm processed, photoelectric encoder plate rotating speed, steering, the reading of positional information, switching frequency, the duty of pwm pulse plate pwm signal Than, phase, dead time give；CPLD uses Xilinx companies high-performance CPLD chip XC95288XL, is used on the chip Hardware Description Language VHDL generates the chip selection signal of encoder plate, pwm pulse plate and sampling plate, and handles pwm pulse plate and connect The IGBT fault signal received.

Analog signalses are nursed one's health includes analog quantity modulate circuit and AD sampling A/D chips with sampling plate, and wherein AD sampling A/D chips are The AD7606 of ADI companies；Analog quantity modulate circuit connects with voltage hall sensor, current Hall sensor and temperature sensor Even；The output of signal conditioning circuit is connected with modulus conversion chip AD7606 input end of analog signal.Over-sampling modulate circuit is first The current signal of Hall sensor, voltage signal are first converted into voltage signal, by differential amplifier circuit and low pass filter The voltage signal that scope is ± 10V is converted into afterwards and is connected with AD7606；1mA current sources and NTC caused by over-sampling modulate circuit Thermistor, the connection of PT100 thermocouples, are converted to voltage signal by temperature signal and are connected with AD7606 chips.AD7606 moulds Number conversion chips are by analog-signal transitions into data signal, and for DSP by data/address bus, chip selection signal reads AD7606 outputs Sampled result.Every piece of analog signalses conditioning can complete the sampling of 16 road analog signalses with sampling plate, wherein 10 tunnels are compatible Voltage, the sampling of current mode Hall sensor, 6 tunnel compatibility NTC and two kinds of temperature sensor samplings of PT100.

FPGA described in coder processes plate uses Xilinx companies XC6SLX9FPGA chips, the output of photoelectric encoder Signal is connected after being isolated by high speed photo coupling with fpga chip, used optocoupler model HCPL-060L；Every block of plate can be same When complete the collection and calculating of No. 6 photoelectric encoder information, FPGA will calculate speed, position and the steering of Hou Mei roads encoder Information is by data bus transmission to dsp chip.Encoder information calculation procedure in FPGA is write using Verilog language, By 4 times of frequency modules of code device signal, encoder DSP signal strobes counter module, encoder to count module, data outputting module Composition；4 times of frequency modules of code device signal obtain encoder output arteries and veins by handling the code device signal of isolation and amplifier 4 frequency-doubled signals and direction information of punching；Encoder to count module is believed 4 frequencys multiplication of DSP signal strobes and encoder output respectively Number counted；And by the way that rotary speed information, direction information and positional information is calculated, then latched by data outputting module Read afterwards for DSP.Every piece of photoelectric encoder signal plate can complete the collection and calculating of 6 groups of code device signals.

FPGA described in pwm pulse plate uses Xilinx companies XC6SLX9FPGA chips, and FPGA receives DSP transmission PWM signal frequency, dutycycle, the information such as dead time and phase, the pwm signal with dead band is then automatically generated, and it is compatible Optical fiber and electric signal output；Pwm pulse plate receives the fault-signal of IGBT driving board output, and locking pulse, finally by number According to bus by transmitting fault information to DSP.Pwm pulse generation program in FPGA is write using Verilog language, by data Receiving module, triangular carrier generation module, modulating wave and carrier wave comparison module, dead band module and fault message output module group Into.Data reception module receive the parameter configuration from DSP, and duty cycle information is latched and be sent to modulating wave and Carrier wave comparison module, by dead band information latch and be sent to dead band module, by carrier wave frequency information with phase-shifting carrier wave information lock Deposit and be sent in carrier signal generation module；Fault message module sends IGBT fault input signals to DSP.Every piece of PWM Plate, which occurs, for signal can generate 36 road pwm signal outputs, and can receive 18 road IGBT fault input signals.

IGBT driving board mainly forms mutual by driving power, optocoupler signal isolation circuit, by P-channel+N channel MOS tubes Apotype common source SEPP single ended push-pull power amplification circuit forms, it is possible to achieve IGBT module driving, short-circuit protection, under-voltage protection work( Energy.Optocoupler signal isolation uses the ACPL-339J of AVAGO companies with driving chip, and drive signal first passes around light-coupled isolation, so Pass through a complementary type common source SEPP single ended push-pull power amplification circuit and power device being made up of P-channel+N-channel MOS pipe afterwards Gate pole be connected；Driving power is realized the 15V Power converts of input into exporting after+15V and -9V, for IGBT gate-drives Use；IGBT current collection level is connected by TVS diode with the DESAT pins of ACPL-339J chips, to realize IGBT's Short-circuit detecting；ACPL-339J chip integration short-circuit protection signals are transmitted with driving voltage UVP signal by pull-up resistor Pwm pulse plate is given, to realize error protection.

The beneficial effects of the utility model are：Control platform uses DSP and more FPGA architectures, pwm pulse generation and coding Device signal acquisition can pass through FPGA flexible configurations with calculating, it is not necessary to limited by DSP pin resources, do not extending plate feelings 6 groups of encoder collections can be completed under condition simultaneously to export with calculating and 36 road pwm signals, 6 groups of three phase electric machine controllers can be met Interface requirement.Control platform uses modularized design, can be according to different control objects, by increasing and decreasing control panel and reconstruct The mode of FPGA programs completes the configuration of control platform interface.

Brief description of the drawings

Fig. 1 is the modularization multi_motor control plateform system block diagram based on DSP and FPGA.

Fig. 2 is control platform plate layout drawing.

Fig. 3 is pwm pulse plate FPGA system structure chart.

Fig. 4 is encoder plate FPGA system structure chart.

Embodiment

Referring to shown in accompanying drawing.

Fig. 1 is the modularization multi_motor control plateform system block diagram based on DSP and FPGA, and Fig. 2 is control platform plate cloth Put figure.Control system platform uses modularized design, and core control panel is connected with auxiliary plate by bus mode.Core controls Plate is inserted on backplane bus unit, analog signalses conditioning and sampling plate, communication board, pwm pulse plate, encoder plate and power panel It is arranged parallel on a 4U type cabinet.The casing structure of this modularization, bus type, it ensure that the EMC of control platform Performance, versatility and flexibility are high.IGBT driving board is individually placed.

Analog quantity modulate circuit is connected with voltage hall sensor, current Hall sensor and temperature sensor, can be with Compatible voltage output type Hall sensor, current-output type Hall sensor and resistor-type temperature sensor simultaneously；Signal condition The output of circuit is connected with modulus conversion chip AD7606 input end of analog signal；Every piece of analog signalses conditioning and sampling Plate can complete the sampling of 16 road analog signalses, wherein the compatible voltage in 10 tunnels samples with current mode Hall sensor, 6 tunnels can be simultaneous Hold NTC and two kinds of temperature sensor samplings of PT100.Over-sampling modulate circuit first believes the current signal of Hall sensor, voltage Number voltage signal is converted to, the voltage that scope is ± 10V is then converted to after differential amplifier circuit and low pass filter and is believed Number and be connected with AD7606；1mA current sources caused by over-sampling modulate circuit connect with NTC thermistor, PT100 thermocouples, Temperature signal is converted into voltage signal and is connected with AD7606 chips.AD7606 chips believe analog-signal transitions into numeral Number, and sample magnitude is transferred to by DSP by data/address bus.

Pwm pulse plate FPGA system structure is as shown in Figure 3.Pwm signal generation program in FPGA uses Verilog programs Write, it is defeated by data reception module, triangular carrier generation module, modulating wave and carrier wave comparison module, dead band module, fault message Go out module composition.Data reception module receives the parameter configuration from DSP, and duty cycle information is latched and is sent to tune Ripple processed and carrier wave comparison module, by dead band information latch and be sent to dead band module, by carrier wave frequency information with and phase-shifting carrier wave Information is latched and is sent in carrier signal generation module；Fault message module sends IGBT fault input signals to DSP.Often Plate, which occurs, for block pwm signal can generate 36 road pwm signal outputs, and can receive 18 road IGBT fault input signals.

Encoder plate FPGA system structure is as shown in Figure 4.Encoder information calculation procedure in FPGA uses Verilog journeys Sequence is write, by 4 times of frequency modules of code device signal, DSP signal strobes counter module, encoder to count module, data output mould Block forms；4 times of frequency modules of code device signal obtain encoder output by handling the code device signal of isolation and amplifier 4 frequency-doubled signals and direction information of pulse；Encoder to count module is respectively to DSP signal strobes and 4 frequencys multiplication of encoder output Signal is counted, and then by calculating, rotary speed information, direction information and positional information can be obtained, through data outputting module Read after latch for DSP.Every piece of photoelectric encoder signal plate can complete the collection and calculating of 6 groups of code device signals.

Optocoupler signal isolation uses the ACPL-339J of AVAGO companies with driving chip, and drive signal is after light-coupled isolation Output, then passes through a complementary type common source SEPP single ended push-pull power amplification circuit and work(being made up of P-channel+N-channel MOS pipe The gate pole of rate device is connected, and push-pull power amplifier circuit uses IR companies IRF7343 cake cores, and gate-drive peak point current is most Greatly 38A；Driving power module uses Jin Shengyang companies QA01 power modules, can be achieved 15V input powers being converted into+15V Export with after -9V, used for IGBT gate-drives.IGBT colelctor electrode passes through high voltage ultrafast rectifier diode STH112U It is connected with the DESAT pins of ACPL-339J chips, to realize IGBT short-circuit detectings；ACPL-339J chip integration short-circuit protections Signal is transferred to pwm pulse plate with driving voltage UVP signal by pull-up resistor, to realize error protection.

Above-described embodiment do not limit the utility model in any form, all to be obtained using equivalent substitution or equivalent transformation Technical scheme, all fall within the scope of protection of the utility model.

Claims (5)

1. the more motor real-time control platforms of modularization based on DSP and FPGA, core control panel, the mould being made up of DSP and CPLD Analog quantity signal condition and sampling plate, communication board, the multiplex coding device process plate based on FPGA, pwm pulse plate, the electricity based on FPGA Source plate, bus board and bipolar transistor driving circuit of insulated gate plate form, it is characterised in that the core control of DSP, CPLD composition Making sheet is connected by bus board and analog signalses conditioning with sampling plate, coder processes plate, pwm pulse plate；Pwm pulse plate Pwm signal, which exports, gives bipolar transistor driving circuit of insulated gate plate；Power panel by 220V alternating current input power supplyings be converted into 5V, ± 15V, 24V isolated form out-put supply are powered to other control panels.

2. the more motor real-time control platforms of the modularization according to claim 1 based on DSP and FPGA, it is characterized in that, DSP Multi_motor control algorithm is completed, reads rotating speed, steering, positional information caused by encoder plate, sets pwm pulse plate pwm signal Switching frequency, dutycycle, phase and dead time；CPLD generation analog signalses conditionings and sampling plate, encoder plate, PWM The chip selection signal of pulse plate, and handle the fault-signal of bipolar transistor driving circuit of insulated gate plate input.

3. the more motor real-time control platforms of the modularization according to claim 1 based on DSP and FPGA, it is characterized in that, institute State analog signalses conditioning and include analog quantity modulate circuit and AD sampling A/D chips with sampling plate, the analog quantity modulate circuit and Voltage hall sensor, current Hall sensor are connected with temperature sensor, while compatible voltage output type Hall sensor, Current-output type Hall sensor and resistor-type temperature sensor.

4. the more motor real-time control platforms of the modularization according to claim 1 based on DSP and FPGA, it is characterized in that, institute The PWM signal frequency that the pwm pulse plate based on FPGA transmits according to DSP is stated, dutycycle, dead time, phase automatically generate band The pwm signal in dead band, and compatible fiber and electric signal output；Pwm pulse plate receives bipolar transistor driving circuit of insulated gate The fault-signal of plate output, and locking pulse, finally by data/address bus by transmitting fault information to core control panel.

5. the more motor real-time control platforms of the modularization according to claim 1 based on DSP and FPGA, it is characterized in that, often Multiplex coding device process plate of the block based on FPGA completes the collection and calculating of No. 6 photoelectric encoder information, the FPGA on plate simultaneously The speed, position and the turn signal that calculate Hou Mei roads encoder are transferred to core control panel.