CN207053471U - A kind of superelevation PSRR power amplification device - Google Patents
A kind of superelevation PSRR power amplification device Download PDFInfo
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- CN207053471U CN207053471U CN201720958428.6U CN201720958428U CN207053471U CN 207053471 U CN207053471 U CN 207053471U CN 201720958428 U CN201720958428 U CN 201720958428U CN 207053471 U CN207053471 U CN 207053471U
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Abstract
The utility model provides a kind of superelevation PSRR power amplification device, including amplifier, reference voltage circuit and low pass circuit, and the reference voltage circuit connects the low pass circuit, and the low pass circuit connects the input of the amplifier；Wherein, the reference voltage circuit includes first resistor and second resistance, the first end connection power supply of the first resistor, the first end of the second end connection second resistance of the first resistor, the first end of the second resistance connects the low pass circuit, the second end ground connection of the second resistance；The low pass circuit includes first switch, second switch and electric capacity, the first end of the first switch connects the first end of the second resistance, second end of first switch connects the first end of the electric capacity and the first end of second switch, second end of the second switch connects the amplifier, the sequential that the second end ground connection of the electric capacity, the first switch and second switch periodically open and close and first switch and second switch open and close is opposite.Superelevation PSRR power amplification device provided by the utility model can reach high PSRR without external capacitor, and simple in construction, cost is low.
Description
Technical Field
The utility model relates to an electronic circuit technical field, in particular to super high power supply rejection ratio power amplifier device.
Background
In the circuit of the power amplifier, after audio input is amplified by amplifiers of all stages, the amplification result is compared with triangular waves, and square waves generated by a comparator are input into a driving circuit to start a loudspeaker. The audio signal is subject to total harmonic distortion during this transmission and is also subject to power ripple. The current approaches to suppress noise and reduce total harmonic distortion are mainly to design precise circuits and add large filter capacitors, thereby improving the Power Supply Rejection Ratio (PSRR) of the chip and reducing the total harmonic distortion.
In the prior art, a fully differential architecture is generally adopted to achieve a relatively high Power Supply Rejection Ratio (PSRR), and in the fully differential architecture, the PSRR is mainly derived from a voltage regulator circuit for generating a differential amplifier VDD/2. Referring to fig. 1, in the prior art, a filter capacitor C is usually externally connected to achieve the effect of high PSRR. However, the externally-hung filter capacitor needs a large-area chip and large working current, so that the cost is high and the design is difficult; moreover, even in such a circuit, due to process mismatch during signal transmission, ripple voltage of a power supply, substrate bias effect and other parasitic effects of the circuit, certain noise and total harmonic distortion are generated, the noise and total harmonic distortion are amplified through an operational amplifier, a comparator and a driving circuit, and relatively large noise and total harmonic distortion still exist on the loudspeaker.
The published chinese patent CN102694514A provides a power amplifier device, which further provides the PSRR of the whole power amplifier device by generating a common-mode voltage, and the common-mode voltage generating unit includes a third resistor and a fourth resistor. However, the common mode voltage generating unit also needs an external filter capacitor to suppress noise and reduce total harmonic distortion, and the external capacitor is a great problem for design cost, chip layout area and the like, and is inconvenient to use in practice.
SUMMERY OF THE UTILITY MODEL
To above problem, the utility model discloses an aim at has designed a super high power supply rejection ratio power amplifier device, need not external electric capacity and can reach high power supply rejection ratio, simple structure, and is with low costs.
The utility model discloses specific technical scheme as follows:
an ultrahigh power supply rejection ratio power amplifier device comprises an amplifier, a reference voltage circuit and a low-pass circuit, wherein the reference voltage circuit is connected with the low-pass circuit, and the low-pass circuit is connected with the input end of the amplifier; wherein,
the reference voltage circuit comprises a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is connected with a power supply, a second end of the first resistor R1 is connected with a first end of a second resistor R2, a first end of the second resistor R2 is connected with the low-pass circuit, and a second end of the second resistor R2 is grounded;
the low-pass circuit comprises a first switch S1, a second switch S2 and a capacitor Cs, wherein a first end of the first switch S1 is connected with a first end of the second resistor R2, a second end of the first switch S1 is connected with a first end of the capacitor Cs and a first end of a second switch S2, a second end of the second switch S2 is connected with the amplifier, a second end of the capacitor Cs is grounded, the first switch S1 and the second switch S2 are periodically turned on and off, and the turn-on and turn-off timings of the first switch S1 and the second switch S2 are opposite.
Specifically, the low-pass circuit of the present invention is an N-level architecture, where N is greater than or equal to 1; wherein:
when N is 1, the low-pass circuit comprises a first switch S1, a second switch S2 and a capacitor Cs, a first end of the first switch S1 is connected to a first end of the second resistor R2, a second end of the first switch S1 is connected to a first end of the capacitor Cs and a first end of a second switch S2, and a second end of the second switch S2 is connected to the amplifier;
when N is 2, the low-pass circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor Cs1, and a second capacitor Cs2, and a second terminal of the second switch S2 is connected to a first terminal of a second capacitor Cs2 and a first terminal of the third switch;
when the low-pass circuit is an N-level architecture low-pass circuit, the low-pass circuit comprises N +1 switches and N capacitors, and the second end of the Nth switch is connected with the first end of the Nth capacitor and the first end of the (N + 1) th switch.
Specifically, when the present invention is a two-stage low-pass circuit, N is 2, the first switch S1, the second switch S2, and the third switch S3 are periodically turned on and off, and the timing of turning on and off the first switch S1 and the second switch S2 are opposite, and the timing of turning on and off the second switch S2 and the third switch S3 are opposite;
when the low-pass circuit is of an N-stage structure, the N +1 switches are periodically turned on and off, and the turn-on and turn-off timings of every adjacent switch are opposite.
Specifically, the formula for calculating the equivalent resistance of the low-pass circuit is:
wherein, CsIs the capacitance value of the capacitor Cs, fCKThe frequency of the first switch S1 and the second switch S2 being turned on and off.
The utility model provides a super high power supply rejection ratio power amplifier device compares with prior art, need not external electric capacity and can reach high power supply rejection ratio, produces a set of false resistance through low pass circuit, can reduce the electric capacity of uF grade into pF grade in the equivalence, and then can do into the chip with traditional external electric capacity inside, can save the effect that can reach high power supply rejection ratio again when chip space in using.
Drawings
Embodiments of the invention are further described below with reference to the accompanying drawings, in which:
FIG. 1 is a structural diagram of a prior art power amplifier circuit
Fig. 2 is a schematic diagram of the power amplifier device with ultra-high power supply rejection ratio of the present invention;
fig. 3 is a circuit structure diagram of the power amplifier device with ultra-high power supply rejection ratio of the present invention;
FIG. 4 is a basic resistance calculation chart;
fig. 5 is a diagram for calculating the basic resistance of the low-pass circuit of the power amplifier with ultra-high power supply rejection ratio of the present invention;
fig. 6 is a circuit diagram of the low-pass circuit of the power amplifier with ultrahigh power supply rejection ratio of the present invention;
fig. 7 is a circuit diagram of the second stage of the low-pass circuit of the power amplifier device with ultra-high power supply rejection ratio of the present invention;
fig. 8 is a timing diagram of the switching of the low-pass circuit of the power amplifier with ultra-high power supply rejection ratio of the present invention;
fig. 9 is a timing diagram of the switching of the low-pass circuit of the power amplifier with ultra-high power supply rejection ratio of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the following drawings and specific embodiments.
In application, the power amplifier circuit generally adopts a full differential mode, please refer to fig. 1, and in order to control the two-terminal dc output to the reference voltage of VDD/2, the full differential architecture usually generates the voltage of VDD/2 as the reference voltage of the power amplifier circuit through VDD and two resistors with the same resistance. Because the fully differential circuit itself has a good effect of suppressing the power noise, the power noise of the conventional fully differential architecture is mainly generated by the VDD/2 resistor divider circuit. In order to achieve the purpose of high power supply rejection ratio in a general traditional power amplifier circuit, a uF-magnitude capacitor C is externally hung to filter noise on VDD so as to achieve the effect of high power supply rejection ratio, the cost of the externally-connected capacitor is high, and the chip design is difficult.
Please refer to fig. 2, which is a schematic diagram of the power amplifier device with ultra-high power supply rejection ratio according to the present invention, a low-pass circuit is designed to generate a set of dummy resistors, so as to equivalently reduce the capacitance of uF magnitude to pF magnitude, and further design the external capacitor into the chip. In application, an external capacitor can be saved, and the effect of high power supply rejection ratio can be achieved.
The utility model provides a super high power supply rejection ratio power amplifier device please refer to fig. 3, including amplifier, reference voltage circuit and low pass circuit, reference voltage circuit connects low pass circuit, low pass circuit connects the input of amplifier. A group of low-pass circuits is added at the place where the resistance divides VDD/2, in order to filter the noise on VDD to achieve the purpose of high power supply rejection ratio. Referring to fig. 3, a pole is generated by a set of resistors R and a set of capacitors C, and the frequency of the pole is 1/RC, i.e. when the noise on VDD is higher than the frequency of the pole, the noise is filtered out and a clean VCM voltage is generated to provide to the power amplifier circuit.
Specifically, the reference voltage circuit comprises a first resistor R1 and a second resistor R2, a first end of the first resistor R1 is connected to the power supply, a second end of the first resistor R1 is connected to a first end of a second resistor R2, a first end of the second resistor R2 is connected to the low-pass circuit, and a second end of the second resistor R2 is grounded;
the low-pass circuit comprises a first switch S1, a second switch S2 and a capacitor Cs, wherein a first end of the first switch S1 is connected with a first end of the second resistor R2, a second end of the first switch S1 is connected with a first end of the capacitor Cs and a first end of a second switch S2, a second end of the second switch S2 is connected with the amplifier, a second end of the capacitor Cs is grounded, the first switch S1 and the second switch S2 are periodically turned on and off, and the turn-on and turn-off timings of the first switch S1 and the second switch S2 are opposite.
FIG. 4 is a diagram of a basic resistance calculation formula, wherein the resistance R is equal to the two-terminal voltage VA-VB divided by the flowing current I. Referring to FIG. 5, which is a diagram of the basic resistance calculation formula of the low pass circuit, the capacitor Cs is connected to VA and VB through the switches S1 and S2, and the frequency of the S1 and S2 switches is fCKThat is, when S1 is turned on, VA is connected to Cs, and S2 is turned off, Cs is disconnected from VB. Similarly, when S1 is turned off, S2 connects Cs and VB together. From this it can be deduced that the equivalent current flowing from VA to VB is CsfCK(VA-VB), and the pseudo resistance can be obtainedEffective resistance value ofWherein, CsIs the capacitance value of the capacitor Cs, fCKThe frequency of the first switch S1 and the second switch S2 being turned on and off.
Specifically, the low pass circuit is N level framework, and N is more than or equal to 1. Wherein:
when N is equal to 1, the low-pass circuit includes a first switch S1, a second switch S2, and a capacitor Cs, a first terminal of the first switch S1 is connected to a first terminal of the second resistor R2, a second terminal of the first switch S1 is connected to a first terminal of the capacitor Cs and a first terminal of the second switch S2, and a second terminal of the second switch S2 is connected to the amplifier.
Please refer to fig. 6, which is a circuit diagram of a first stage of the low pass circuit, and fig. 7, which is a circuit diagram of a second stage of the low pass circuit. Generally, if a higher equivalent resistance is to be achieved, a lower frequency and a smaller Cs capacitance are required, but in practice, the lower frequency and the smaller capacitance cause the Cs charge to be easily disturbed and the parasitic resistance of Cs to ground itself causes a large reduction in the effect of the dummy resistance. To avoid the above problem, a multi-stage pseudo resistor structure can be used to solve the above problem, i.e. two Cs capacitors are used in the low pass circuit stage of fig. 7 to avoid using too low frequency and too small Cs capacitor, so as to meet the application requirement.
When N is 2, the low-pass circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor Cs1, and a second capacitor Cs2, and a second terminal of the second switch S2 is connected to a first terminal of a second capacitor Cs2 and a first terminal of the third switch;
when the low-pass circuit is an N-level architecture low-pass circuit, the low-pass circuit comprises N +1 switches and N capacitors, and the second end of the Nth switch is connected with the first end of the Nth capacitor and the first end of the (N + 1) th switch.
Specifically, when the present invention is a two-stage low-pass circuit, N is 2, the first switch S1, the second switch S2, and the third switch S3 are periodically turned on and off, and the timing of turning on and off the first switch S1 and the second switch S2 are opposite, and the timing of turning on and off the second switch S2 and the third switch S3 are opposite;
when the low-pass circuit is of an N-stage structure, the N +1 switches are periodically turned on and off, and the turn-on and turn-off timings of every adjacent switch are opposite.
Please refer to fig. 8, which is a timing diagram of the first stage of the low pass circuit, and fig. 9, which is a timing diagram of the second stage of the low pass circuit. In the first level architecture, the switching timings of S1 and S2 are reversed, i.e., S2 is turned off when S1 is turned on, and S2 is turned on when S1 is turned off, as shown in fig. 8. In the two-stage architecture, the timing of S1 and S2 is in anti-phase and S1 and S3 are in-phase, S2 is ON while S3 is OFF when S1 is ON, and S2 is ON while S3 is OFF when S1 is OFF.
The above description of the present invention does not limit the scope of the present invention. Any other corresponding changes and modifications made according to the technical idea of the present invention should be included in the scope of the claims of the present invention.
Claims (4)
1. The power amplifier device with the ultrahigh power supply rejection ratio is characterized by comprising an amplifier, a reference voltage circuit and a low-pass circuit, wherein the reference voltage circuit is connected with the low-pass circuit, and the low-pass circuit is connected with the input end of the amplifier; wherein,
the reference voltage circuit comprises a first resistor R1 and a second resistor R2, wherein a first end of the first resistor R1 is connected with a power supply, a second end of the first resistor R1 is connected with a first end of a second resistor R2, a first end of the second resistor R2 is connected with the low-pass circuit, and a second end of the second resistor R2 is grounded;
the low-pass circuit comprises a first switch S1, a second switch S2 and a capacitor Cs, wherein a first end of the first switch S1 is connected with a first end of the second resistor R2, a second end of the first switch S1 is connected with a first end of the capacitor Cs and a first end of a second switch S2, a second end of the second switch S2 is connected with the amplifier, a second end of the capacitor Cs is grounded, the first switch S1 and the second switch S2 are periodically turned on and off, and the turn-on and turn-off timings of the first switch S1 and the second switch S2 are opposite.
2. The ultrahigh-power-supply-rejection-ratio power amplifier device according to claim 1, wherein the low-pass circuit is of an N-level architecture, N is greater than or equal to 1; wherein:
when N is 1, the low-pass circuit comprises a first switch S1, a second switch S2 and a capacitor Cs, a first end of the first switch S1 is connected to a first end of the second resistor R2, a second end of the first switch S1 is connected to a first end of the capacitor Cs and a first end of a second switch S2, and a second end of the second switch S2 is connected to the amplifier;
when N is 2, the low-pass circuit includes a first switch S1, a second switch S2, a third switch S3, a first capacitor Cs1, and a second capacitor Cs2, and a second terminal of the second switch S2 is connected to a first terminal of a second capacitor Cs2 and a first terminal of the third switch;
when the low-pass circuit is an N-level architecture low-pass circuit, the low-pass circuit comprises N +1 switches and N capacitors, and the second end of the Nth switch is connected with the first end of the Nth capacitor and the first end of the (N + 1) th switch.
3. The ultrahigh power supply rejection ratio power amplifier device as claimed in claim 2, wherein when the low pass circuit is a two-stage structure, N is 2, the first switch S1, the second switch S2 and the third switch S3 are periodically turned on and off, and the timing of turning on and off the first switch S1 and the second switch S2 is opposite, and the timing of turning on and off the second switch S2 and the third switch S3 is opposite;
when the low-pass circuit is of an N-stage structure, the N +1 switches are periodically turned on and off, and the turn-on and turn-off timings of every adjacent switch are opposite.
4. The ultrahigh power supply rejection ratio power amplifier device according to claim 1, wherein the calculation formula of the equivalent resistance of the low-pass circuit is:
wherein, CsIs the capacitance value of the capacitor Cs, fCKThe frequency of the first switch S1 and the second switch S2 being turned on and off.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720958428.6U CN207053471U (en) | 2017-08-01 | 2017-08-01 | A kind of superelevation PSRR power amplification device |
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| CN201720958428.6U CN207053471U (en) | 2017-08-01 | 2017-08-01 | A kind of superelevation PSRR power amplification device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107332525A (en) * | 2017-08-01 | 2017-11-07 | 深圳市中移联半导体科技有限公司 | A kind of superelevation PSRR power amplification device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107332525A (en) * | 2017-08-01 | 2017-11-07 | 深圳市中移联半导体科技有限公司 | A kind of superelevation PSRR power amplification device |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20190509 Address after: 518000 Guangdong Province, Futian District, Shenzhen, 1063 Xiangmei Road, Shuixie Flower Du Mingcuiju 2 20B Patentee after: Lin Qiliang Address before: 518000 No. 22 Huanping Road, Gaoqiao Community, Pingdi Street, Longgang District, Shenzhen City, Guangdong Province Patentee before: Shenzhen Sino link Semiconductor Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20180227 Termination date: 20200801 |