CN203859728U - Improved Miller compensation amplifier - Google Patents
Improved Miller compensation amplifier Download PDFInfo
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- CN203859728U CN203859728U CN201420297987.3U CN201420297987U CN203859728U CN 203859728 U CN203859728 U CN 203859728U CN 201420297987 U CN201420297987 U CN 201420297987U CN 203859728 U CN203859728 U CN 203859728U
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- miller
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- compensated amplifier
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Abstract
The utility model provides an improved Miller compensation amplifier, which comprises a transconductance amplifier, a compensation capacitor, a compensation resistor, an NMOS transistor and a bias current source, wherein the negative phase input end of the transconductance amplifier is connected with an input signal; the positive phase input end of the transconductance amplifier is connected with the output end of the Miller compensation amplifier; the output end of the transconductance amplifier is connected with the grid electrode of the NMOS transistor through the compensation resistor; the bias current source is connected between a power source end and the drain electrode of the NMOS transistor; current is injected to the drain electrode of the NMOS transistor; two ends of the compensation capacitor are respectively connected with the grid electrode and the drain electrode of the NMOS transistor; the source electrode of the NMOS transistor is connected with a ground terminal; the connection node between the current source and the NMOS transistor is connected with the output end of the Miller compensation amplifier. Compared with the prior art, the compensation resistor of the improved Miller compensation amplifier is in series connection between a first amplifier stage and a second amplifier stage, consequently, a smaller capacitance value for the compensation capacitor is required when the position of a dominant pole remains unchanged, so that the area of the compensation capacitor is reduced.
Description
[technical field]
The utility model relates to circuit design field, particularly a kind of modified model miller-compensated (Miller Compensation) amplifier.
[background technology]
In integrated circuit, often adopt signal amplification appliance (or signal amplification circuit), in order to guarantee stable output signal, need carry out loop stability compensation, general normal employing miller-compensated amplifier, one of its advantage is greatly to reduce the area of building-out capacitor.
Please refer to shown in Fig. 1, it is a kind of miller-compensated two-stage signal amplifier of the prior art, wherein, trsanscondutance amplifier GM forms first order amplifying stage, NMOS (N-Mental-Oxide-Semiconductor) transistor MN and bias current sources Ib form second level amplifying stage, the first resistance R 1 and the second resistance R 2 represent respectively the dead resistance of first order amplifying stage and second level amplifying stage, the first capacitor C 1 and the second capacitor C 2 represent respectively the parasitic capacitance of first order amplifying stage and second level amplifying stage, and Cx is building-out capacitor.The dominant pole P1=1/ (R1*A2*Cx) that this two-stage signal amplifier produces, inferior limit P2=gm2/C2, RHP Z1=gm2/Cx at zero point, second level gain A 2=gm2*R2, wherein, R1 is the resistance of the first resistance R 1, R2 is the resistance of the second resistance R 2, and gm1 is the mutual conductance of first order amplifying stage (being trsanscondutance amplifier GM), the mutual conductance of gm2 second level amplifying stage, C2 is the capacitance of the second capacitor C 2, the capacitance that Cx is building-out capacitor.Owing to being subject to the restriction of every grade of maximum gain of circuit and matching, building-out capacitor Cx in general circuit needs 10pF～20pF above (1pF=1000fF), nonetheless, building-out capacitor Cx still can occupy very large area, and building-out capacitor Cx increasing is twice, half before the dominant pole of compensation is but only reduced to.
Therefore, be necessary to provide a kind of improved technical scheme to overcome the problems referred to above.
[utility model content]
The purpose of this utility model is to provide a kind of modified model miller-compensated amplifier, and it can reduce the area of building-out capacitor.
In order to address the above problem, the utility model provides a kind of modified model miller-compensated amplifier, and it comprises trsanscondutance amplifier, building-out capacitor, compensating resistance, nmos pass transistor and bias current sources.The negative-phase input of described trsanscondutance amplifier is connected with input signal, and its normal phase input end is connected with the output of miller-compensated amplifier, and its output is connected with the grid of described nmos pass transistor through compensating resistance; Bias current sources is connected between power end and the drain electrode of described nmos pass transistor, and it is to the drain electrode Injection Current of described nmos pass transistor; One end of building-out capacitor is connected with the grid of described nmos pass transistor, and its other end is connected with the drain electrode of described nmos pass transistor, and the source electrode of described nmos pass transistor is connected with earth terminal; Described current source is connected with the output of miller-compensated amplifier with the connected node between nmos pass transistor.
Further, described modified model miller-compensated amplifier also comprises and moves resistance zero point, moves this zero point between one end that resistance is connected in nmos pass transistor grid and described building-out capacitor not and described nmos transistor drain is connected.
Further, described modified model miller-compensated amplifier also comprises the feedback circuit being connected between the output of miller-compensated amplifier and the negative-phase input of trsanscondutance amplifier, and described feedback circuit provides the feedback voltage of the output end voltage of reflection miller-compensated amplifier to described negative-phase input.
Further, described feedback circuit comprises the first divider resistance and the second divider resistance between the output and ground that is series at successively described miller-compensated amplifier, and the connected node voltage between the first divider resistance and the second divider resistance is described feedback voltage.
Further, the output of described trsanscondutance amplifier is formed with dead resistance and parasitic capacitance, and the output of miller-compensated amplifier is formed with dead resistance and parasitic capacitance or load capacitance.
The utility model provides another kind of modified model miller-compensated amplifier, and it comprises trsanscondutance amplifier, building-out capacitor, compensating resistance, PMOS transistor and bias current sources.The negative-phase input of described trsanscondutance amplifier is connected with input signal, and its normal phase input end is connected with the output of miller-compensated amplifier, and its output is connected with the transistorized grid of described PMOS through compensating resistance; Bias current sources is connected between earth terminal and the transistorized drain electrode of described PMOS, and electric current is extracted in its drain electrode from described PMOS transistor MP; One end of building-out capacitor is connected with the transistorized grid of described PMOS, and its other end is connected with the transistorized drain electrode of described PMOS, and the transistorized source electrode of described PMOS is connected with power end; Described current source is connected with the output of miller-compensated amplifier with the connected node between PMOS transistor.
Further, described modified model miller-compensated amplifier also comprises and moves resistance zero point, moves this zero point between one end that resistance is connected in PMOS transistor gate and described building-out capacitor not and described PMOS transistor drain is connected.
Further, described modified model miller-compensated amplifier also comprises the feedback circuit being connected between the output of miller-compensated amplifier and the negative-phase input of trsanscondutance amplifier, and described feedback circuit provides the feedback voltage of the output end voltage of reflection miller-compensated amplifier to described negative-phase input.
Further, described feedback circuit comprises the first divider resistance and the second divider resistance between the output and ground that is series at successively described miller-compensated amplifier, and the connected node voltage between the first divider resistance and the second divider resistance is described feedback voltage.
Further, the output of described trsanscondutance amplifier is formed with dead resistance and parasitic capacitance, and the output of miller-compensated amplifier is formed with dead resistance and parasitic capacitance or load capacitance.
Compared with prior art, the utility model is connected in series compensating resistance between first order amplifying stage and second level amplifying stage, like this, in the situation that realizing identical dominant pole position, the capacitance of the building-out capacitor needing is less, thereby can reduce the area of building-out capacitor, and then saves chip cost.
[accompanying drawing explanation]
In order to be illustrated more clearly in the technical scheme of the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly described, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.Wherein:
Fig. 1 is the circuit diagram of a kind of miller-compensated two-stage signal amplifier of the prior art;
Fig. 2 is the circuit diagram of the modified model miller-compensated amplifier of the utility model in first embodiment;
Fig. 3 is the circuit diagram that the modified model of the utility model in second embodiment moves miller-compensated amplifier zero point;
Fig. 4 is the circuit diagram of the modified model miller-compensated amplifier of the utility model in the 3rd embodiment;
Fig. 5 is the circuit diagram of the modified model null offset miller-compensated amplifier of the utility model in the 4th embodiment.
[embodiment]
For above-mentioned purpose of the present utility model, feature and advantage can be become apparent more, below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Alleged " embodiment " or " embodiment " refers to special characteristic, structure or the characteristic that can be contained at least one implementation of the utility model herein.Different local in this manual " in one embodiment " that occur not all refer to same embodiment, neither be independent or the embodiment mutually exclusive with other embodiment optionally.Unless stated otherwise, the word that connection herein, the expression that is connected, joins are electrically connected all represents to be directly or indirectly electrical connected.
Due in integrated circuit fabrication process, the capacitance size that 20uM*20uM area can be manufactured is approximately: the 300fF of PIP (Poly-Insulation-Poly) type; The 800fF of MOS type; The 800fF of MIM (Metal-Insulation-Metal) type, and more than the high resistance measurement of the area manufacture of 20uM*20uM can reach 500K ohm equally, therefore, the utility model is connected in series compensating resistance between first order amplifying stage and second level amplifying stage, like this, in the situation that realizing identical dominant pole position, the capacitance of the building-out capacitor needing is less, thereby can reduce the area of building-out capacitor, and then save chip cost.
Please refer to shown in Fig. 2, it is the circuit diagram of the modified model miller-compensated amplifier of the utility model in first embodiment.This modified model miller-compensated amplifier is miller-compensated two-stage signal amplifier, and it comprises trsanscondutance amplifier GM, building-out capacitor Cxx, compensating resistance Ra, nmos pass transistor MN and bias current sources Ib.The negative-phase input of described trsanscondutance amplifier GM is connected with input signal VI, and its normal phase input end is connected with the output VO of miller-compensated amplifier, and its output is connected with the grid of described nmos pass transistor MN through compensating resistance Ra; Bias current sources Ib is connected between power end VCC and the drain electrode of described nmos pass transistor MN, and it is to the drain electrode Injection Current of described nmos pass transistor MN; One end of building-out capacitor Cxx is connected with the grid of described nmos pass transistor MN, and its other end is connected with the drain electrode of described nmos pass transistor MN, and the source electrode of described nmos pass transistor MN is connected with earth terminal GND; Described current source Ib is connected with the output VO of miller-compensated amplifier with the connected node between nmos pass transistor MN.Wherein, trsanscondutance amplifier GM forms first order amplifying stage, nmos pass transistor MN and bias current sources Ib form second level amplifying stage (being that second level amplifying stage is the common source amplifying stage of nmos type), the first resistance R 1 and the second resistance R 2 represent respectively the dead resistance of first order amplifying stage and second level amplifying stage, the first capacitor C 1 represents the parasitic capacitance of first order amplifying stage, and the second capacitor C 2 represents parasitic capacitance or the load capacitance of second level amplifying stage.
The open-loop transfer function of the modified model miller-compensated amplifier shown in Fig. 2 is: H (s)=-A (1-s*Cxx/gm2)/((1+s*R1*A2* (1+Ra/R1) * Cxx) * (1+s*C2/gm2)),
Wherein, A=gm1*R1*gm2*R2, second level gain A 2=gm2*R2, dominant pole P1_1=1/ (R1*A2* (1+Ra/R1) * Cxx), inferior limit P2_2=gm2/C2 (same as the prior art), RHP Z1=gm2/Cxx at zero point, R1 is the resistance of the first dead resistance R1, R2 is the resistance of the second dead resistance R2, gm1 is the mutual conductance of trsanscondutance amplifier GM, the mutual conductance of gm2 second level amplifying stage, C2 is the capacitance of the second parasitism or load capacitance C2, Cxx is the capacitance of building-out capacitor Cxx.
If the dominant pole position P1 of dominant pole of the present utility model position P1_1 and Miller amplifier in Fig. 1 is identical, the building-out capacitor Cxx=needing (1/ (1+Ra/R1)) * Cx, by introducing the area that compensating resistance Ra can reduce building-out capacitor between first order amplifying stage and second level amplifying stage; Meanwhile, inferior pole and zero moves toward high frequency, is more conducive to loop stability.In addition, compared with prior art, the building-out capacitor increasing in the utility model is twice, and it is more that the dominant pole of compensation reduces.
In a concrete example, suppose gm1=gm2=40uS, R1=R2=2.5Mohm, building-out capacitor Cx of the prior art shown in Fig. 1 is 10pF (12.5 of the mos capacitance that area is 20uM*20uM), if compensating resistance Ra=500Kohm is (footprint area 20uM*20uM, a capacity area), 10 of the mos capacitances that the capacity area of the building-out capacitor Cxx that the utility model needs is 20uM*20uM, an additional compensating resistance Ra, the gross area of building-out capacitor Cxx and building-out capacitor Ra is 11 20uM*20uM, few 1 the mos capacitance area of building-out capacitor Cx more of the prior art, if the building-out capacitor Cx of prior art is 20pF (25 of the mos capacitance that area is 20uM*20uM), compensating resistance Ra=500Kohm, adopting the building-out capacitor Cxx of the utility model needs and the gross area of compensating resistance Ra is 22 20uM*20uM, if compensating resistance Ra=1Mohm, the area altogether needing is 20 20uM*20uM, visible, the capacitance of the building-out capacitor needing is larger, adopt the utility model more useful, compared with prior art, the area that building-out capacitor reduces is larger.
Please refer to shown in Fig. 3, it moves the circuit diagram of miller-compensated amplifier zero point for the modified model in second embodiment of the utility model.The difference of itself and Fig. 2 is, it also comprises and moves resistance R x zero point, move grid that resistance R x is connected in nmos pass transistor MN and described building-out capacitor Cxx this zero point not and described nmos pass transistor MN drain between the one end being connected, by moving resistance R x zero point, RHP can be moved to high frequency or Left half-plane zero point, be Z2=1/ (Rx-1/gm2) * Cxx the zero point that is the miller-compensated amplifier in Fig. 3, when Rx-gm2>0, be positioned at Left half-plane this zero point, wherein Rx is the resistance value that moves resistance R X zero point.Identical with Fig. 2 of the dominant pole of the modified model null offset miller-compensated amplifier shown in Fig. 3 and time limit.
Please refer to shown in Fig. 4, it is the circuit diagram of the modified model miller-compensated amplifier in the 3rd embodiment in the utility model.Modified model miller-compensated amplifier in Fig. 4 comprises trsanscondutance amplifier GM, building-out capacitor Cxx, compensating resistance Ra, PMOS (P-Mental-Oxide-Semiconductor) transistor MP and bias current sources Ib.The negative-phase input of described trsanscondutance amplifier GM is connected with input signal VI, and its normal phase input end is connected with the output VO of miller-compensated amplifier, and its output is connected with the grid of described PMOS transistor MP through compensating resistance Ra; Bias current sources Ib is connected between earth terminal GND and the drain electrode of described PMOS transistor MP, and electric current is extracted in its drain electrode from described PMOS transistor MP; One end of building-out capacitor Cxx is connected with the grid of described PMOS transistor MP, and its other end is connected with the drain electrode of described PMOS transistor MP, and the source electrode of described PMOS transistor MP is connected with power end VCC; Described current source Ib is connected with the output VO of miller-compensated amplifier with the connected node between PMOS transistor MP.Wherein, trsanscondutance amplifier GM forms first order amplifying stage, PMOS transistor MP and bias current sources Ib form second level amplifying stage (being that second level amplifying stage is the common source amplifying stage of pmos type), the first resistance R 1 and the second resistance R 2 represent respectively the dead resistance of first order amplifying stage and second level amplifying stage, the first capacitor C 1 represents the parasitic capacitance of first order amplifying stage, and the second capacitor C 2 represents parasitic capacitance or the load capacitance of second level amplifying stage.The difference of Fig. 4 and Fig. 2 is only, the common source amplifying stage that the second level amplifying stage in Fig. 4 is pmos type, the common source amplifying stage that the second level amplifying stage in Fig. 2 is nmos type.The formula at modified model miller-compensated amplifier and the dominant pole of modified model miller-compensated amplifier in Fig. 2 in Fig. 4, inferior limit and RHP zero point represents identical respectively, specifically please refer to the above-mentioned statement to Fig. 2, does not repeat them here.
Please refer to shown in Fig. 5, it is the circuit diagram of the modified model null offset miller-compensated amplifier of the utility model in the 4th embodiment.The difference of itself and Fig. 4 is, it also comprises and moves resistance R x zero point, move grid that resistance R x is connected in PMOS transistor MP and described building-out capacitor Cxx this zero point not and between one end of being connected of the drain electrode of described PMOS transistor MP, by moving resistance R x zero point, RHP can be moved to high frequency or Left half-plane zero point, be Z2=1/ (Rx-1/gm2) * Cxx the zero point that is the miller-compensated amplifier in Fig. 5, when Rx-gm2>0, be positioned at Left half-plane this zero point, wherein Rx is the resistance value that moves resistance R x zero point.Identical with Fig. 4 of the dominant pole of the modified model null offset miller-compensated amplifier shown in Fig. 5 and time limit.
At this, it should be noted that, in Fig. 2-Fig. 5, between output VO and the negative-phase input of trsanscondutance amplifier GM, also can set up feedback circuit, and not only limitation with figure in output VO directly feed back to first order amplifying stage.Described feedback circuit provides the feedback voltage of the described output V0 voltage of reflection, concrete, described feedback circuit comprises the first divider resistance and the second divider resistance being series at successively between described output VO and earth terminal GND, connected node between the first divider resistance and the second divider resistance is connected with the negative-phase input of described trsanscondutance amplifier GM, and the connected node voltage of the first divider resistance and the second divider resistance is described feedback voltage.
In sum, the utility model by being connected in series compensating resistance Ra between first order amplifying stage and second level amplifying stage, like this, in the situation that realizing identical dominant pole position, the capacitance of the building-out capacitor needing is less, thereby can reduce the area of building-out capacitor, saves chip cost, time pole and zero moves toward high frequency simultaneously, is more conducive to loop stability.
In the utility model, " connection ", be connected, word that the expression such as " company ", " connecing " is electrical connected, if no special instructions, represent direct or indirect electric connection.
It is pointed out that being familiar with any change that person skilled in art does embodiment of the present utility model does not all depart from the scope of claims of the present utility model.Correspondingly, the scope of claim of the present utility model is also not limited only to previous embodiment.
Claims (10)
1. a modified model miller-compensated amplifier, is characterized in that, it comprises trsanscondutance amplifier, building-out capacitor, compensating resistance, nmos pass transistor and bias current sources,
The negative-phase input of described trsanscondutance amplifier is connected with input signal, and its normal phase input end is connected with the output of miller-compensated amplifier, and its output is connected with the grid of described nmos pass transistor through compensating resistance; Bias current sources is connected between power end and the drain electrode of described nmos pass transistor, and it is to the drain electrode Injection Current of described nmos pass transistor; One end of building-out capacitor is connected with the grid of described nmos pass transistor, and its other end is connected with the drain electrode of described nmos pass transistor, and the source electrode of described nmos pass transistor is connected with earth terminal; Described current source is connected with the output of miller-compensated amplifier with the connected node between nmos pass transistor.
2. modified model miller-compensated amplifier according to claim 1, it is characterized in that, it also comprises and moves resistance zero point, moves this zero point between one end that resistance is connected in nmos pass transistor grid and described building-out capacitor not and described nmos transistor drain is connected.
3. according to the modified model miller-compensated amplifier described in claim 1 or 2, it is characterized in that, it also comprises the feedback circuit being connected between the output of miller-compensated amplifier and the negative-phase input of trsanscondutance amplifier, and described feedback circuit provides the feedback voltage of the output end voltage of reflection miller-compensated amplifier to described negative-phase input.
4. modified model miller-compensated amplifier according to claim 3, is characterized in that,
Described feedback circuit comprises the first divider resistance and the second divider resistance between the output and ground that is series at successively described miller-compensated amplifier, and the connected node voltage between the first divider resistance and the second divider resistance is described feedback voltage.
5. modified model miller-compensated amplifier according to claim 3, is characterized in that, the output of described trsanscondutance amplifier is formed with dead resistance and parasitic capacitance, and the output of miller-compensated amplifier is formed with dead resistance and parasitic capacitance or load capacitance.
6. a modified model miller-compensated amplifier, is characterized in that, it comprises trsanscondutance amplifier, building-out capacitor, compensating resistance, PMOS transistor and bias current sources,
The negative-phase input of described trsanscondutance amplifier is connected with input signal, and its normal phase input end is connected with the output of miller-compensated amplifier, and its output is connected with the transistorized grid of described PMOS through compensating resistance; Bias current sources is connected between earth terminal and the transistorized drain electrode of described PMOS, and electric current is extracted in its drain electrode from described PMOS transistor MP; One end of building-out capacitor is connected with the transistorized grid of described PMOS, and its other end is connected with the transistorized drain electrode of described PMOS, and the transistorized source electrode of described PMOS is connected with power end; Described current source is connected with the output of miller-compensated amplifier with the connected node between PMOS transistor.
7. modified model miller-compensated amplifier according to claim 6, it is characterized in that, it also comprises and moves resistance zero point, moves this zero point between one end that resistance is connected in PMOS transistor gate and described building-out capacitor not and described PMOS transistor drain is connected.
8. according to the modified model miller-compensated amplifier described in claim 6 or 7, it is characterized in that, it also comprises the feedback circuit being connected between the output of miller-compensated amplifier and the negative-phase input of trsanscondutance amplifier, and described feedback circuit provides the feedback voltage of the output end voltage of reflection miller-compensated amplifier to described negative-phase input.
9. modified model miller-compensated amplifier according to claim 8, is characterized in that,
Described feedback circuit comprises the first divider resistance and the second divider resistance between the output and ground that is series at successively described miller-compensated amplifier, and the connected node voltage between the first divider resistance and the second divider resistance is described feedback voltage.
10. modified model miller-compensated amplifier according to claim 6, is characterized in that, the output of described trsanscondutance amplifier is formed with dead resistance and parasitic capacitance, and the output of miller-compensated amplifier is formed with dead resistance and parasitic capacitance or load capacitance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420297987.3U CN203859728U (en) | 2014-06-05 | 2014-06-05 | Improved Miller compensation amplifier |
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| CN201420297987.3U CN203859728U (en) | 2014-06-05 | 2014-06-05 | Improved Miller compensation amplifier |
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| CN203859728U true CN203859728U (en) | 2014-10-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467374A (en) * | 2014-12-31 | 2015-03-25 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and switch-type convertor using same |
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2014
- 2014-06-05 CN CN201420297987.3U patent/CN203859728U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104467374A (en) * | 2014-12-31 | 2015-03-25 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and switch-type convertor using same |
| CN104467374B (en) * | 2014-12-31 | 2017-04-12 | 矽力杰半导体技术(杭州)有限公司 | Control circuit and switch-type convertor using same |
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Address after: 214028 10th Floor, Area A, 530 Building, Qingyuan Road, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee after: WUXI ZHONGGAN MICROELECTRONIC CO., LTD. Address before: 214028 10th Floor, Area A, 530 Building, Qingyuan Road, Taihu International Science Park, Wuxi New District, Jiangsu Province Patentee before: Wuxi Vimicro Co., Ltd. |
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