CN206931320U - A kind of array base palte and display device - Google Patents
A kind of array base palte and display device Download PDFInfo
- Publication number
- CN206931320U CN206931320U CN201720969437.5U CN201720969437U CN206931320U CN 206931320 U CN206931320 U CN 206931320U CN 201720969437 U CN201720969437 U CN 201720969437U CN 206931320 U CN206931320 U CN 206931320U
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- lead
- grid
- array base
- base palte
- boost line
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Abstract
The utility model discloses a kind of array base palte and display device.The array base palte includes a plurality of grid line and data wire in viewing area, a plurality of grid lead and source lead in non-display area, and the grid lead connects grid line and the IC pin respectively, and the source lead connects data wire and IC pins respectively；The first boost line is at least parallel with the both ends of a grid lead, and/or, the second boost line is at least parallel with the both ends of source lead.Even if grid lead and source lead in the array base palte by ESD punch through damage also can normal work, repaired without the later stage.
Description
Technical field
It the utility model is related to Display Technique, more particularly to a kind of array base palte and display device.
Background technology
A leakage problem is of common occurrence in industry is shown caused by the IC leads of damage by static electricity screen.It is in a notification number
A kind of array base palte and its restorative procedure and display device are disclosed in CN103293812B patent document, the array base palte leads to
The first repair line and/or the second repair line vacantly in grid lead and/or source lead stacking are crossed, if grid lead or source electrode
If lead is damaged, can both ends by laser fusion connect grid lead and the first repair line or connection source lead and
Second repair line is repaired.But the when and where that ESD occurs has uncertainty, it is difficult to take precautions against, once ESD is hit
Hinder IC leads, it is also necessary to which detection is which bar IC lead is breakdown, will also be again if the transportation after dispatching from the factory occurs for breakdown
Return repair in shop to answer, add workflow and its inconvenience.
Utility model content
In order to solve above-mentioned the deficiencies in the prior art, the utility model provides a kind of array base palte and display device.The battle array
Even if grid lead and source lead in row substrate by ESD punch through damage also can normal work, repaired without the later stage.
Technical problem to be solved in the utility model is achieved by the following technical programs：
A kind of array base palte, including a plurality of grid line and data wire in viewing area, in non-display area
A plurality of grid lead and source lead, the grid lead connect grid line and the IC pin, the source lead difference respectively
Connect data wire and IC pins；The first boost line is at least parallel with the both ends of a grid lead, and/or, at least a source electrode draws
The second boost line is parallel with the both ends of line.
Further, it is in levels stack structure between the grid lead and the first boost line, and/or, the source electrode draws
It is in levels stack structure between line and the second boost line.
Further, the same layer of first boost line and source lead, and/or, second boost line and the grid
The same layer of lead.
Further, it is provided with insulating barrier between the grid lead and the first boost line.
Further, it is in left and right parallel construction between the grid lead and the first boost line, and/or, the source electrode draws
It is in left and right parallel construction between line and the second boost line.
Further, binding has driving IC on the IC pins.
A kind of display device, including above-mentioned array base palte.
The utility model has the advantages that：The first boost line, source are parallel with the grid lead of the array base palte
The second boost line is parallel with the lead of pole, even if ESD, which occurs, punctures one or more grid lead therein or source lead, its
Corresponding first boost line or the second boost line are also still maintained under normally state, and the grid lead and first auxiliary
The simultaneously breakdown probability of index contour or the source lead and the second boost line is relatively low, thus reliability and stability compared with
Height, and can also usually reduce the conducting resistance of the grid lead and source lead.
Brief description of the drawings
Fig. 1 is the schematic diagram of array base palte provided by the utility model；
Fig. 2 is the lead of array base palte and the stacking schematic diagram of boost line shown in Fig. 1；
Fig. 3 is the schematic diagram of another array base palte provided by the utility model.
Embodiment
The utility model is described in detail with reference to the accompanying drawings and examples.
Embodiment one
As shown in figs. 1 and 3, a kind of array base palte, including a plurality of grid line 1 and data wire 2 in viewing area, are located at
A plurality of grid lead 11 and source lead 21 in non-display area, the grid lead 11 connect the grid line 1 and IC respectively
Pin 3, the source lead 21 connect data wire 2 and IC pins 3 respectively；Is at least parallel with the both ends of a grid lead 11
One boost line 12, and/or, the second boost line 22 is at least parallel with the both ends of source lead 21.
The first boost line 12 is parallel with the grid lead 11 of the array base palte, the second auxiliary is parallel with source lead 21
Line 22, even if ESD, which occurs, punctures one or more grid lead 11 therein or source lead 21, its corresponding first boost line
12 or second boost line 22 be also still maintained under normally state, and the boost line 12 of the grid lead 11 and first or
The simultaneously breakdown probability of the boost line 22 of source lead 21 and second is relatively low, therefore reliability and stability are higher, and
And it can also usually reduce the conducting resistance of the grid lead 11 and source lead 21.
As illustrated in fig. 1 and 2, it is in levels stack structure between the boost line 12 of grid lead 11 and first, and/or, institute
It is in levels stack structure to state between the boost line 22 of source lead 21 and second.This structure can reduce the face of non-display area
Product, be advantageous to the narrow frame of display device.
Preferably, the 21 same layer of the first boost line 12 and source lead, and/or, second boost line 22 and described
11 same layer of grid lead, thus first boost line 12 can be synchronously made when making the source lead 21, made
Second boost line 22 is synchronously made when making the grid lead 11, reduces the making step of the array base palte.The grid
Insulating barrier 4 is provided between the boost line 12 of lead 11 and first, this insulating barrier 4 can be when making the gate insulation layer in viewing area
It is synchronous to make.
As shown in figure 3, be in left and right parallel construction between the boost line 12 of grid lead 11 and first, and/or, the source
It is in left and right parallel construction between the boost line 22 of pole lead 21 and second.
Binding has driving IC on the IC pins 3.
Embodiment two
A kind of display device, including a kind of described array base palte of embodiment.
Embodiment described above only expresses embodiment of the present utility model, and its description is more specific and detailed, but simultaneously
Therefore the limitation to the utility model patent scope can not be interpreted as, as long as using equivalent substitution or the form of equivalent transformation institute
The technical scheme of acquisition, it all should fall within the scope of protection of the utility model.
Claims (7)
1. a kind of array base palte, including a plurality of grid line and data wire in viewing area, more in non-display area
Bar grid lead and source lead, the grid lead connect grid line and the IC pin respectively, and the source lead connects respectively
Connect data wire and IC pins；It is characterized in that：The first boost line is at least parallel with the both ends of a grid lead, and/or, at least
The second boost line is parallel with the both ends of source lead.
2. array base palte according to claim 1, it is characterised in that：Presented between the grid lead and the first boost line
Lower stepped construction, and/or, it is in levels stack structure between the source lead and the second boost line.
3. array base palte according to claim 2, it is characterised in that：The same layer of first boost line and source lead, and/
Or, second boost line and the same layer of the grid lead.
4. the array base palte according to Claims 2 or 3, it is characterised in that：Between the grid lead and the first boost line
It is provided with insulating barrier.
5. array base palte according to claim 1, it is characterised in that：In a left side between the grid lead and the first boost line
Right parallel construction, and/or, it is in left and right parallel construction between the source lead and the second boost line.
6. array base palte according to claim 1, it is characterised in that：Binding has driving IC on the IC pins.
A kind of 7. display device, it is characterised in that：Including any described array base palte in claim 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720969437.5U CN206931320U (en) | 2017-08-04 | 2017-08-04 | A kind of array base palte and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720969437.5U CN206931320U (en) | 2017-08-04 | 2017-08-04 | A kind of array base palte and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206931320U true CN206931320U (en) | 2018-01-26 |
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ID=61355609
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720969437.5U Active CN206931320U (en) | 2017-08-04 | 2017-08-04 | A kind of array base palte and display device |
Country Status (1)
| Country | Link |
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| CN (1) | CN206931320U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111505875A (en) * | 2020-05-09 | 2020-08-07 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel with array substrate and display device |
-
2017
- 2017-08-04 CN CN201720969437.5U patent/CN206931320U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111505875A (en) * | 2020-05-09 | 2020-08-07 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel with array substrate and display device |
| WO2021227112A1 (en) * | 2020-05-09 | 2021-11-18 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, display panel having same, and display device |
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