CN206892573U - A kind of ECU with CPU redundancy structures - Google Patents

A kind of ECU with CPU redundancy structures Download PDF

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Publication number
CN206892573U
CN206892573U CN201720829965.0U CN201720829965U CN206892573U CN 206892573 U CN206892573 U CN 206892573U CN 201720829965 U CN201720829965 U CN 201720829965U CN 206892573 U CN206892573 U CN 206892573U
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cpu
ecu
interface unit
redundancy structures
memory cell
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CN201720829965.0U
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王建
靳旭
吴生先
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Microvast Power Systems Co Ltd
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Microvast Power Systems Co Ltd
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Abstract

The utility model discloses a kind of ECU with CPU redundancy structures, the ECU includes:First CPU, the 2nd CPU, the 3rd CPU, memory cell, input interface unit and output interface unit;Wherein, the first CPU is identical with the 2nd CPU specifications, and the input interface unit connects the first CPU and the 2nd CPU respectively, and the output interface unit is selectively communicated to the CPU of the first CPU or described 2nd by switching circuit;3rd CPU is respectively communicated with the first CPU and the 2nd CPU, also, the 3rd CPU and switching circuit electrical connection by logic level 232;The memory cell and the 3rd CPU communication connections.The ECU of such a structure can reduce the complexity and development cost of software while ECU safety and stabilities are ensured.

Description

A kind of ECU with CPU redundancy structures
Technical field
It the utility model is related to full-vehicle control field, more particularly to a kind of ECU with CPU redundancy structures.
Background technology
ECU (Electronic Control Unit, i.e. electronic controller unit), also known as " car running computer " of automobile Or " vehicle-mounted computer ", its purposes are exactly to control the transport condition of automobile and realize its various functions.Mainly utilize various biographies The data acquisition of sensor, bus is with exchanging, to judge the intention of vehicle-state and driver and manipulate automobile by actuator.
A types of the VCU (Vehicle Control Unit, i.e. entire car controller) as ECU, is full-vehicle control plan Hardware carrier slightly, it is responsible for coordinating each ECU work, realizes the intention and vehicle efficiency optimization of driver, it is necessary to as far as possible The reliability of entire car controller is improved, is analyzed it is also desirable to gather various status informations, to what is occurred under extreme case Malfunction is identified rapidly and takes corresponding countermeasure.Most of VCU in order to simplify circuit to reduce hardware into This, one CPU of generally use (Central Processing Unit, i.e. central processing unit) carries out signal transacting.This design Scheme shortcoming is it cannot be guaranteed that the accuracy controlled whole system progress energy management and the coordination of each part, works as system data When exchange capacity is big, core devices CPU breaks down, and paralysis disabled state occurs in whole system, and safety and reliability is not It can meet to require, so as to influence vehicle performance, or even have the hidden danger for causing major accident.
As Chinese patent application (CN 101339432A) discloses a kind of finished automobile controller monitoring system and its realization side Method, the finished automobile controller monitoring system include peripheral controllers and entire car controller, and the entire car controller includes host CPU, from CPU With safety line supervisory circuit;Host CPU and communicated, host CPU and led to from CPU from CPU by SPI (Serial Peripheral Interface (SPI)) bus Safety line is crossed with safety line supervisory circuit to be connected;Safety line supervisory circuit is joined directly together by safety line and peripheral controllers, whole Vehicle controller is connected by CAN with peripheral controllers.
Wherein, the realization of finished automobile controller monitoring system comprises the following steps:1) host CPU of entire car controller, be total to from CPU Same collection brake and accelerator pedal signal, and it is direct directly with peripheral controllers I/O port by safety line and safety line supervisory circuit It is connected;2) communication monitoring in the normal mode of operation, is carried out to host CPU from CPU, when host CPU occurs abnormal, replaced from CPU Host CPU directly notifies peripheral controllers by dragging down safety line, Full Vehicle System is entered safe mode.
Above-mentioned finished automobile controller monitoring system by increase on the basis of original single CPU it is a piece of from CPU to substitute out Now abnormal host CPU is run, and then ensures the safety and stability of entire car controller.But above-mentioned entire car controller prison In control system, due to receiving the data from host CPU from CPU using inquiry mode, entire car controller passes through the main program from CPU Periodic queries Status Flag, to judge whether Full Vehicle System enters abnormality, so as to carry out Abnormal Mode Operation, it is this from CPU adds the complexity of ECU software design by the way of SPI carries out communication monitoring to host CPU.
Utility model content
The purpose of this utility model is to provide a kind of ECU with CPU redundancy structures, it is intended to improve ECU securities and The complexity of Software for Design is reduced on the premise of stability.
To use following technical scheme up to this purpose, the utility model:
A kind of ECU with CPU redundancy structures, there is following feature, including:First CPU, the 2nd CPU, the 3rd CPU, deposit Storage unit, input interface unit and output interface unit, wherein, the first CPU and the 2nd CPU specifications are identical, input interface list Member connects the first CPU and the 2nd CPU respectively, and output interface unit is selectively communicated to the first CPU or second by switching circuit CPU;3rd CPU is respectively communicated with the first CPU and the 2nd CPU, also, the 3rd CPU and switching by serial ports (such as logic level 232) Circuit electrically connects;Memory cell and the 3rd CPU communication connections.
The first CPU and the 2nd CPU of same size, when the first CPU normal operations, the 2nd CPU are set in above-mentioned ECU As Hot Spare, and by the CPU of the 3rd cpu monitor the first and the 2nd CPU working condition;When the first CPU breaks down, the 3rd CPU control switching circuit connection output interface units and original the 2nd CPU as Hot Spare, i.e., with the 2nd CPU on behalf of execution First CPU work, so as to ensure the safety and stability of ECU operations.Due to the first CPU of same size and the 2nd CPU Identical runs software only need to be matched, so as to reduce the complexity of software and development cost.
Further, in above-mentioned ECU, also with following feature:Memory cell include FLASH (nonvolatile storage), At least one of FRAM (ferroelectric memory) and EEPROM (Electrical Erasable read-only storage) memory, wherein, FLASH and FRAM is connected to the 3rd CPU by SPI respectively, and EEPROM is connected to the 3rd CPU by IIC (IC bus) or SPI.
In above-mentioned ECU, memory cell is able to record the first CPU and the 2nd CPU operational factor, fault message, plays The effect of black box, it is easy to follow-up diagnosis and repair.
Further, in above-mentioned ECU, also with following feature:Also comprising the system base that the 3rd CPU is connected to by SPI Plinth chip.
Above-mentioned system base chip can be independently-powered to the 3rd CPU.
Further, in above-mentioned ECU, also with following feature:The model MC33907 of system base chip or MC33908。
The higher operational reliabilitys of CPU can guarantee that using the system base chip of above-mentioned model.
Further, in above-mentioned ECU, also with following feature:Switching circuit be DPDT electronic analog swtich or Relay array.
Above-mentioned ECU has the advantages of CPU handoff responses are fast, can realize the first CPU and the 2nd CPU seamless switching.
Further, in above-mentioned ECU, also with following feature:Input interface unit includes digital quantity input module, mould At least one of analog quantity input module and frequency input module.
Further, in above-mentioned ECU, also with following feature:Output interface unit includes multichannel CAN transceiver, number At least one of word amount output module and analog output module.
Further, in above-mentioned ECU, also with following feature:EMI also including power supply and connection power supply (do by electromagnetism Disturb) unit, power supply to the first CPU, the 2nd CPU, memory cell, input interface unit and output interface unit power.
Above-mentioned ECU can reduce electromagnetic interference.
Further, in above-mentioned ECU, also with following feature:First CPU1 and the 2nd CPU2 is MPC5604B cores Piece, the 3rd CPU are S32K144 chips.
Using in the ECU of said chip, the 3rd CPU function of the functional safety grade more than the first CPU and the 2nd CPU is pacified Congruent level, so that it is guaranteed that the 3rd CPU reliably workings.
Brief description of the drawings
Fig. 1 is the structured flowchart of ECU in embodiment.
In accompanying drawing:1st, the first CPU;2nd, the 2nd CPU;3rd, the 3rd CPU;4th, memory cell;41、EEPROM;42、FLASH; 43、FRAM;5th, input interface unit;51st, digital quantity input module;52nd, Analog input mModule;53rd, frequency input module;6、 Switching circuit;7th, output interface unit;71st, CAN transceiver;72nd, digital output module;73rd, analog output module;8th, it is System base chip;9th, power supply;10th, EMI units.
Embodiment
Further illustrate the technical solution of the utility model below in conjunction with the accompanying drawings and by embodiment.
Fig. 1 is the structured flowchart of ECU in embodiment, as shown in figure 1, present embodiments providing one kind has CPU redundancy knots The ECU of structure, the ECU include:First CPU1, the 2nd CPU2, the 3rd CPU3, memory cell 4, input interface unit 5, output interface Unit 7, power supply 9, EMI units 10,.
Specifically, the first CPU1 and the 2nd CPU2 specifications are identical, the 3rd CPU3 is respectively communicated with first by logic level 232 CPU1 and the 2nd CPU2.In the present embodiment, the first CPU1 and the 2nd CPU2 are MPC5604B chips, and the 3rd CPU3 is S32K144 chips.That is chip functions safety of the 3rd CPU3 chip functions safe class higher than the first CPU1 and the 2nd CPU2 Grade.
In the present embodiment, input interface unit 5 connects the first CPU1 and the 2nd CPU2 respectively, wherein, input interface unit 5 Comprising:Digital quantity input module 51, Analog input mModule 52 and frequency input module 53.Certainly, carried in the utility model In the ECU of the other embodiment of confession, input interface unit 5 include digital quantity input module 51, Analog input mModule 52 and It is at least one in frequency input module 53.
In the present embodiment, output interface unit 7 is communicated to the first CPU1 or the 2nd CPU2 by the selectivity of switching circuit 6, and And the 3rd CPU3 and switching circuit 6 electrically connect.Wherein, output interface unit 7 includes:Multichannel CAN transceiver 71, digital quantity are defeated Go out module 72 and analog output module 73, also, digital output module 72 possesses monitoring and diagnostic function.Certainly, exist In the ECU of other embodiment provided by the utility model, output interface unit 7 includes multichannel CAN transceiver 71, digital output In module 72 and analog output module 73 it is at least one can or interface unit 7 include at least all the way CAN receive Send out device 71.
In the present embodiment, switching circuit 6 is preferably DPDT electronic analog swtich, and certainly, switching circuit 6 can also adopt DPDT electronic analog swtich is replaced with relay array.
In the present embodiment, the CPU3 of memory cell 4 and the 3rd communication connection, wherein, memory cell 4 include EEPROM 41, FLASH 42 and FRAM 43.Specifically, FLASH 42 and FRAM 43 is connected to the 3rd CPU3 by SPI, EEPROM 41 by IIC is connected to the 3rd CPU3.Certainly, in ECU provided by the utility model, only need to provide EEPROM41, FLASH42 and At least one of FRAM43 memories.
In the present embodiment, power supply 9 and EMI units 10 connect, also, power supply 9 possesses monitoring and diagnostic function.Power supply 9 to First CPU1, the 2nd CPU2, memory cell 4, input interface unit 5 and output interface unit 7 are powered.
System base chip 8 is connected to the 3rd CPU3 by SPI, i.e., independently-powered from system base chip 8 to the 3rd CPU3. In the present embodiment, the model MC33907 of system base chip 8.
Above-mentioned ECU CPU switching methods use following steps in the present embodiment:
Step 1: electric on ECU, input interface unit 5 is to the first CPU1 and the 2nd CPU2 synchronization output signals, the 3rd CPU3 Monitor the first CPU1 and the 2nd CPU2 working condition, also, the raw information acquiescence that the 3rd CPU3 is stored based on memory cell 4 First CPU1 normal operations, now, output interface unit 7 keep being connected with the first CPU1, and the 2nd CPU2 carries out Hot Spare;
Step 2: when the 3rd CPU3 detects the first CPU1 failures, the 3rd CPU3 sends ready signal to the 2nd CPU2;
If the 2nd CPU2 is ready, the 3rd CPU3 sends switching command to switching circuit 6, output interface unit 7 with 2nd CPU2 is connected;
If the 2nd CPU2 is not ready to ready, the 3rd CPU3 sends reset instruction to the 2nd CPU2, treats that the 2nd CPU is answered After the completion of position, the 3rd CPU sends ready signal again to the 2nd CPU.
Step 3: when the 3rd CPU3 detects the equal failures of the first CPU1 and the 2nd CPU2, ECU is shut down, output interface list First 7 outside output safety control instructions, also, memory cell 4 records the first CPU1 and the 2nd CPU2 fault message.
Certainly, in the CPU switching methods that the present embodiment provides, original letter that the 3rd CPU3 is stored based on memory cell 4 Breath the 2nd CPU2 normal operations of acquiescence, now, output interface unit 7 keeps being connected with the 2nd CPU2, and the first CPU1 carries out heat Backup.
Technical principle of the present utility model is described above in association with specific embodiment, but it should be recognized that this above-mentioned A little descriptions are intended merely to explain principle of the present utility model, and can not be construed in any way to scope of protection of the utility model Concrete restriction.Based on explanation herein, those skilled in the art can associate this practicality not paying creative work Other new embodiments or equivalent substitution, fall within the scope of protection of the utility model.

Claims (9)

  1. A kind of 1. ECU with CPU redundancy structures, it is characterised in that including:First CPU, the 2nd CPU, the 3rd CPU, storage are single Member, input interface unit and output interface unit;
    Wherein, the first CPU is identical with the 2nd CPU specifications, and the input interface unit connects the first CPU respectively With the 2nd CPU, the output interface unit is selectively communicated to the CPU of the first CPU or described 2nd by switching circuit;
    3rd CPU is respectively communicated with the first CPU and the 2nd CPU by serial ports, also, the 3rd CPU and described Switching circuit electrically connects;
    The memory cell and the 3rd CPU communication connections.
  2. 2. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that the memory cell includes At least one of FLASH, FRAM and EEPROM memory;
    Wherein, the FLASH and FRAM is connected to the 3rd CPU by SPI respectively, and the EEPROM is connected by IIC or SPI It is connected to the 3rd CPU.
  3. 3. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that also include and institute is connected to by SPI State the 3rd CPU system base chip.
  4. 4. the ECU according to claim 3 with CPU redundancy structures, it is characterised in that the type of the system base chip Number it is MC33907 or MC33908.
  5. 5. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that the switching circuit is that double-pole is double Throw electronic analog swtich or relay array.
  6. 6. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that the input interface unit includes At least one of digital quantity input module, Analog input mModule and frequency input module.
  7. 7. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that the output interface unit includes At least one of multichannel CAN transceiver, digital output module and analog output module.
  8. 8. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that also including described in power supply and connection The EMI units of power supply, the power supply is to the first CPU, the 2nd CPU, the memory cell, the input interface unit And the output interface unit power supply.
  9. 9. the ECU according to claim 1 with CPU redundancy structures, it is characterised in that the first CPU and described Two CPU are MPC5604B chips, and the 3rd CPU is S32K144 chips.
CN201720829965.0U 2017-07-10 2017-07-10 A kind of ECU with CPU redundancy structures Active CN206892573U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108415334A (en) * 2018-04-04 2018-08-17 苏州妙益科技股份有限公司 A kind of BMS main control modules of three CPU

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108415334A (en) * 2018-04-04 2018-08-17 苏州妙益科技股份有限公司 A kind of BMS main control modules of three CPU

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