CN206864161U - The drive circuit that gate driving circuit and light emitting control drive circuit blend - Google Patents
The drive circuit that gate driving circuit and light emitting control drive circuit blend Download PDFInfo
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- CN206864161U CN206864161U CN201720792306.4U CN201720792306U CN206864161U CN 206864161 U CN206864161 U CN 206864161U CN 201720792306 U CN201720792306 U CN 201720792306U CN 206864161 U CN206864161 U CN 206864161U
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Abstract
The drive circuit that the drive circuit that a kind of gate driving circuit and light emitting control drive circuit blend, the gate driving circuit and light emitting control drive circuit blend includes logic circuitry portions and driving output circuit part；The logic circuitry portions include clock generating unit, trigger signal unit, overall signal's generation unit, gate driving circuit, light emitting control drive circuit；The clock generating unit includes gate clock generation unit and Luminous clock generation unit, the gate driving circuit and light emitting control drive circuit are integral type circuit, raster data model and light emitting control driving integral circuitry are formed, power consumption can be reduced using the utility model and reduce cost.
Description
Technical field
The present invention relates to the circuit of display, especially raster data model and light emitting control drive circuit.
Background technology
All it is progressive scan, the i.e. gate driving circuit or hair of synchronization, only a line because the characteristics of display screen
Photocontrol drive circuit has output, and remaining gate driving circuit or light emitting control drive circuit without output row are without output.
However, the clock of synchronization, control gate drive circuit or the conducting of light emitting control drive circuit is but exported to remaining without defeated
The gate driving circuit or light emitting control drive circuit of trip, thus, cause the load excessive of clock, useless power consumption increase.
The content of the invention
To solve the above problems, blended the invention provides a kind of gate driving circuit and light emitting control drive circuit
The drive circuit that drive circuit, the gate driving circuit and light emitting control drive circuit blend include logic circuitry portions and
Drive output circuit part；The logic circuitry portions include clock generating unit, and trigger signal unit, overall signal produce single
Member, gate driving circuit, light emitting control drive circuit；The clock generating unit include gate clock generation unit and it is luminous when
Clock generation unit, the gate driving circuit and light emitting control drive circuit are integral type circuit, and composition raster data model is with lighting
Control driving integral circuitry.
The raster data model and raster data model and light emitting control driving one that light emitting control driving integral circuitry is that N rows cascade
Body circuit, N are natural number；The raster data model of the N rows cascade drives with light emitting control driving integral circuitry including light emitting control
Circuit and gate driving circuit.
The light emitting control drive circuit include reset transistor, the first transistor, second transistor, third transistor,
4th transistor, the transistor of the 5th transistor the 6th, the 7th transistor and the 8th transistor.
The first end of reset transistor is used to connect gate switch level, and its 3rd end is used to input reset signal, resets
Second end of the second end electrical connection second transistor of transistor, the second end of the 4th transistor, the first of the 5th transistor
End and the first end of the 7th transistor.
The first end connection gate switch level of the first transistor, the second end of the first transistor is electrically connected the second crystal
The first end of pipe.
Second end of second transistor is electrically connected the first end of the 5th transistor, and its 3rd end is used to input light emitting control
Signal.
The first end connection gate switch level of third transistor, the second end of third transistor is electrically connected the 4th crystal
The first end of pipe.
Second end of the 4th transistor is electrically connected the first end of the 7th transistor, and its 3rd end is used to input light emitting control
Signal.
Second end of the 5th transistor is electrically connected the first end of the 6th transistor, and its 3rd end is used to input light emitting control
Signal.
The second end connection gate switch level of 6th transistor.
Second end of the 7th transistor is electrically connected the first end of the 8th transistor, and its 3rd end is used to input light emitting control
Signal.
The second end connection gate switch level of 8th transistor.
The gate driving circuit includes the first NOT gate, the 9th transistor, the tenth transistor and the 11st transistor；It is luminous
Control the input of the second end and the first NOT gate of the reset transistor of drive circuit to be electrically connected, the output end of the first NOT gate with
The 3rd end electrical connection of 9th transistor, the first end of the 9th transistor input with the first end electrical connection of the tenth transistor
Clock, the second end of the 9th transistor and the second end electrical connection of the tenth transistor are simultaneously electric with the second end of the 11st transistor
Gas connection output gate drive signal, the 3rd end of the 11st transistor are electrically connected with the 3rd end of the tenth transistor, and the tenth
3rd end of one transistor is electrically connected with the input of the first NOT gate, the first end connection gate switch electricity of the 11st transistor
It is flat.
Preferably, the drive circuit that the gate driving circuit and light emitting control drive circuit blend also includes N row levels
The limitation clock of connection enters unit, and N is natural number, and the limitation clock enters unit and raster data model and light emitting control driving one
The corresponding connection of body circuit.
Drive Nth row display when, Nth row limitation clock enter unit only allow clock export to Nth row raster data model with
Light emitting control drives the light emitting control drive circuit of integral circuitry, Nth row raster data model and light emitting control driving integral circuitry
Light emitting control drive circuit exports LED control signal, only allows clock to export to Nth row raster data model and light emitting control and drives
The gate driving circuit of integral circuitry.
The drive circuit that described gate driving circuit and light emitting control drive circuit blends, the limitation clock enter
Unit includes the first nor gate, the second NOT gate, the tenth two-transistor, the 13rd transistor, the 14th transistor and the 3rd NOT gate.
3rd end of the 13rd transistor is electrically connected with the output of the first nor gate, its first end and clock generating unit electricity
Gas connection is electrically connected with input clock, its second end with the 3rd NOT gate input.
3rd end of the 14th transistor is electrically connected with the input of the second NOT gate, its first end and clock generating unit
Electrical connection is electrically connected with input clock, its second end with the second NOT gate input.
3rd end of the tenth two-transistor is electrically connected with the output end of the first nor gate, and its second end and the 3rd NOT gate are defeated
Enter end electrical connection, first end connection gate switch level.
The Nth row limitation clock enters the first nor gate input N-1 rows LED control signal and N+1 rows of unit
During LED control signal, N is natural number, it is allowed to which clock is exported to Nth row light emitting control drive circuit.
Preferably, the drive circuit that the raster data model and optical drive blend also includes level conversion unit, the electricity
Flat converting unit is arranged between logic circuitry portions and driving output circuit part, sets logic circuitry portions relatively low
Level, driving output circuit part higher level can be set.
Technical scheme has following advantageous effects：Unit is entered using limitation clock, makes clock only defeated
Go out to the light emitting control drive circuit of current output row, clock and drive electricity without output to the light emitting control of non-present output row
Road, useless power consumption is avoided, and then reduce power consumption；It is simultaneously current to export capable light emitting control drive circuit LED control signal again
As the clock of gate driving circuit, clock is set only to export to the gate driving circuit of current output row, clock is without exporting extremely
The gate driving circuit of non-present output row, it also avoid useless power consumption；Using raster data model and light emitting control driving one electricity
The design on road, eliminates the signal wire of required setting when being separately provided two driver elements, and section eliminates the number of circuit element
And area, reduce power consumption and reduce cost；Logic circuit and driving output circuit are separated using level conversion unit, realizes and patrols
Collect circuit part and use relatively low level, driving output circuit part uses higher level, also further reduces power consumption.
Brief description of the drawings
The drive circuit frame that a kind of gate driving circuit of Fig. 1 embodiment of the present invention and light emitting control drive circuit blend
Figure；
The drive circuit frame that another gate driving circuit of Fig. 2 embodiment of the present invention and light emitting control drive circuit blend
Figure；
The drive circuit frame that another gate driving circuit of Fig. 3 embodiment of the present invention and light emitting control drive circuit blend
Figure；
Fig. 4 present invention limitation clocks enter element circuit figure；
The raster data model of Fig. 5 embodiment of the present invention and light emitting control driving integral circuitry figure；
The timing diagram of Fig. 6 embodiment illustrated in fig. 1 of the present invention；
The circuit diagram of level conversion unit LS1 in Fig. 7 embodiment illustrated in fig. 1 of the present invention；
The circuit diagram of level conversion unit LS2 in Fig. 8 embodiment illustrated in fig. 1 of the present invention；
Fig. 9 embodiment of the present invention driving that another gate driving circuit and light emitting control drive circuit blend again electricity
Road block diagram；
The timing diagram of Figure 10 embodiment illustrated in fig. 9 of the present invention.
Embodiment
For the technical characteristic of the present invention and effect can be described in detail, and can be realized according to the content of this specification, below
Embodiments of the present invention are further illustrated.
The drive circuit that Fig. 1 provides a kind of raster data model for the present embodiment and optical drive blends, the raster data model electricity
The drive circuit that road and light emitting control drive circuit blend includes logic circuitry portions（1）With driving output circuit part（2）,
Logic circuitry portions include 2 clock generating units（3）, one is two ECK clock generating units（It can also be three or more
Bar ECK clock generating units, principle and two ECK clock generating units are the same, can be selected according to actual conditions, specifically
See Fig. 9）, another be two GCK clock generating units（Can also be three or a plurality of GCK clock generating units, principle with
Two ECK clock generating units are the same, can be selected according to actual conditions）, trigger signal unit（4）, overall signal production
Raw unit（5）, the cascade of N rows raster data model and light emitting control drive integral circuitry（6）, the cascade of N rows limitation clock enter it is single
Member（20）（N is natural number）And level conversion unit（21）, raster data model and light emitting control drive integral circuitry（6）For N row levels
The raster data model of connection and light emitting control driving integral circuitry, it includes gate driving circuit and light emitting control drive circuit；Limitation
Clock enters unit（20）With raster data model and light emitting control driving integral circuitry（6）Corresponding connection.
When driving Nth row display, Nth row limitation clock enters unit（20）Only clock is allowed to export to Nth row grid
Driving and light emitting control driving integral circuitry（6）In light emitting control drive circuit, Nth row raster data model and light emitting control drive
Integral circuitry（6）Light emitting control drive circuit output LED control signal, only allow a clock export to Nth row raster data model with
Light emitting control drives integral circuitry（6）Gate driving circuit.
Light emitting control drive circuit described in the present embodiment includes reset transistor（7）, the first transistor（8）, it is second brilliant
Body pipe（9）, third transistor（10）, the 4th transistor（11）, the 5th transistor（12）, the 6th transistor（13）, the 7th crystal
Pipe（14）With the 8th transistor（15）.
Reset transistor（7）First end（71）For connecting grid high level, its 3rd end（73）Resetted for inputting
Signal, the second end of reset transistor（72）It is electrically connected second transistor（9）The second end（92）, the 4th transistor（10）'s
Second end（102）, the 5th transistor（11）First end（111）With the 7th transistor（13）First end（131）.
The first transistor（8）First end（801）Connect grid high level, the first transistor（8）The second end（802）Electricity
Gas connects second transistor（9）First end（901）.
Second transistor（9）The second end（901）It is electrically connected the 5th transistor（11）First end（111）, it the 3rd
End（903）For inputting Nth row LED control signal.
Third transistor（10）First end（101）Connect grid high level, third transistor（10）The second end（102）
It is electrically connected the 4th transistor（10）First end（101）.
4th transistor（11）The second end（112）It is electrically connected the 7th transistor（14）First end（141）, it the 3rd
End（113）For inputting N+1 row LED control signals.
5th transistor（12）The second end（122）It is electrically connected the 6th transistor（13）First end（131）, it the 3rd
End（123）For inputting Nth row LED control signal.
6th transistor（13）The second end（132）Connect grid low level.
7th transistor（14）The second end（142）It is electrically connected the 8th transistor（15）First end（151）, it the 3rd
End（143）For inputting N+1 row LED control signals.
8th transistor（15）The second end（152）Connect grid low level.
Gate driving circuit described in the present embodiment includes the first NOT gate（16）, the 9th transistor（17）, the tenth transistor
（18）With the 11st transistor（19）；The reset transistor of light emitting control drive circuit（7）The second end（72）With the first NOT gate
（16）Input electrical connection, the first NOT gate（16）Output end and the 9th transistor（17）The 3rd end（173）Electrically connect
Connect, the 9th transistor（17）First end（171）With the tenth transistor（18）First end（181）It is electrically connected input clock
（GCK）, the 9th transistor（17）The second end（172）With the tenth transistor（18）The second end（182）Electrical connection, and with the
11 transistors（19）The second end（192）Electrical connection output N+1 row gate drive signals, the 11st transistor（19）'s
3rd end（193）With the tenth transistor（18）The 3rd end（183）Electrical connection, the 11st transistor（19）The 3rd end
（193）With the first NOT gate（16）Input electrical connection, the 11st transistor（19）First end（191）Connect the low electricity of grid
It is flat.
In order to further reduce power consumption, the drive circuit that the raster data model and optical drive blend also includes level conversion
Unit（21）, the level conversion unit（21）It is arranged at logic circuitry portions（1）With driving output circuit part（2）Between,
Make logic circuitry portions（1）Relatively low level can be set, drive output circuit part（2）Higher level can be set.This
Level conversion unit in embodiment（21）LS1 and level conversion unit（21）LS2 raises/reduced the height of drive output signal respectively
Low level, so as to realize that logical gate uses relatively low level, driving output par, c uses higher level, in actual use
Can be according to demand using LS1 or using LS2 or simultaneously using the power consumption of LS1 and LS2 to reduce.
Embodiment is illustrated with reference to Fig. 1, overall signal's output unit（5）Access per a line raster data model with
Light emitting control drives integral circuitry（6）, before drive circuit that the raster data model and optical drive blend is started working, overall situation letter
Number output unit（5）Integral circuitry is driven to every a line raster data model and light emitting control first（6）In Mid point set, own
Mid level points be height, all LED control signal level is low, all gate drive signal level for height.
As shown in figure 4, because limitation clock enters unit, clock ECK1 is only in N-1 row LED control signals（Em_
N-1）With N+1 row LED control signals（Em_N+1）Time width（T1T2T3T4）The interior raster data model that can enter is with lighting
Control driving integral circuitry（6）, Mid signals and LED control signal control clock GCK1 enter gate driving circuit.
The T1 periods：Third transistor（10）With the 4th transistor（11）Place branch road work, keeps Nth row light emitting control letter
Number（Em_N）To be low.
The T2 periods：5th transistor（12）With the 6th transistor（13）Place branch road work, triggering Nth row light emitting control letter
Number（Em_N）For height.
The T3 periods：7th transistor（14）With the 8th transistor（15）Place branch road work, keeps Nth row light emitting control letter
Number（Em_N）For height.
The T4 periods：The first transistor（8）And second transistor（9）Place branch road work, triggers Nth row LED control signal
（Em_N）To be low.Hereafter the 5th transistor（12）With the 6th transistor（13）Place branch road keeps Nth row LED control signal
（Em_N）To be low.
In T2 the and T3 periods, Nth row LED control signal is exported（Em_N）, in the T3 periods, Mid_N signals and N
Row LED control signal（Em_N）Clock GCK1 is controlled by gate driving circuit output Nth row gate drive signal（Gate_
N）.
Same principle, the clock of N+1 rows（ECK2）Enter unit in the limitation clock of N+1 rows（20）Control under enter
Raster data model and light emitting control driving integral circuitry（6）, the clock of Mid points and LED control signal the control N+1 rows of N+1 rows
GCK2's enters gate driving circuit.
As shown in Figure 7 and Figure 8：LED control signal（Em_N）And gate drive signal（gate_N）It is low-level logic letter
Number, it passes through level conversion unit LS1, LS2（21）Turn into the drive signal of high level afterwards.But can also be as needed, Dan Cai
Use level conversion unit（21）LS1, or list use level conversion unit（21）LS2, or level conversion unit is used simultaneously（21）
LS1 and level conversion unit（21）LS2, while Vgl, VgL, Vgh, VgH concrete numerical value are not required, it is workable
Numerical value is all in protection domain.
Raster data model drives integral circuitry to export the pixel to viewing area after the buffer that overdrives with light emitting control.
Phase inverter number in driving buffer can adjust LED control signal（Em_N）And gate drive signal（gate _N）For
Positive pulse or negative pulse, depending on specifically having an actual conditions.
The drive circuit embodiment that Fig. 2 provides another raster data model and optical drive blends, the present embodiment and earlier figures 1
The difference for the drive circuit that raster data model described in embodiment and optical drive blend is not include level conversion unit（21）, this reality
It is identical with the embodiment of earlier figures 1 to apply the remainder of a circuit, no longer specifically describes here.
The drive circuit embodiment that Fig. 3 provides another raster data model and optical drive blends, the present embodiment and earlier figures 1
The difference for the drive circuit that raster data model described in embodiment and optical drive blend is not include limitation clock unit（20）And electricity
Flat converting unit（21）, the remainder of the present embodiment circuit is identical with the embodiment of earlier figures 1, no longer does specifically retouch here
State.
Fig. 9 provides the drive circuit embodiment that another raster data model and optical drive blend again, and Figure 10 is the present embodiment
Timing diagram, the difference of the present embodiment and embodiment illustrated in fig. 1 is that have three ECK and GCK clock generating units, its principle and electricity
Road and two ECK and GCK clock generating units are identicals, are no longer specifically described here.
In the embodiment of the present invention, due to entering unit using limitation clock, clock is set only to export to the hair of current output row
Photocontrol drive circuit, light emitting control drive circuit of the clock without output to non-present output row, avoids useless power consumption, enters
And reduce power consumption；Simultaneously the light emitting control drive circuit LED control signal of current output row again as gate driving circuit when
Clock, clock is only exported to the gate driving circuit of current output row, clock and driven without output to the grid of non-present output row
Dynamic circuit, it also avoid useless power consumption.Using raster data model and the design of light emitting control driving integral circuitry in embodiment, save
The signal wire of required setting during two driver elements is separately provided, section eliminates the number and area of circuit element, reduces work(
Consume and reduce cost.Logic circuit and driving output circuit are separated using level conversion unit in embodiment, realize logic electricity
Road part uses relatively low level, and driving output circuit part uses higher level, also further reduces power consumption.
It should be noted that each particular technique feature described in above-mentioned embodiment, in reconcilable feelings
Under condition, it can be combined by any suitable mode.In order to avoid unnecessary repetition, the present invention is to various possible groups
Conjunction mode is not described further.
Above with reference to embodiment to the present invention have been described in detail, it is illustrative and not restrictive, is not taking off
From changing and modifications under present general inventive concept, within protection scope of the present invention.
Claims (5)
1. the drive circuit that a kind of gate driving circuit and light emitting control drive circuit blend, the gate driving circuit and hair
The drive circuit that photocontrol drive circuit blends includes logic circuitry portions and driving output circuit part；The logic circuit
Part includes clock generating unit, trigger signal unit, overall signal's generation unit, gate driving circuit, light emitting control driving
Circuit；The clock generating unit includes gate clock generation unit and Luminous clock generation unit, it is characterised in that the grid
Pole drive circuit and light emitting control drive circuit are integral type circuit, composition raster data model and light emitting control driving integral circuitry.
2. the drive circuit that a kind of gate driving circuit as claimed in claim 1 and light emitting control drive circuit blend, it is special
Sign is that the raster data model is the raster data model that N rows cascade and light emitting control driving one with light emitting control driving integral circuitry
Body circuit, N are natural number；
The light emitting control drive circuit includes reset transistor, the first transistor, second transistor, third transistor, the 4th
Transistor, the transistor of the 5th transistor the 6th, the 7th transistor and the 8th transistor；
The first end of reset transistor is used to connect gate switch level, and its 3rd end is used to input reset signal, resets crystal
Pipe the second end electrical connection the second end of second transistor, the second end of the 4th transistor, the 5th transistor first end and
The first end of 7th transistor；
The first end connection gate switch level of the first transistor, the second end electrical connection second transistor of the first transistor
First end；
Second end of second transistor is electrically connected the first end of the 5th transistor, and its 3rd end is used to input light emitting control letter
Number；
The first end connection gate switch level of third transistor, the second end of third transistor is electrically connected the 4th transistor
First end；
Second end of the 4th transistor is electrically connected the first end of the 7th transistor, and its 3rd end is used to input light emitting control letter
Number；
Second end of the 5th transistor is electrically connected the first end of the 6th transistor, and its 3rd end is used to input light emitting control letter
Number；
The second end connection gate switch level of 6th transistor；
Second end of the 7th transistor is electrically connected the first end of the 8th transistor, and its 3rd end is used to input light emitting control letter
Number；
The second end connection gate switch level of 8th transistor；
The gate driving circuit includes the first NOT gate, the 9th transistor, the tenth transistor and the 11st transistor；Light emitting control
Second end of the reset transistor of drive circuit is electrically connected with the input of the first NOT gate, the output end of the first NOT gate and the 9th
The 3rd end electrical connection of transistor, the first end of the 9th transistor and the first end electrical connection input clock of the tenth transistor
Signal, the second end of the 9th transistor and the second end electrical connection of the tenth transistor are simultaneously electric with the second end of the 11st transistor
Gas connection output gate drive signal, the 3rd end of the 11st transistor are electrically connected with the 3rd end of the tenth transistor, and the tenth
3rd end of one transistor is electrically connected with the input of the first NOT gate, the first end connection gate switch electricity of the 11st transistor
It is flat.
3. the drive circuit that a kind of gate driving circuit as claimed in claim 2 and light emitting control drive circuit blend, its
It is characterised by, the drive circuit that the gate driving circuit and light emitting control drive circuit blend also includes the limit of N rows cascade
Clock processed enters unit, and N is natural number, and the limitation clock enters unit and raster data model and light emitting control driving integral circuitry
Corresponding connection；
When driving Nth row display, Nth row limitation clock, which enters unit, only allows clock to export to Nth row light emitting control driving electricity
Road, Nth row light emitting control drive circuit output LED control signal only allow clock to export to the gate driving circuit of Nth row.
4. the drive circuit that gate driving circuit as claimed in claim 3 and light emitting control drive circuit blend, its feature
It is, the limitation clock, which enters unit, includes the first nor gate, the second NOT gate, the tenth two-transistor, the 13rd transistor, the
14 transistors and the 3rd NOT gate；
3rd end AND OR NOT gate output electrical connection of the 13rd transistor, its first end electrically connect with Luminous clock generation unit
Connect with input clock, its second end is electrically connected with the 3rd NOT gate input；
3rd end of the 14th transistor is electrically connected with the input of the second NOT gate, its first end and Luminous clock generation unit
Electrical connection is electrically connected with input clock, its second end with the second NOT gate input；
The output end electrical connection of 3rd end AND OR NOT gate of the tenth two-transistor, its second end and the 3rd NOT gate input are electric
Connection, first end connection gate switch level；
The Nth row limitation clock enters the first nor gate input N-1 rows LED control signal of unit and N+1 rows light
During control signal, N is natural number, it is allowed to which clock is exported to Nth row light emitting control drive circuit.
5. the drive circuit that the gate driving circuit and light emitting control drive circuit as described in claim 3 or 4 blend, it is special
Sign is, the drive circuit that the raster data model and optical drive blend also includes level conversion unit, the level conversion list
Member is arranged between logic circuitry portions and driving output circuit part, logic circuitry portions is set relatively low level,
Driving output circuit part can set higher level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201720792306.4U CN206864161U (en) | 2017-07-03 | 2017-07-03 | The drive circuit that gate driving circuit and light emitting control drive circuit blend |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720792306.4U CN206864161U (en) | 2017-07-03 | 2017-07-03 | The drive circuit that gate driving circuit and light emitting control drive circuit blend |
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| CN206864161U true CN206864161U (en) | 2018-01-09 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093393A (en) * | 2017-07-03 | 2017-08-25 | 成都晶砂科技有限公司 | The drive circuit that gate driving circuit and light emitting control drive circuit are blended |
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2017
- 2017-07-03 CN CN201720792306.4U patent/CN206864161U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107093393A (en) * | 2017-07-03 | 2017-08-25 | 成都晶砂科技有限公司 | The drive circuit that gate driving circuit and light emitting control drive circuit are blended |
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