CN206863732U - A kind of control device of NAND Flash controllers - Google Patents
A kind of control device of NAND Flash controllers Download PDFInfo
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- CN206863732U CN206863732U CN201621377812.9U CN201621377812U CN206863732U CN 206863732 U CN206863732 U CN 206863732U CN 201621377812 U CN201621377812 U CN 201621377812U CN 206863732 U CN206863732 U CN 206863732U
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Abstract
The utility model discloses a kind of control device of NAND Flash controllers, including definition layer module, analytic sheaf module, physics realization layer module, NAND Flash interface modules, the definition layer module, analytic sheaf module, physics realization layer module, NAND Flash interface modules are sequentially connected, and all modules are realized using digital logic circuit；The physics realization floor module realizes circuit including ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential；ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential realize that circuit is connected with analytic sheaf module respectively, and state of a control electromechanics road, physical layer interface sequential realize that circuit is connected with each other.The utility model provides a kind of hardware unit for control NAND Flash particles, after defining related execute instruction wherein so that NAND Flash controllers are with can completing different interface type NAND flash storage particles correct to be read, programs, erasing operation.
Description
Technical field
NAND Flash controllers field is the utility model is related to, more particularly to a kind of control of NAND Flash controllers
Device.
Background technology
With the rapid development of electronic information society, data storage requirement amount shows explosive growth, non-volatile
Memory NAND Flash flash memories have the characteristics that high power capacity, high density, high-performance, therefore application is more and more extensive.Complete
Correct reading and writing, erasing operation to NAND Flash flash memory particles, it is necessary to hardware control according to sequential interface and operational order
Memory is operated.
The interface of different NAND Flash particles manufacturers is different, for unified NAND Flash interfaces, is united in the world
One is two kinds of interface, and one kind is ONFI interfaces, and another kind is Toggle interfaces.Every kind of interface type has ONFI2.x again
With ONFI3.x and ONFI4.x, Toggle1.0, Toggle2.0 different editions.To these different editions interface types
NAND particles, which such as can complete to read, program, wipe at operation, the NAND Flash controllers, to be needed to include total interface sequential control
System, it just can guarantee that the nand memory particle for accessing different vendor's different editions interface type.
Because the operation to NAND Flash particles includes programming, reading, erasing operation, and operated under distinct interface agreement
Sequential is different.Therefore the control to NAND Flash needs comprising all various types of programmings, read, erasing sequential, and
Between different NAND Flash particles manufacturers (magnesium light, Samsung, Toshiba, Hynix ...), access operation for identical and also can
There is different browsing process.NAND Flash need to be completely covered the reading and writing of all different type particles, erasing operation and not
The different generation of biconditional operation sequential, so also needing to add many extra logic control circuits completions.It is as shown in figure 3, different
Interface and every kind of interface corresponding to programming, read, erasing operation sequential it is different, be required for increasing control circuit in the controller
Complete correspondingly SECO.
In order to meet the different NAND Flash particle manipulations of various interface types described above, and need to meet difference
The distinct interface operation of particle manufacturer.According to existing technology, needed to increase control logic circuit according to the different time sequential routines,
And the different types of control of different vendor needs to increase extra hardware logic electric circuit again, then causes hardware circuit extremely complex,
And with the renewal of NAND Flash particle sequential, when controller just needs to redefine the particle of logic circuit satisfaction renewal
Sequence, hardware cost are very high and portable excessively poor.
With the continuous development of NAND Flash particles and being continuously increased for function sequential so that this quasi-controller is to hardware
The complexity more and more higher of circuit, logistical overhead is also very big, is unfavorable for safeguarding and transplants.These shortcomings considerably increase NAND
The research and development time of Flash controller chip products and cost.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of control device of NAND Flash controllers, in fact
Now NAND Flash particles are controlled and provide a kind of hardware foundation, after definition is corresponding in a device performs order,
So that NAND Flash controllers disclosure satisfy that various types of NAND Flash interface particles of existing various manufacturers, and it is complete
It is correct to read, program, wiping behaviour into different interface type (asynchronous, ONFI or Toggle) NAND flash storage particles
Make, can also be flexibly adapted to the new temporal aspect that following NAND Flash particles development occurs.
In order to solve the above technical problems, the technical solution adopted in the utility model is：
A kind of control device of NAND Flash controllers, including definition layer module, analytic sheaf module, physics realization layer mould
Block, NAND Flash interface modules, the definition layer module, analytic sheaf module, physics realization layer module, NAND Flash connect
Mouth mold block is sequentially connected, and all modules are realized using digital logic circuit.
Further, the physics realization floor module includes ECC encoding and decoding drive circuit, state of a control electromechanics road, bottom
Interface sequence realizes circuit；ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential realize circuit respectively with
Analytic sheaf module is connected, and state of a control electromechanics road, physical layer interface sequential realize that circuit is connected with each other.
Compared with prior art, advantageous effects of the present utility model are：There is provided a kind of for controlling NAND Flash
The hardware foundation of particle, can using the NAND Flash controllers of definition after related execute instruction is defined in a device
The different types of particle sequential of distinct interface is configured using ARM CPU, hardware logic electric circuit expense is greatly reduced,
And the various various interface sequences of manufacturer's particle are can adapt to without increase logic hardware circuit every time, possess very strong flexibility
And portability.
Brief description of the drawings
Fig. 1 is the utility model hardware circuit diagram.
Fig. 2 is NAND Flash interface schemas.
Fig. 3 is NAND Flash controllers control particle scheme.
Fig. 4 is the multichannel NAND Flash controller block diagrams that ARM CPU are defined.
Fig. 5 is that sequential is latched in order.
Fig. 6 is address latch sequential.
Fig. 7 is asynchronous to write data to NAND Flash sequential.
Fig. 8 is that ONFI2.0 reads data time sequence from NAND Flash.
Fig. 9 is that Toggle2.0 interface types read data time sequence from NAND Flash particles.
Figure 10 is that Toggle2.0 interface types write data to NAND Flash sequential.
Figure 11 is the NAND Flash controller programming operational flowcharts that the utility model is implemented.
Figure 12 is the NAND Flash controller read operation flow charts that the utility model is implemented.
Figure 13 is the NAND Flash controller erasing operation flow charts that the utility model is implemented.
Figure 14 is that the NAND Flash controller asynchronous interfaces that the utility model is implemented write data waveform figure.
Figure 15 is the NAND Flash controller ONFI3.0 interface readings of the utility model implementation according to oscillogram.
Embodiment
The utility model is described in further detail with reference to the accompanying drawings and detailed description.
NAND Flash interface sequence includes asynchronous interface, ONFI interfaces, Toggle interfaces, and wherein ONFI interfaces divide again
For ONFI2.x and ONFI3.x and ONFI4.x different editions, Toggle interfaces are divided into Toggle1.0 and Toggle2.0, such as scheme
Shown in 1, the sequential of distinct interface has a part variation, and version sequential has been consistent with Toggle sequential after ONFI3.x.
NAND Flash interfaces, which access, to be included to the configuration to give an order, each corresponding register of instruction, during these access interfaces
The register group of sequence realizes that the particle of NAND Flash difference sequential accesses.Analytic sheaf performs NAND Flash defined in parsing
Controller related register instructs, and translates its register instruction and specific command control signal is sent into physics realization layer, by
The generation of execution and corresponding sequential of the physics realization layer to specific instruction, produces different timing control signals and is sent to NAND
Flash interface modules, complete the combination of all sequential needed for operation NAND Flash particles.NAND Flash interfaces connect
NAND Flash particles, the interface sequence group of configuration is issued to NAND flash storage particles, completed to NAND Flash
The programming of memory, reading, erasing operation；Including：
The sequential interface that NAND Flash particles are operated in NAND Flash controllers is defined by ARM CPU；
It is ONFI or Toggle types to select NAND Flash access interfaces, and different types of different editions are such as
ONFI2.x, ONFI3.x and ONFI4.x or Toggle1.0, Toggle2.0 selection；
ECC (Error Correcting Code) module is to NAND Flash flash memories in definition NAND Flash controllers
The configuration of error correcting capability during particle manipulation.NAND Flash controllers of the present utility model can realize 64bit/page,
The error correction of 70bit/page, 48bit/page different stalls ability；
Programming data register interface is defined to provide to NAND Flash particles to be programmed for NAND Flash controllers
Data；
Define the specific timing instructions of NAND Flash controllers operation NAND Flash particles, including CE enable which
The definition of NAND Flash storage particles, CLE specifically accesses the definition of NAND Flash grain commands, ALE accesses NAND Flash
The definition of grain address.And DQS signal definition of ONFI and Toggle types driving data read-write sampling etc..NAND Flash are controlled
Device control register processed is as shown in table 1.
The register that table 1 defines
2nd, the register group that parsing configuration definition layer is configured, analytic sheaf are posted using the parsing of command decoder circuit is a series of
Storage group, translate into specific control signal instruction in NAND Flash controllers, including the selection of NAND Flash interfaces, NAND
Flash controllers to be driven the control signal of the different operating timing protocols of NAND Flash particles, NAND Flash controls
The data that device programs toward particle, the concrete operations order after the command decoder circuit decoding of analytic sheaf are sent to physics reality
ECC encoding and decoding drive module, control sub-state machine module, the physical layer interface sequential of existing layer realize module.
3rd, physics realization layer will be delivered to after the register parsing of definition, physics realization layer is real to the instruction after specific parsing
Apply, perform register group, produce defined operation NAND Flash particle sequential combinations, drive NAND flash interfaces, it is complete
The control of paired NAND Flash particles.
The NAND Flash controllers that the utility model is implemented are before according to the configuration time sequential routine, it is necessary first to are configuring
Definition layer configures NAND Flash interface registers, as shown in Figure 3, it is necessary to configure operation NAND Flash different interface types,
Optional type has asynchronous interface, Toggle1.0, Toggle2.0, ONFI2.x, ONFI3.x.And need to configure ECC error correction
Ability, NAND Flash controllers could control the error correcting capability of ECC coding-decoding circuits to drive.Due to NAND of the present utility model
Flash controller methods and device are used for the NAND flash storage particles for controlling multichannel, at most can while or divide
When operate the NAND flash storages of 8 passages, as shown in figure 4, therefore setting operation logical in NAND Flash controllers
The register configuration of road number so that the NAND Flash controllers neatly memory of 1 passage of control operation or multiple passages,
Access speed and memory capacity are considerably increased using the NAND Flash controllers of multichannel.
The NAND Flash controller programming operating processes that the utility model is implemented are as shown in figure 11, are specially：Select CE,
That is NAND Flash controllers selection that to be accessed NAND Flash particles, configure CE registers, the value configured is i.e.
Which CE selected；80h is sent, 80h orders are that the instruction of operation is programmed to NAND Flash particles, configuration CLE deposits
Device, its value are 80h；Address is sent, that is, operates the specific address of NAND Flash particle storage arrays, configures ALE registers,
Including Die addresses, plan addresses, Page addresses, Block addresses；Programming data register is configured, selection will be toward NAND
The data of Flash particles programming；10h orders are sent, configure CLE command registers；Stand-by period register is configured, wait drags down
WaitRBHigh.These register-combinatorials are configured finally to produce as schemed by NAND Flash control devices of the present utility model
10 timing diagrams are supplied to NAND flash storage particles, so as to complete the programming operation to memory.
The NAND Flash controller read operation flows that the utility model is implemented are as shown in figure 12, as needed configuration
NAND Flash interface registers, such as configuration NAND Flash interfaces are Toggle2.0 interface types, and read operation configuration has
Body is：CE is selected, configures CE registers, which CE is the values configured select；00h is sent, configures CLE registers, its value is
00h；Address is sent, configures ALE registers, including Die addresses, plan addresses, Page addresses, Block addresses；Send 30h lives
Order, configuration CLE registers are 30h；Stand-by period register is configured, wait drags down WaitRBHigh；Reading state simultaneously judges Rdy
Whether it is equal to 1, if equal to 1, reads data to interface.Configure these register-combinatorials and pass through NAND of the present utility model
Flash control devices finally produce timing diagram as described in Figure 9 and are supplied to NAND flash storage particles, so as to complete to depositing
The read operation of reservoir.
The NAND Flash controller erasing operation flows that the utility model is implemented are as shown in figure 13, are specially：Select CE,
CE registers are configured, which CE is the values configured select, and sends 60h, configures CLE registers, its value is 60h；Send address,
The block address configuration of NAND Flash particles is wiped, configures ALE registers, i.e. Block addresses；Configure stand-by period deposit
Device, wait drag down WaitRBHgh.
The utility model device includes definition layer module, analytic sheaf module, physics realization layer module, NAND Flash interfaces
Module, all modules use digital logic circuit to realize, as shown in Figure 1.
The definition layer module：For realize define NAND Flash controllers operation NAND Flash particles it is specific when
Sequence instructs, configuration NAND Flash interface registers, ECC error correction capabilities register, channel number register, stand-by period deposit
Device, programming data register, CE registers, CLE registers, ALE registers, WE registers, RE registers, CLK registers,
DQS registers.This series of registers combines, and completing NAND Flash controllers needs control parameter and control NAND
Flash particle manipulation sequential.The definition layer module is connected with analytic sheaf module.
The analytic sheaf module：A series of NAND Flash controllers register groups defined for parsing definition layer, will
Instruction after parsing is sent to physics realization layer module.
The analytic sheaf module is completed to parse the different specific control signals of definition register by command decoder circuit
Operation.
The physics realization layer module：For realizing the specific register instruction for decoding out, different modules, root are delivered to
The specific sequential for accessing NAND Flash particles is realized according to the register interface of configuration, is sent to NAND Flash interface modules.
The physics realization floor module includes ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential reality
Existing circuit.The ECC encoding and decoding drive circuit is used to receive ECC error correction capabilities register of the command decoder circuit to definition,
According to configuration error correcting capability value, ECC encoding and decoding drive circuit according to different error correcting capability values, adjustment verification code length provide to
LDPC coding/decoding modules.The state of a control electromechanics road is used for the series of instructions according to parsing register-combinatorial, different behaviour
It is respectively transmitted as instruction and gives state of a control electromechanics road, the state control of the circuit realiration difference sequential function.State of a control is electromechanical
Road produces a series of access NAND Flash configured according to different sequential interface signals by a series of sub-state machine circuits
Particle timing control signal.State of a control machine state machine circuit will distinguish caused by a series of access NAND Flash operation
Clock signal delivers to physical layer interface sequential and realizes circuit one by one, physical layer interface sequential realize circuit module according to instruction carry out CE,
The combination in ALE, CLE, DQS, CLK, WE, RE different command time sequential routine forms the overall sequential for accessing NAND Flash interfaces,
NAND Flash interface modules, such as configuration Toggle2.0 interface types are sent to, and configures operation NAND Flash
The order CLE of grain is to read, then as shown in Figure 9 eventually through timing diagram caused by physics realization layer.Completed according to the sequential
The data read operation of NAND Flash particles.
The NAND Flash interface modules will access particle sequential after combining and provided to NAND flash storages, press
The accurate time sequential routine driving NAND Flash particles of sighting target, complete the reading, programming, erasing operation of NAND flash storages.
Claims (2)
1. a kind of control device of NAND Flash controllers, it is characterised in that including definition layer module, analytic sheaf module, thing
Reason realizes layer module, NAND Flash interface modules, the definition layer module, analytic sheaf module, physics realization layer module, NAND
Flash interface modules are sequentially connected, and all modules are realized using digital logic circuit；
The definition layer module：The specific sequential that NAND Flash controllers operation NAND Flash particles are defined for realizing refers to
Order, configuration NAND Flash interface registers, ECC error correction capabilities register, channel number register, stand-by period register, volume
Journey data register, CE registers, CLE registers, ALE registers, WE registers, RE registers, CLK registers, DQS deposits
Device；This series of registers combines, and completing NAND Flash controllers needs control parameter and control NAND Flash particle behaviour
Make sequential；The definition layer module is connected with analytic sheaf module；
The analytic sheaf module：A series of NAND Flash controllers register groups defined for parsing definition layer, will be parsed
Instruction afterwards is sent to physics realization layer module；
The analytic sheaf module is completed to the different specific control signal parsing operations of definition register by command decoder circuit；
The physics realization layer module：For realizing the specific register instruction that decodes out, deliver to different modules, according to
The register interface put realizes the specific sequential for accessing NAND Flash particles, is sent to NAND Flash interface modules；
The physics realization floor module includes ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential realization electricity
Road；
The ECC encoding and decoding drive circuit is used to receive ECC error correction capabilities register of the command decoder circuit to definition, according to
Error correcting capability value is configured, ECC encoding and decoding drive circuit is provided to LDPC according to different error correcting capability values, adjustment verification code length
Coding/decoding module；
The state of a control electromechanics road is used for the series of instructions according to parsing register-combinatorial, and different operational orders passes respectively
State of a control electromechanics road is given, the state control of the circuit realiration difference sequential function；State of a control electromechanics road according to it is different when
Sequence interface signal, a series of access NAND Flash particle SECO configured are produced by a series of sub-state machine circuits
Signal；State of a control machine state machine circuit will distinguish caused by a series of access NAND Flash operation clock signal one by one
Deliver to physical layer interface sequential and realize circuit, physical layer interface sequential realize circuit module according to instruction carry out CE, ALE, CLE, DQS,
The combination in CLK, WE, RE different command time sequential routine forms the overall sequential for accessing NAND Flash interfaces, is sent to NAND
Flash interface modules, and the order CLE for configuring operation NAND Flash particles is reading, then eventually through physics realization layer
Caused timing diagram；The data read operation of NAND Flash particles is completed according to the sequential；
The NAND Flash interface modules will access particle sequential after combining and provided to NAND flash storages, according to mark
Accurate time sequential routine driving NAND Flash particles, complete the reading, programming, erasing operation of NAND flash storages.
A kind of 2. control device of NAND Flash controllers as claimed in claim 1, it is characterised in that the physics realization
Floor module realizes circuit including ECC encoding and decoding drive circuit, state of a control electromechanics road, physical layer interface sequential；ECC encoding and decoding drive
Circuit, state of a control electromechanics road, physical layer interface sequential realize that circuit is connected with analytic sheaf module respectively, and state of a control is electromechanical
Road, physical layer interface sequential realize that circuit is connected with each other.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111913666A (en) * | 2020-07-31 | 2020-11-10 | 深圳忆联信息系统有限公司 | Method and device compatible with Nand particles with different protocols, computer equipment and storage medium |
| TWI782341B (en) * | 2018-11-14 | 2022-11-01 | 慧榮科技股份有限公司 | Flash memory controller and encoding circuit within flash memory controller |
-
2016
- 2016-12-13 CN CN201621377812.9U patent/CN206863732U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI782341B (en) * | 2018-11-14 | 2022-11-01 | 慧榮科技股份有限公司 | Flash memory controller and encoding circuit within flash memory controller |
| CN111913666A (en) * | 2020-07-31 | 2020-11-10 | 深圳忆联信息系统有限公司 | Method and device compatible with Nand particles with different protocols, computer equipment and storage medium |
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Effective date of registration: 20210709 Address after: No. 1503, unit 1, building 2, No. 352, Zhonghe Renhe Road, high tech Zone, Chengdu, Sichuan 610212 Patentee after: Chengdu kexinrui Electronic Technology Co.,Ltd. Address before: 610225 24 section 1 Xuefu Road, Southwest Airport Economic Development Zone, Chengdu, Sichuan Patentee before: Chengdu University of Information Technology |