CN206807422U - Frequency discriminator, the phaselocked loop of wide catching range - Google Patents
Frequency discriminator, the phaselocked loop of wide catching range Download PDFInfo
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- CN206807422U CN206807422U CN201720697609.8U CN201720697609U CN206807422U CN 206807422 U CN206807422 U CN 206807422U CN 201720697609 U CN201720697609 U CN 201720697609U CN 206807422 U CN206807422 U CN 206807422U
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Abstract
Frequency discriminator, the phaselocked loop of wide catching range, belong to optical communication field, and the utility model is to solve the problems, such as that traditional frequency discriminator catching range is still extremely limited.The utility model includes d type flip flop DFF1, Full differential operational amplifier A0, current source I1, NPN transistor Q1, Q2, resistance R1, R2, electric capacity C1；Voltage comparator COMP1, COMP2, latch L1 and door AND1, AND2；Frequency discriminator controls charge pump when the VCO V-CLKs exported differ farther out with data frequency, charge pump continuous firing can be driven, make clock frequency Step wise approximation data rate, and the charge pump that control when both frequencies are close frequency discriminator is stopped, the work for completing frequency discriminator and phase discriminator switches.
Description
Technical field
The utility model belongs to optical communication field, is related to a kind of frequency discriminator with wider catching range.
Background technology
In fiber optic communication integrated circuit, because signal can introduce shake and noise, it is necessary to clock number in transmittance process
Come to carry out Clock Extraction to data according to restoring circuit, and data are purified with the clock extracted and then eliminate shake.When
Clock data recovery circuit includes phase-locked loop structures, and phase-locked loop structures include frequency discriminator (FD), phase discriminator (PD), charge pump
(CP), low pass filter (LPF), voltage controlled oscillator (VCO), it is shown in Figure 1.Phase discriminator (PD) provides the seizure work(of phase
Can, but because the catching range of phase discriminator (PD) is typically small, it is necessary to be caught by the advanced line frequency of frequency discriminator (FD) so that when
Phase discriminator (PD) further phase acquisition is transferred to when clock frequency is close with data rate again, control VCO frequencies of oscillation are clock frequency
Rate, which is finally reached and phase identical with data rate, has the relation determined.Seizure of the high performance phaselocked loop to frequency discriminator (FD)
Scope proposes higher requirement.
Fig. 2 gives the circuit structure of traditional frequency discriminator.CLKIIt is clock signal caused by voltage controlled oscillator (VCO), warp
After crossing phase adjustment, CLKQIt is and CLKIPhase differs 90 ° of quadrature clock signal, DINFor data-signal.For obtain clock with
Phase relation between data with data-signal to clock signal, it is necessary to be sampled.With reference to Fig. 3 timing diagram explanation
The operation principle of traditional frequency discriminator.
1. work as CLKIFrequency (VOC output frequencies) is faster than DINFrequency (data frequency), i.e. CLKIPhase is ahead of DIN, it is referred to as
Fast clock, referring to Fig. 3 (a).The D in d type flip flop FF1INRising edge samples CLK all the timeIHigh level, therefore FF1 output end
XAHigh level is exported always.The D in d type flip flop FF2INRising edge starts a period of time sampling CLKQLow level, FF2 output
Hold XBExport low level；After a period of time, DINRising edge is changed to sample CLKQHigh level, therefore XBOutput by low level
It is changed into high level.The X in d type flip flop FF3BRising edge samples XAHigh level, therefore FF3 output end VOUTExport high level control
Charge pump (CP) charging processed so that VCO output frequencies decline, gradually consistent with data frequency.
2. work as CLKIFrequency (VOC output frequencies) is slower than DINFrequency (data frequency), i.e. CLKIPhase lags behind DIN, it is referred to as
Slow clock, referring to Fig. 3 (b).The D in d type flip flop FF1INRising edge samples CLK all the timeILow level, therefore XAExport always low
Level.The D in d type flip flop FF2INRising edge starts a period of time sampling CLKQLow level, XBExport low level；By one section
Time, DINRising edge is changed to sample CLKQHigh level, therefore XBOutput high level is changed into from low level.In d type flip flop FF3
Middle XBRising edge samples X all the timeALow level, therefore VOUTExport low level control charge pump (CP) electric discharge so that VCO output frequencies
Rate rises, gradually consistent with data frequency.
The frequency discriminator of traditional structure is still to be selected by the lead lag relationship of clock phase to enter line frequency.In data frequency
When rate and close clock frequency difference, CLKI, CLKQWith DINPhase corresponding relation be immovable, so in XBTo XASampling
When, will be because of clock signal frequency soon with obtaining V slowlyOUTThe low and high level output uniquely determined.Frequency phase-difference farther out when,
Clock and the phase corresponding relation of data will no longer be situations that Fig. 3 is presented, such as when data frequency and pair of clock frequency
Situation is answered as shown in Fig. 4：Upper a data signal DINRising edge correspond to clock signal clkIAnd CLKQLow level, next bit
Data-signal DINRising edge corresponded to clock signal clkIAnd CLKQHigh level, now data DINTo clock signal clkI's
Sampled result XAWith data DINTo clock signal clkQSampled result XBWill occur level upset simultaneously, can not keep unique
The level of determination, and then cause d type flip flop FF3 XBTo XASampled result VOUTIt is uncertain, it can not correctly control charge pump to be
Charging or electric discharge.When input signal shake is larger, there is random phase offset in each cycle, beyond traditional frequency discriminator
Narrower catching range, easily produces losing lock, the problem of causing the stability of a system to be deteriorated, it is difficult to meet High-Performance Phase-Locked for
The requirement of frequency discriminator catching range.
The content of the invention
The purpose of the utility model is to solve the problems, such as that traditional frequency discriminator catching range is still extremely limited, there is provided one
The frequency discriminator of the wide catching range of kind, the utility model can reduce phaselocked loop losing lock, increase the stability of a system.
The frequency discriminator of wide catching range described in the utility model, frequency discriminator is by controlling charge pump to low pass filter charge and discharge
Electricity, to change the control voltage LF to voltage controlled oscillator, and then the clock frequency for changing voltage controlled oscillator tends to data frequency；
Frequency discriminator includes d type flip flop DFF1, Full differential operational amplifier A0, frequency difference decision circuit and charge and discharge control electricity
Road；
D type flip flop DFF1 is sampled using differential data signals DIN, DINB to differential clock signal CK, CKB, D triggerings
Device DFF1 sampled result is amplified by Full differential operational amplifier A0, and Full differential operational amplifier A0 amplification result is sent to frequency
Poor decision circuit；The output end of frequency difference decision circuit is connected with the control terminal of charge-discharge control circuit；Full differential operational amplifier
A0 inverse output terminal is connected with the discharge control terminal of charge pump；The discharge and recharge instruction output end and electric charge of charge-discharge control circuit
The discharge and recharge command input of pump is connected；
When differential data signals DIN, DINB and differential clock signal CK, CKB frequency phase-difference are remote, d type flip flop DFF1
Output quickly overturn, frequency difference decision circuit output high level；
Control voltage LF is gradually increasing by 0, then drop to stable output during, frequency discriminator includes following three
Individual working condition；
First working condition：Meet condition LF<M1, then charge-discharge control circuit control charge pump filled to low pass filter
Electricity, control voltage LF rise；M1 is minimum voltages of the control voltage LF of voltage controlled oscillator VCO in the range of linearity；
Second working condition：Meet condition M1≤LF≤M2, then charge-discharge control circuit control charge pump keeps a upper shape
State, continue to charge to low pass filter, control voltage LF continues to rise；M2 is that the control voltage LF of voltage controlled oscillator VCO is online
Ceiling voltage in property region；
3rd working condition：Meet condition LF>M2, then in the Full differential operational amplifier A0 high electricity of inverse output terminal output
Usually, charge-discharge control circuit control charge pump allows low pass filter to discharge, and control voltage LF declines；In fully differential operation amplifier
During device A0 inverse output terminal output low level, charge-discharge control circuit temporarily ceases the control to charge pump, does not charge and does not put
Electricity, control voltage LF keep constant；
3rd working condition is the stepped decline processes of control voltage LF, when being down to differential data signals DIN, DINB and difference
When dividing the frequency phase-difference of clock signal CK, CKB near, d type flip flop DFF1 output steady and continuous, frequency difference decision circuit exports low electricity
It is flat；Control charge pump is stopped, and control voltage LF is stable to be exported.
Preferably, frequency difference decision circuit includes current source I1, NPN transistor Q1, NPN transistor Q2, resistance R1, resistance R2
With electric capacity C1；
The in the same direction of Full differential operational amplifier A0, inverse output terminal connect NPN transistor Q1 base stage, NPN crystal respectively
Pipe Q2 base stage；
NPN transistor Q1 emitter stage, NPN transistor Q2 emitter stage connect current source I1 anode, current source simultaneously
I1 negativing ending grounding；
NPN transistor Q1 colelctor electrode, NPN transistor Q2 colelctor electrode pass through resistance R1, resistance R2 connection direct currents respectively
Power vd D；NPN transistor Q1 colelctor electrode and NPN transistor Q2 colelctor electrode connect electric capacity C1 both ends respectively；NPN crystal
Output end of the pipe Q1 colelctor electrode as frequency difference decision circuit；
Resistance R1 resistance is less than resistance R2 resistance.
Preferably, charge-discharge control circuit include voltage comparator COMP1, voltage comparator COMP2, latch L1, with
Door AND1 and with door AND2；
Control voltage LF output ends connect the input in the same direction of voltage comparator COMP1 input and COMP2 in the same direction simultaneously
End；
Level M1, level M2 be respectively connected to voltage comparator COMP1 reverse input end, voltage comparator COMP2 it is anti-
To input；
Voltage comparator COMP1 output end connection latch L1 S ends；
Voltage comparator COMP2 output end connection latch L1 R ends；
Latch L1 Q ends connection and door AND1 another input；
Latch L1'sEnd connection and door AND2 another input；
With the charging instruction output end of door AND1 output end as charge-discharge control circuit；
With the electric discharge instruction output end of door AND2 output end as charge-discharge control circuit.
Preferably, charge pump includes current source I2, current source I3, charge switch S1, discharge switch S2 and discharge switch S3；
Current source I2, charge switch S1, discharge switch S2, discharge switch S3 and current source I3 are sequentially connected in series, and current source
I2 anode connection dc source VDD, current source I3 negativing ending grounding；
Charge switch S1 control terminal is connected with the charging instruction output end of charge-discharge control circuit；
Discharge switch S2 control terminal is connected with the electric discharge instruction output end of charge-discharge control circuit；
Discharge switch S3 control terminal is connected with Full differential operational amplifier A0 inverse output terminal.
Preferably, low pass filter includes resistance R3, electric capacity C2 and electric capacity C3,
Charge switch S1 and discharge switch S2 common node connect resistance R3 one end, electric capacity C2 one end and control simultaneously
Voltage LF output ends processed, electric capacity C2 other end ground connection；
Resistance R3 other end connection electric capacity C3 one end, electric capacity C3 other end ground connection.
Preferably, differential clock signal CK, CKB be separately input into d type flip flop DFF1 data input pin D ends,End；Difference
Divided data signal DIN, DINB be separately input into d type flip flop DFF1 input end of clock C-terminal,End；The output end Q of d type flip flop
End,End connects differential operational amplifier A0 in the same direction, reverse input end respectively.
Preferably, when the remote scope of differential data signals DIN, DINB and differential clock signal CK, CKB frequency phase-difference is
Clock frequency exceeds the scope of data center's frequency ± 1%, on the contrary then nearer for the two frequency phase-difference..
According to another aspect of the present utility model, there is provided a kind of phaselocked loop, including described in above-mentioned preferably any one
The frequency discriminator of wide catching range.
The beneficial effects of the utility model are：The charge pump of frequency discriminator control is in the VCO V-CLKs exported and data frequency
When rate is differed farther out, charge pump continuous firing can be driven, makes clock frequency Step wise approximation data rate, and can be in both frequencies
The charge pump for controlling frequency discriminator when close is stopped, and the work for completing frequency discriminator and phase discriminator switches.The seizure model
Enclose global covering, whole VCO covering linear zone within (VCO bound clock frequency i.e. corresponding to voltage M1 and M2) all
Seizure can be realized, has reached the catching range of non-constant width, the occurrence of greatly reducing losing lock, adds the stabilization of system
Property, traditional frequency discriminator performance is had a distinct increment.
The frequency acquisition scope of the utility model frequency discriminator is big, clock frequency beyond data center's frequency ± 1%~±
It also can accurately be caught in the range of 10%, there is no losing lock to show using the phaselocked loop of the utility model frequency discriminator in the wide range of frequencies
As.
The scope that the utility model can catch frequency is corresponding with the VCO limit frequency of clock up and down, i.e., the utility model can
The scope for catching frequency is voltage M1 reference clock frequencies corresponding with M2, also implies that the utility model catching range can root
Factually border circuit performance requirement is changed.And traditional frequency discriminator capture range is solidification, can not voluntarily changed.
Brief description of the drawings
Fig. 1 is the theory diagram of phaselocked loop；
Fig. 2 is the circuit theory diagrams of traditional frequency discriminator；
Fig. 3 is the clock of traditional frequency discriminator and the timing diagram of data；Wherein (a) is the timing diagram under fast clock status；(b)
For the timing diagram under slow clock status；
Fig. 4 is the timing diagram for the clock and data for causing traditional frequency discriminator failure；
Fig. 5 is the theory diagram of the frequency discriminator of wide catching range described in the utility model；
Fig. 6 is the circuit theory diagrams of the frequency discriminator of wide catching range described in the utility model；
Fig. 7 is the control voltage raising and lowering stage voltage change of the frequency discriminator of wide catching range described in the utility model
Schematic diagram；
Fig. 8 is the principle of phase lock loop block diagram using frequency discriminator described in the utility model.
Embodiment
With reference to Fig. 5 to Fig. 8, the utility model is described in further detail.
In the prior art, when being designed for the frequency discriminator in phaselocked loop, clock frequency and data are commonly available to
The nearer situation of frequency phase-difference (clock frequency is poor within ± the 1% of data center's frequency with data center's frequency), when two
Person's frequency phase-difference farther out (difference of clock frequency and data center's frequency exceeds ± 1% scope of data center's frequency) when, often
There is loss of lock, conventional phase locked loops have the defects of stability of a system is poor, easy losing lock, and frequency acquisition scope is small.This practicality
A kind of new frequency discriminator and phaselocked loop of new proposition, its frequency acquisition scope is big, in interior (clock frequency and number in a big way
According to the difference of centre frequency within ± 1%~± the 10% of data center's frequency) can accurately it catch.The utility model frequency discriminator
Capture range be ± 1~± 10%, during scope less than ± 1%, FD=0, transfer to phase discriminator to continue to capture.
Embodiment：Referring to Fig. 6, charge pump includes current source I2, current source I3, charge switch S1, discharge switch S2, electric discharge
Switch S3；Low pass filter includes resistance R3, electric capacity C2 and electric capacity C3.
The frequency discriminator of wide catching range includes d type flip flop DFF1, Full differential operational amplifier A0, current source I1, NPN crystal
Pipe Q1, NPN transistor Q2, resistance R1, resistance R2, electric capacity C1；Voltage comparator COMP1, voltage comparator COMP2, latch
L1 and door AND1 and door AND2；
Differential clock signal CK, CKB be separately input into d type flip flop DFF1 data input pin D ends,End；Differential data
Signal DIN, DINB be separately input into d type flip flop DFF1 input end of clock C-terminal,End；The output end Q ends of d type flip flop,End
Differential operational amplifier A0 in the same direction, reverse input end is connected respectively；Full differential operational amplifier A0 in the same direction, inverse output terminal
NPN transistor Q1 base stage, NPN transistor Q2 base stage is connected respectively；
NPN transistor Q1 emitter stage, NPN transistor Q2 emitter stage connect current source I1 anode, current source simultaneously
I1 negativing ending grounding；
NPN transistor Q1 colelctor electrode, NPN transistor Q2 colelctor electrode pass through resistance R1, resistance R2 connection direct currents respectively
Power vd D；NPN transistor Q1 colelctor electrode and NPN transistor Q2 colelctor electrode connect electric capacity C1 both ends respectively；NPN crystal
Output end FD of the pipe Q1 colelctor electrode as frequency difference decision circuit；
Resistance R1 resistance is less than resistance R2 resistance.
Control voltage LF output ends connect the input in the same direction of voltage comparator COMP1 input and COMP2 in the same direction simultaneously
End；
Level M1, level M2 be respectively connected to voltage comparator COMP1 reverse input end, voltage comparator COMP2 it is anti-
To input；
Voltage comparator COMP1 output end E connection latch L1 S ends；
Voltage comparator COMP2 output end F connection latch L1 R ends；
Latch L1 Q ends connection and door AND1 another input；
Latch L1'sEnd connection and door AND2 another input；
Charge switch S1 control terminal is connected with door AND1 output end G；
Discharge switch S2 control terminal is connected with door AND2 output end H.
Current source I2, charge switch S1, discharge switch S2, discharge switch S3 and current source I3 are sequentially connected in series, and current source
I2 anode connection dc source VDD, current source I3 negativing ending grounding；
Charge switch S1 control terminal is connected with the charging instruction output end of charge-discharge control circuit；
Discharge switch S2 control terminal is connected with the electric discharge instruction output end of charge-discharge control circuit；
Discharge switch S3 control terminal goes out end with Full differential operational amplifier A0 reverse defeated FD1B and is connected.
Charge switch S1 and discharge switch S2 common node connect resistance R3 one end, electric capacity C2 one end and control simultaneously
Voltage LF output ends processed, electric capacity C2 other end ground connection；
Resistance R3 other end connection electric capacity C3 one end, electric capacity C3 other end ground connection.
Differential data signals DIN, DINB be input to d type flip flop DFF1 clock end C-terminal,End, and to being input to DFF1
The differential clock signal D ends of data terminal,End is sampled.When clock frequency and data frequency are close, and clock frequency
Less than data frequency so that during the rising edge of the advanced clock of rising edge of data, sampling output Q is 0；Another situation clock frequency
When rate is higher than data frequency so that during the rising edge of the rising edge lagging clock of data, sampling output Q is 1；The 0 of now Q holdings
Or 1 be that steady and continuous is continuous.Now frequency difference decision circuit output FD=0, connects to characterize clock frequency and data frequency
Closely, then AND1, AND2 export 0, and S1, S2 are in off-state, no matter in FD1B=0 S3 disconnects, or during FD1B=1
S3 is closed, and does not influence charging and discharging state, i.e. frequency discriminator is not controlled charge pump, and it will be by phase discriminator, by phase demodulation by control
Device further carries out phase acquisition.
When clock frequency and far data frequency phase-difference, because the characteristic of d type flip flop itself, sampling output Q will be 0
And quickly overturn between 1.
D type flip flop DFF1 is output to Full differential operational amplifier A0, and signal amplifies by A0, there is provided certain gain and enhancing
Current driving ability, A0 output A in the same direction and reversely output B and DFF1 positive output Q and is reversely exportedLevel height
Corresponding identical, NPN transistor Q1 and Q2 base stage is passed in Full differential operational amplifier A0 output.
Design resistance R1 resistances are less than resistance R2 resistances, and in original state, C points voltage is more than D point voltages, therefore
FD outputs are 1, are also 1 with door AND1 and with a door AND2 input FD.The closed and disconnected for now switching S1 and S2 is complete
Controlled by the input L with door AND1 and with door AND2 input LB.During whole frequency discrimination, control voltage LF change
As shown in Figure 7.
1. when clock frequency and data frequency phase-difference are far, the level point of A, B two will quickly be overturn between zero and one, C and D points
Voltage because electric capacity C1 presence, can not quick response change, therefore C points voltage still be higher than D point voltages, and FD keeps exporting 1.
VCO control voltage LF is carried out with level M1 and M2 respectively as input in voltage comparator COMP1, COMP2
Comparing, level M1 and level M2 correspond to minimum and maximum levels of the control voltage LF of VCO frequencies of oscillation in linear zone respectively,
Then there are three kinds of situations in LF and M1 and M2 comparative result：LF is less than M1, LF and is more than M1 and is more than M2 less than M2, LF.
When LF voltages begin to ramp up from 0 and are less than voltage M1, E, F export 0, and latch L1 S ends input is defeated for 1, R ends
Enter for 0.L1 Q ends output is 1,End output 0.Now FD is 1, and the output G with door AND1 is 1, switch S1 closures.With door
AND2 output is 0, switchs S2 disconnection.Charge pump charges to electric capacity C2 and C3, VCO control voltage LF is increased.
For LF voltages between M1 and M2, latch L1 S ends input is that the input of 0, R ends is 0.Now latch L1, which is in, protects
Hold state.Charge pump keeps charging to electric capacity C3 and electric capacity C2 so that VCO control voltage LF persistently rises.
When LF is risen to just above M2, latch L1 S ends input is that the input of 0, R ends is 1, latch L1 L output ends
It is 1 for 0, LB output ends.Switch S1 to disconnect, switch S2 closures, control voltage LF enters the decline stage.Now electric capacity C3 and electricity
Whether appearance C2, which discharges, also needs to the Automatic level control of the reverse output FD1B by Full differential operational amplifier A0, when FD1B is 1, puts
Electric switch S3 is closed, electric capacity C3 and electric capacity C2 electric discharges.When FD1B is 0, although discharge switch S2 is closed, discharge switch S3 breaks
Open, charge switch S1 also disconnects, and electric capacity C3 and electric capacity C2 neither charge nor discharged, and frequency discriminator temporarily ceases the control to charge pump
System.
2. during the decline of LF voltages, referring to Fig. 7, control voltage LF declines process to be stepped, during discharge condition then
It is then voltage maintaining segment during the not discharge condition that do not charge, this is the process that control voltage LF slowly declines, in the mistake for descending branch
Cheng Zhong, clock frequency are gradually drawn close farther out with data frequency by differing, when clock frequency and close (the clock frequency of data frequency phase-difference
Rate is poor within ± the 1% of data center's frequency with data center's frequency), when clock frequency is slightly larger than data frequency, A 1,
B is 0, and now C points voltage is less than D point voltages, FD outputs 0.Charge switch S1 and discharge switch S2 disconnects, and charge pump stops work
Make, do not charge and also do not discharge, the work of frequency discriminator is completed, and transfers to phase discriminator to carry out further phase acquisition
Control voltage LF does not give phase discriminator power and data frequency is caught in ascent stage, frequency discriminator, and
The LF decline stages carry out data frequency seizure, because the control voltage LF rates of rise are too fast.And due to switching S3 presence,
And rationally design electric capacity C2 and C3 value so that control voltage LF decline stage is step shape descending at slow speed state, among it
There is a bit of horizontal stable time in gap, be advantageous to frequency acquisition.
Phaselocked loop using frequency discriminator of the present utility model is as shown in Figure 8.
Based on above-mentioned analysis, it is seen that the utility model utilizes frequency discriminator cleverly structure and the electricity with latch control terminal
Lotus pump is combined, and frequency acquisition can be realized in the whole linear zones of VCO (the VCO clock frequencies corresponding to voltage M1-M2),
And traditional frequency discriminator only can realize seizure in less scope near centre frequency, the utility model compares traditional frequency discriminator
There is tremendous increase in terms of catching range, greatly reduce the possibility of losing lock generation, add the stability of system.
Although the utility model is described herein with reference to specific embodiment, it should be understood that, this
A little embodiments are only principle of the present utility model and the example of application.It should therefore be understood that can be to exemplary reality
Apply example and carry out many modifications, and can be designed that other arrangements, this reality limited without departing from appended claims
With new spirit and scope.It should be understood that it can be combined by way of different from described by original claim
Different dependent claims and feature specifically described herein.It will also be appreciated that the spy with reference to described by separate embodiments
Sign can be used in other embodiments.
Claims (8)
1. the frequency discriminator of wide catching range, frequency discriminator is by controlling charge pump to low pass filter discharge and recharge, to change to voltage-controlled
The control voltage LF of oscillator, and then the clock frequency for changing voltage controlled oscillator tends to data frequency；
It is characterised in that it includes d type flip flop DFF1, Full differential operational amplifier A0, frequency difference decision circuit and charge and discharge control electricity
Road；
D type flip flop DFF1 is sampled using differential data signals DIN, DINB to differential clock signal CK, CKB, d type flip flop
DFF1 sampled result is amplified by Full differential operational amplifier A0, and Full differential operational amplifier A0 amplification result is sent to frequency difference
Decision circuit；The output end of frequency difference decision circuit is connected with the control terminal of charge-discharge control circuit；Full differential operational amplifier A0
Inverse output terminal be connected with the discharge control terminal of charge pump；The discharge and recharge instruction output end and charge pump of charge-discharge control circuit
Discharge and recharge command input be connected；
When differential data signals DIN, DINB and differential clock signal CK, CKB frequency phase-difference are remote, d type flip flop DFF1's is defeated
Go out quick upset, frequency difference decision circuit output high level；
Control voltage LF is gradually increasing by 0, then drop to stable output during, frequency discriminator includes following three works
Make state；
First working condition：Meet condition LF<M1, then charge-discharge control circuit control charge pump to low pass filter charge, control
Voltage LF processed rises；M1 is minimum voltages of the control voltage LF of voltage controlled oscillator VCO in the range of linearity；
Second working condition：Meeting condition M1≤LF≤M2, then charge-discharge control circuit control charge pump keeps laststate, after
Continue and charged to low pass filter, control voltage LF continues to rise；M2 is the control voltage LF of voltage controlled oscillator VCO in the range of linearity
Interior ceiling voltage；
3rd working condition：Meet condition LF>M2, then export high level in Full differential operational amplifier A0 inverse output terminal
When, charge-discharge control circuit control charge pump allows low pass filter to discharge, and control voltage LF declines；In Full differential operational amplifier
During A0 inverse output terminal output low level, charge-discharge control circuit temporarily ceases the control to charge pump, does not charge and does not discharge,
Control voltage LF keeps constant；
3rd working condition is the stepped decline processes of control voltage LF, when being down to differential data signals DIN, DINB and difference
When clock signal CK, CKB frequency phase-difference are near, d type flip flop DFF1 output steady and continuous, frequency difference decision circuit output low level；
Control charge pump is stopped, and control voltage LF is stable to be exported.
2. the frequency discriminator of wide catching range according to claim 1, it is characterised in that frequency difference decision circuit includes current source
I1, NPN transistor Q1, NPN transistor Q2, resistance R1, resistance R2 and electric capacity C1；
The in the same direction of Full differential operational amplifier A0, inverse output terminal connect NPN transistor Q1 base stage, NPN transistor Q2 respectively
Base stage；
NPN transistor Q1 emitter stage, NPN transistor Q2 emitter stage connect current source I1 anode simultaneously, current source I1's
Negativing ending grounding；
NPN transistor Q1 colelctor electrode, NPN transistor Q2 colelctor electrode pass through resistance R1, resistance R2 connection dc sources respectively
VDD；NPN transistor Q1 colelctor electrode and NPN transistor Q2 colelctor electrode connect electric capacity C1 both ends respectively；NPN transistor Q1
Output end of the colelctor electrode as frequency difference decision circuit；
Resistance R1 resistance is less than resistance R2 resistance.
3. the frequency discriminator of wide catching range according to claim 2, it is characterised in that charge-discharge control circuit includes voltage
Comparator COMP1, voltage comparator COMP2, latch L1, with door AND1 and with door AND2；
Control voltage LF output ends connect the input in the same direction of voltage comparator COMP1 input and COMP2 in the same direction simultaneously；
Level M1, level M2 be respectively connected to voltage comparator COMP1 reverse input end, voltage comparator COMP2 it is reverse defeated
Enter end；
Voltage comparator COMP1 output end connection latch L1 S ends；
Voltage comparator COMP2 output end connection latch L1 R ends；
Latch L1 Q ends connection and door AND1 another input；
Latch L1'sEnd connection and door AND2 another input；
With the charging instruction output end of door AND1 output end as charge-discharge control circuit；
With the electric discharge instruction output end of door AND2 output end as charge-discharge control circuit.
4. the frequency discriminator of wide catching range according to claim 3, it is characterised in that charge pump includes current source I2, electricity
Stream source I3, charge switch S1, discharge switch S2 and discharge switch S3；
Current source I2, charge switch S1, discharge switch S2, discharge switch S3 and current source I3 are sequentially connected in series, and current source I2
Anode connects dc source VDD, current source I3 negativing ending grounding；
Charge switch S1 control terminal is connected with the charging instruction output end of charge-discharge control circuit；
Discharge switch S2 control terminal is connected with the electric discharge instruction output end of charge-discharge control circuit；
Discharge switch S3 control terminal is connected with Full differential operational amplifier A0 inverse output terminal.
5. the frequency discriminator of wide catching range according to claim 3, it is characterised in that low pass filter include resistance R3,
Electric capacity C2 and electric capacity C3,
Charge switch S1 and discharge switch S2 common node connect resistance R3 one end, electric capacity C2 one end and control electricity simultaneously
Press LF output ends, electric capacity C2 other end ground connection；
Resistance R3 other end connection electric capacity C3 one end, electric capacity C3 other end ground connection.
6. the frequency discriminator of wide catching range according to claim 1, it is characterised in that differential clock signal CK, CKB distinguish
Input to d type flip flop DFF1 data input pin D ends,End；Differential data signals DIN, DINB are separately input into d type flip flop
DFF1 input end of clock C-terminal,End；The output end Q ends of d type flip flop,End connects the same of differential operational amplifier A0 respectively
To, reverse input end.
7. the frequency discriminator of wide catching range according to claim 1, it is characterised in that differential data signals DIN, DINB and
The scope that differential clock signal CK, CKB frequency phase-difference are remote is scope of the clock frequency beyond data center's frequency ± 1%, instead
It is then nearer for the two frequency phase-difference.
8. a kind of phaselocked loop, it is characterised in that include the frequency discrimination of the wide catching range as any one of claim 1 to 7
Device.
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| CN201720697609.8U CN206807422U (en) | 2017-06-15 | 2017-06-15 | Frequency discriminator, the phaselocked loop of wide catching range |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107276585A (en) * | 2017-06-15 | 2017-10-20 | 哈尔滨工业大学（威海） | Frequency discriminator, the phaselocked loop of wide catching range |
| CN108494397A (en) * | 2018-01-22 | 2018-09-04 | 西安电子科技大学 | A kind of voltage-controlled oscillator circuit and phaselocked loop |
-
2017
- 2017-06-15 CN CN201720697609.8U patent/CN206807422U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107276585A (en) * | 2017-06-15 | 2017-10-20 | 哈尔滨工业大学（威海） | Frequency discriminator, the phaselocked loop of wide catching range |
| CN107276585B (en) * | 2017-06-15 | 2023-08-15 | 厦门亿芯源半导体科技有限公司 | Wide capture range discriminator and phase locked loop |
| CN108494397A (en) * | 2018-01-22 | 2018-09-04 | 西安电子科技大学 | A kind of voltage-controlled oscillator circuit and phaselocked loop |
| CN108494397B (en) * | 2018-01-22 | 2021-09-21 | 西安电子科技大学 | Voltage-controlled oscillator circuit and phase-locked loop |
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