CN206759420U - Bidirectional level conversion circuit - Google Patents
Bidirectional level conversion circuit Download PDFInfo
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- CN206759420U CN206759420U CN201720594115.7U CN201720594115U CN206759420U CN 206759420 U CN206759420 U CN 206759420U CN 201720594115 U CN201720594115 U CN 201720594115U CN 206759420 U CN206759420 U CN 206759420U
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Abstract
Bidirectional level conversion circuit, it is related to technical field of circuit design, it includes：Amplifier U1, resistance R1, resistance R2, diode D1, positive electricity source interface VCC, first electric level interface VCC1_IO and second electrical level interface VCC2_IO, first electric level interface VCC1_IO connection resistance R1, resistance R1 connects resistance R2 respectively, second electrical level interface VCC2_IO and amplifier U1 input in the same direction, resistance R2 connects GND and amplifier U1 reverse input end respectively, amplifier U1 power positive end connection positive electricity source interface VCC, amplifier U1 power supply negative terminal meets GND, amplifier U1 output end connection diode D1 positive pole, diode D1 negative pole connects the first electric level interface VCC1_IO, the magnitude of voltage of positive electricity source interface VCC input amplifier U1 power positive ends is equal with the work-based logic level value of high level chip.The bidirectional level conversion circuit is built using common electronic component, and the discrete component quantity being related to is few, and structure is extremely succinct, compact, small volume, is built while suitable for realizing multidiameter delay I/O logic level conversion in exiguous space.
Description
Technical field
Technical field of circuit design is the utility model is related to, more particularly to a kind of bidirectional level conversion circuit.
Background technology
Level conversion is often used in design of electronic circuits, particularly in digital circuit product widely used today,
The logic chip that various producers release deposits the horizontal simultaneously disunity of logic level at work, and this results in different digit chips and existed
During work logic level it is inconsistent and can not proper communication situation, such as chip A（In the description of this patent, work is patrolled
It is " low level chip " to collect the relatively low chip definition of level）Work-based logic level is 3.3V, and chip B（In this patent
It is " high level chip " by the of a relatively high chip definition of work-based logic level in description）Work-based logic level is 12V, now
Low level chip（Chip A）With high level chip（Chip B）Logic communication cannot be directly carried out, if making chip A and chip B straight
Data signal that None- identified other side sends or the possibility for burning out chip logic port will be had by tapping into row logic communication, in order to
Solves the unmatched problem of this kind of level, when designing digital circuit product, it is necessary to consider to carry out phase to Different Logic level
Mutually conversion, the particularly conversion of bi-directional logic level.
Existing bidirectional level conversion circuit is built based on multiple discrete components mostly, such as Chinese patent CN
Built in 1996758A using discrete components such as phase inverter+triode+diode+pull-up resistors；Chinese patent
By controlling the break-make sequential of two NPN type triodes in CN103199847A, to realize the first level signal and the second electricity
Bi-directional conversion between ordinary mail number.The problem of following all be present in these circuits：Circuit is built using a fairly large number of discrete component
（The discrete component quantity being related in whole circuit is more than 10）, circuit overall structure is more complicated, not succinct enough and monoblock
Circuit volume is larger, while such circuit structure is difficult to realize multidiameter delay I/O logic level conversion in tiny space
Build, easily occur causing because of some element failure welding further, since the element being related to is excessive, during actual production whole
The serious consequence that circuit can not work.
Utility model content
The technical problems to be solved in the utility model is to provide that a kind of component number being related to is few, simple for structure, volume
Less bidirectional level conversion circuit.
In order to solve the above-mentioned technical problem, the utility model adopts the following technical scheme that：A kind of bidirectional level conversion circuit,
Including：Amplifier U1, resistance R1, resistance R2, diode D1, the positive electricity source interface VCC for connecting positive supply, for connecting high electricity
First electric level interface VCC1_IO of the flat chip and second electrical level interface VCC2_IO for connecting low level chip, described first
Electric level interface VCC1_IO connection resistance R1, the resistance R1 connect resistance R2, second electrical level interface VCC2_IO and amplifier respectively
U1 input in the same direction, the resistance R2 connect GND and amplifier U1 reverse input end, the power positive end of the amplifier U1 respectively
Connection positive electricity source interface VCC, the amplifier U1 power supply negative terminal meet GND, the output end connection diode D1's of the amplifier U1
Positive pole, negative pole the first electric level interface of connection VCC1_IO of the diode D1, the positive electricity source interface VCC input amplifiers U1 electricity
The magnitude of voltage of source anode is equal with the work-based logic level value VCC1 of high level chip；
Wherein, VCC1*R2/(R1+R2) it is equal or approximately equal to VCC2；
In above formula, the VCC2 be low level chip work-based logic level value, the R1It is described for resistance R1 resistance
R2For resistance R2 resistance.
Further, the bidirectional level conversion circuit also includes resistance R3 and resistance R4, and the resistance R2 is connected respectively
GND and resistance 4, the resistance R4 connect amplifier U1 reverse input end and resistance R3, the resistance R3 connections positive electricity respectively again
Source interface VCC；
Wherein, 0<VCC1*R4/(R3+R4)<VCC2*(1/3)；
In above formula, the R3For resistance R3 resistance, the R4For resistance R4 resistance.
Wherein, the work-based logic level value VCC1 of the high level chip is 12V, the work-based logic of the low level chip
Level value VCC2 is 3.3V, the resistance R of the resistance R11For 5.1K Ω, the resistance R of the resistance R22For 2K Ω, the resistance
R3 resistance R3For 10K Ω, the resistance R of the R44For 1K Ω.
Operation principle of the present utility model is as described below：
When low level chip logic level VCC2 first then, it can be directly inputted through second electrical level interface VCC2_IO
Amplifier U1 input in the same direction（Because resistance R1 connects the in the same direction of resistance R2, second electrical level interface VCC2_IO and amplifier U1 respectively
Input, that is to say, that resistance R2, second electrical level interface VCC2_IO and amplifier U1 input in the same direction are connected to resistance R1
Lower end, therefore second electrical level interface VCC2_IO and amplifier U1 input in the same direction is joined directly together）, because resistance R2 is connected respectively
GND and amplifier U1 reverse input end, that is to say, that amplifier U1 reverse input end also connects GND, while amplifier U1 power supply
Negative terminal also meets GND, therefore amplifier U1 reverse input end and power supply negative terminal magnitude of voltage are 0, it is clear that amplifier U1 input in the same direction
Magnitude of voltage（For the logic level values of the low level chip inputted through second electrical level interface VCC2_IO）More than 0, i.e., amplifier U1's is same
It is more than the magnitude of voltage of reverse input end to input terminal voltage value, therefore amplifier U1 output ends export to the first electric level interface VCC1_IO
Magnitude of voltage be the magnitude of voltage for being added in its power positive end, and the work-based logic level of the magnitude of voltage of power positive end and high level chip
Value VCC1 is equal, thus achieves low level and is changed to high level so that low level chip can be led to high level chip
Letter, wherein, the diode D1 being arranged between amplifier U1 output ends and the first electric level interface VCC1_IO can prevent the first level
Interface VCC1_IO causes to damage when first supplying upper electric to amplifier U1 output ends.
When high level chip logic level VCC1 first then, the level inputs electricity through the first electric level interface VCC1_IO
Road, due to the first electric level interface VCC1_IO connection resistance R1, and resistance R1 connects resistance R2, second electrical level interface VCC2_ respectively
IO and amplifier U1 input in the same direction, that is to say, that second electrical level interface VCC2_IO connection resistance R1 lower end and amplifier U1
Input in the same direction, in addition, resistance R2 is also respectively connected with GND and amplifier U1 reverse input end, that is to say, that resistance R2 lower ends
And amplifier U1 reverse input end meets GND, i.e., the reverse input end voltage of resistance R2 lower ends and amplifier U1 is 0, now second
Electric level interface VCC2_IO magnitude of voltage is the magnitude of voltage of the input voltage value, i.e. resistance R1 lower ends of amplifier U1 inputs in the same direction.When
So it is also understood that in circuit, resistance R1 and resistance R2 series connection partial pressures, the electricity of the first electric level interface VCC1_IO inputs
Press the magnitude of voltage that the magnitude of voltage reloaded after resistance R1 partial pressures at resistance R2 both ends is second electrical level interface VCC2_IO（Cause
It is 0 for terminal voltage under resistance R2）, pass through resistance R1 and resistance R2 series connection partial pressures so that incoming level is after resistance R1 partial pressures, electricity
The magnitude of voltage of road back segment reduces, the low level for meeting low level chip operation requirement so as to realize high level to be converted into so that high
Level chip can be with low level chip communication.
In summary, bidirectional level conversion circuit provided by the utility model can realize the two-way electricity between high and low level
Flat turn is changed so that the digit chip of Different Logic level can mutual proper communication.More importantly it is that above-mentioned bidirectional level turns
Change circuit and use most commonly seen electronic component（Resistance, amplifier and diode）Build, the discrete component quantity being related to
Few, circuit structure is extremely succinct, compact, monoblock circuit small volume, suitable for realizing that multidiameter delay IO is patrolled in tiny space
Built while collecting level conversion.
Brief description of the drawings
Fig. 1 is the integrated circuit structural representation of the utility model embodiment；
Fig. 2 is to realize that 3.3V logic levels turn the computers of 12V logic levels and imitated with the bidirectional level conversion circuit in Fig. 1
True schematic diagram；
Fig. 3 is to realize that 12V logic levels turn the computers of 3.3V logic levels and imitated with the bidirectional level conversion circuit in Fig. 1
True schematic diagram.
Embodiment
For the ease of the understanding of those skilled in the art, with accompanying drawing the utility model is made with reference to specific embodiment into
The explanation of one step.
As shown in Figure 1, a kind of bidirectional level conversion circuit, including：Amplifier U1, resistance R1, resistance R2, diode D1, use
In positive electricity source interface VCC, the first electric level interface VCC1_IO for connecting high level chip of connection positive supply and for connecting
Second electrical level the interface VCC2_IO, the first electric level interface VCC1_IO connection resistance R1, the resistance R1 of low level chip
Resistance R2, second electrical level interface VCC2_IO and amplifier U1 input in the same direction are connected respectively, and the resistance R2 connects GND respectively
With amplifier U1 reverse input end, the power positive end connection positive electricity source interface VCC of the amplifier U1, the power supply of the amplifier U1 is born
GND, the output end connection diode D1 of amplifier U1 positive pole are terminated, the negative pole of the diode D1 connects the first level and connect
Mouth VCC1_IO, the magnitude of voltage of the positive electricity source interface VCC inputs amplifier U1 power positive ends and the work-based logic electricity of high level chip
Level values VCC1 is equal；
Wherein, VCC1*R2/(R1+R2) it is equal or approximately equal to VCC2；
In above formula, VCC2 be low level chip work-based logic level value, R1For resistance R1 resistance, the R2For electricity
Hinder R2 resistance.
For ease of understanding, exemplified by the bidirectional level between 12V logic levels and 3.3V logic levels is mutually changed below
To be illustrated to the operation principle of above-mentioned bidirectional level conversion circuit.
1）Upper operating voltage first is supplied to amplifier U1, is inputted by positive electricity source interface VCC to the voltage of amplifier U1 power positive ends
VCC (+)=12V, voltage VCC (-)=0V of power supply negative terminal（Ground connection）.
2）The resistance for setting resistance R1 is 5.1K Ω, and resistance R2 resistance is 2K Ω.
Make a concrete analysis of and how to change below：
A）Assuming that when 3.3V_IO logic levels arrive first, i.e., first there is 3.3V level through second electrical level interface VCC2_
IO inputs amplifier U1 inputs in the same direction, now amplifier U1 input terminal voltage V (+)=3.3V in the same direction, and now amplifier U1 is reversely inputted
Terminal voltage V（-）=0V, so V (+)>V (-), then U1 output Vout=VCC (+)=12V, that is, the first electricity
Straight cut VCC1_IO generates the output of 12V_IO logic levels, realizes 3.3V_IO logic level transitions as 12V_IO logics electricity
Flat function, emulation of the computer software is carried out to the level conversion function in this direction, specific analogous diagram is as shown in Fig. 2 by Fig. 2
As can be seen that when second electrical level interface VCC2_IO gives the input of 3.3V logic levels, emulation voltmeter measures terminal voltage on R1
It is 11.463V to the voltage difference between ground, is approximately 12V logic levels, therefore thinks that realizing 3.3V logic levels turns 12V logics
Level；
B) assume when 12V_IO logic levels arrive first, the input voltage of U1 inputs in the same direction is V (+)=R2*12V /
(R1+R2)=3.38V, approximation can regard 3.3V, i.e. 3.3V_IO logic levels as, so now completing by 12V_IO logics
Level turns the function of 3.3V_IO logic levels, emulation of the computer software figure such as Fig. 3 of the logic level transition function in this direction
It is shown.As seen from Figure 3, when the first electric level interface VCC1_IO input voltage is equal to 12V, second electrical level interface VCC2_
IO voltage directly can be drawn by resistance R1 and R2 partial pressure, now emulated voltmeter measurement and drawn second electrical level interface VCC2_
IO voltage is equal to 3.3V, so as to complete the function that 12V logic levels change into 3.3V logic levels.
In the circuit, being arranged on diode D1 between amplifier U1 output ends and the first electric level interface VCC1_IO can be with
Amplifier U1 output ends are caused to damage when preventing the first electric level interface VCC1_IO from first supplying upper electric.
The example that the bidirectional level between 12V logic levels and 3.3V logic levels is mutually changed above, this area skill
Art personnel should be understood that when the logic level difference for needing to change, and still can use the circuit structure in above-described embodiment,
As long as the resistance of corresponding adjustment resistance and the operational voltage value being added in amplifier.
In summary, the bidirectional level conversion circuit that above-described embodiment provides can realize the two-way electricity between high and low level
Flat turn is changed so that the digit chip of Different Logic level can mutual proper communication.More importantly it is that above-mentioned bidirectional level turns
Change circuit and use most commonly seen electronic component（Resistance, amplifier and diode）Build, the discrete component quantity being related to
Few, circuit structure is extremely succinct, compact, monoblock circuit small volume, suitable for realizing that multidiameter delay IO is patrolled in tiny space
Built while collecting level conversion.
Improved as further, as shown in Figure 1, above-mentioned bidirectional level conversion circuit also includes resistance R3 and resistance
R4, the resistance for setting resistance R3 is 10K Ω, and resistance R4 resistance is 1K Ω, and resistance R2 connects GND and resistance 4, resistance R4 respectively
Connect amplifier U1 reverse input end and resistance R3, resistance R3 connection positive electricity source interfaces VCC respectively again.
Due to resistance R3 and resistance R4 series connection partial pressure effect, can prevent second electrical level interface VCC2_IO without input when or
The voltage disturbance that several volts of zero point causes amplifier U1 mistake to export.Or between 12V logic levels and 3.3V logic levels
Exemplified by bidirectional level is mutually changed, in figs. 2 and 3, amplifier U1 reverse input end voltages V（-）=R4*VCC1/(R4+R3) =
1.09V 0V<1.09V<1.1V, this 1.09V magnitude of voltage separated can be prevented when second electrical level interface VCC2_IO is without input
When, amplifier U1 malfunctions produce mistake output.
Above-described embodiment is the preferable implementation of the utility model, and in addition, the utility model can be with other sides
Formula is realized, any on the premise of the technical program design is not departed from obviously to replace in protection model of the present utility model
Within enclosing.
In order to allow those of ordinary skill in the art more easily understand the utility model relative to prior art improvement it
Place, some accompanying drawings of the present utility model and description have been simplified, and for the sake of clarity, present specification is omitted one
A little other elements, those of ordinary skill in the art should be aware that these elements omitted also may make up in of the present utility model
Hold.
Claims (3)
1. bidirectional level conversion circuit, it is characterised in that including：Amplifier U1, resistance R1, resistance R2, diode D1, for connecting
The positive electricity source interface VCC of positive supply, the first electric level interface VCC1_IO for connecting high level chip and for connecting low level
The second electrical level interface VCC2_IO of chip, the first electric level interface VCC1_IO connection resistance R1, the resistance R1 connect respectively
Connecting resistance R2, second electrical level interface VCC2_IO and amplifier U1 input in the same direction, the resistance R2 connect GND and amplifier respectively
U1 reverse input end, the power positive end connection positive electricity source interface VCC of the amplifier U1, the power supply negative terminal of the amplifier U1 connect
GND, the amplifier U1 output end connection diode D1 positive pole, the negative pole of the diode D1 connect the first electric level interface
VCC1_IO, the work-based logic level of the magnitude of voltage and high level chip of the positive electricity source interface VCC inputs amplifier U1 power positive ends
Value VCC1 is equal；
Wherein, VCC1*R2/(R1+R2) it is equal or approximately equal to VCC2；
In above formula, the VCC2 be low level chip work-based logic level value, the R1For resistance R1 resistance, the R2For
Resistance R2 resistance.
2. bidirectional level conversion circuit according to claim 1, it is characterised in that：Also include resistance R3 and resistance R4, institute
State resistance R2 and connect GND and resistance 4 respectively, the resistance R4 connects amplifier U1 reverse input end and resistance R3, institute respectively again
State resistance R3 connection positive electricity source interfaces VCC；
Wherein, 0<VCC1*R4/(R3+R4)<VCC2*(1/3)；
In above formula, the R3For resistance R3 resistance, the R4For resistance R4 resistance.
3. bidirectional level conversion circuit according to claim 2, it is characterised in that：The work-based logic of the high level chip
Level value VCC1 is 12V, and the work-based logic level value VCC2 of the low level chip is 3.3V, the resistance R of the resistance R11For
5.1K Ω, the resistance R of the resistance R22For 2K Ω, the resistance R of the resistance R33For 10K Ω, the resistance R of the R44For 1K
Ω。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720594115.7U CN206759420U (en) | 2017-05-25 | 2017-05-25 | Bidirectional level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720594115.7U CN206759420U (en) | 2017-05-25 | 2017-05-25 | Bidirectional level conversion circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206759420U true CN206759420U (en) | 2017-12-15 |
Family
ID=60620323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720594115.7U Expired - Fee Related CN206759420U (en) | 2017-05-25 | 2017-05-25 | Bidirectional level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206759420U (en) |
-
2017
- 2017-05-25 CN CN201720594115.7U patent/CN206759420U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20171215 Termination date: 20200525 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |