CN206757612U - A kind of multipath server interacted system - Google Patents

A kind of multipath server interacted system Download PDF

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Publication number
CN206757612U
CN206757612U CN201720501286.0U CN201720501286U CN206757612U CN 206757612 U CN206757612 U CN 206757612U CN 201720501286 U CN201720501286 U CN 201720501286U CN 206757612 U CN206757612 U CN 206757612U
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China
Prior art keywords
processor
interface
backplane
plate
veneer
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Expired - Fee Related
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CN201720501286.0U
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Chinese (zh)
Inventor
王素华
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Zhengzhou Yunhai Information Technology Co Ltd
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Zhengzhou Yunhai Information Technology Co Ltd
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Priority to CN201720501286.0U priority Critical patent/CN206757612U/en
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Abstract

The utility model provides a kind of multipath server interacted system, including：First veneer, the second veneer, front panel, backboard；First veneer is provided with first processor, second processor, the 3rd processor, fourth processor, and first processor interface, second processor interface, the 3rd processor interface, fourth processor interface；First processor interface is connected with plate interface before first, and second processor interface is connected with plate interface before second, and the 5th processor interface is connected with plate interface before the 3rd, and the 6th processor interface is connected with plate interface before the 4th；3rd processor interface is connected with the first backplane interface, and fourth processor interface is connected with the second backplane interface, and the 7th processor interface is connected with the 3rd backplane interface, and eight processor interface is connected with the 4th backplane interface.By wiring mutual contact mode of the present utility model, bus bar mode is optimized, data transmission quality is improved between multipath server.

Description

A kind of multipath server interacted system
Technical field
The present invention relates to server field, more particularly to a kind of multipath server interacted system.
Background technology
With the raising of signal rate, signal integrity position shared in signal effectively transmits is more and more important.Shadow The reason for ringing signal integrity is a lot, although engineer optimizes in design on board level as far as possible, and evades all signal integrities Unfavorable factor.But because interconnection architecture transmission is long on topological structure, so big loss can not be undertaken by also resulting in chip, Reach or even exceed design limit, so cause framework not realize, optimize bus signals integrality.
The content of the invention
In order to overcome above-mentioned deficiency of the prior art, the present invention provides a kind of multipath server interacted system, including：The One veneer, the second veneer, front panel, backboard；First veneer is provided with first processor, second processor, the 3rd processor, and the 4th Processor, and first processor interface, second processor interface, the 3rd processor interface, fourth processor interface；
Second veneer is provided with the 5th processor, the 6th processor, the 7th processor, eight processor, and the 5th processing Device interface, the 6th processor interface, the 7th processor interface, eight processor interface；
First processor, second processor, the 3rd processor, fourth processor are connected with each other, the 5th processor, at the 6th Device, the 7th processor are managed, eight processor is connected with each other；First processor, second processor, the 3rd processor, fourth process Device corresponds to respectively to be connected with first processor interface, second processor interface, the 3rd processor interface, fourth processor interface, 5th processor, the 6th processor, the 7th processor, eight processor correspond to and the 5th processor interface, the 6th processing respectively Device interface, the 7th processor interface, the connection of eight processor interface；
Plate interface before front panel is provided with first, plate interface before second, plate interface before the 3rd, plate interface before the 4th, backboard are set There are the first backplane interface, the second backplane interface, the 3rd backplane interface, the 4th backplane interface；
First processor interface is connected with plate interface before first, and second processor interface is connected with plate interface before second, the Five processor interfaces are connected with plate interface before the 3rd, and the 6th processor interface is connected with plate interface before the 4th；
3rd processor interface is connected with the first backplane interface, and fourth processor interface is connected with the second backplane interface, the Seven processor interfaces are connected with the 3rd backplane interface, and eight processor interface is connected with the 4th backplane interface.
Preferably, first processor is connected with first processor interface, and second processor is connected with second processor interface, 3rd processor is connected with the 3rd processor interface, and fourth processor is connected with fourth processor interface, the 5th processor and Five processor interfaces are connected, and the 6th processor is connected with the 6th processor interface, and the 7th processor and the 7th processor interface connect Connect, eight processor is connected with eight processor interface.
Preferably, first processor passes sequentially through first processor interface, plate interface before first, plate interface before the 4th, and Six processor interfaces are connected with the 6th processor.
Preferably, second processor passes sequentially through second processor interface, plate interface before second, plate interface before the 3rd, and Five processor interfaces are connected with the 5th processor.
Preferably, the 3rd processor passes sequentially through the 3rd processor interface, the first backplane interface, the 3rd backplane interface, and Seven processor interfaces are connected with the 7th processor.
Preferably, fourth processor passes sequentially through fourth processor interface, the second backplane interface, the 4th backplane interface, and Eight processor interface is connected with eight processor.
Preferably, connected on the first veneer and the second veneer between processor using QPI buses, processor connects with processor Connected between mouthful using QPI buses, the first veneer, the second veneer, front panel, the connection between backboard is connected using QPI buses Connect.
Preferably, first processor interface, second processor interface, the 3rd processor interface, fourth processor interface, the Five processor interfaces, the 6th processor interface, the 7th processor interface, eight processor interface use QPI EBIs；
Plate interface before first, plate interface before second, plate interface before the 3rd, plate interface before the 4th, the first backplane interface, second Backplane interface, the 3rd backplane interface, the 4th backplane interface use QPI bus buckle interfaces.
Preferably, first processor is connected with second processor, and second processor is connected with fourth processor, fourth process Device is connected with the 3rd processor, and the 3rd processor is connected with first processor.
Preferably, the 5th processor is connected with the 6th processor, and the 6th processor is connected with eight processor, the 8th processing Device is connected with the 7th processor, and the 7th processor is connected with the 5th processor.
As can be seen from the above technical solutions, the present invention has advantages below：
Multipath server interacted system includes：First veneer, the second veneer, front panel, backboard；First veneer is provided with first Processor, second processor, the 3rd processor, fourth processor, and first processor interface, second processor interface, the Three processor interfaces, fourth processor interface；By wiring mutual contact mode of the present utility model, bus bar mode is optimized, Data transmission quality is improved between multipath server, and it is long to avoid on topological structure interconnection architecture transmission, causes to locate It is excessive to manage device loss.
Brief description of the drawings
In order to illustrate more clearly of technical scheme, the required accompanying drawing used in description will be made below simple Ground introduction, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for ordinary skill For personnel, on the premise of not paying creative work, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is the link topology of multipath server interacted system；
Fig. 2 is the first veneer schematic diagram；
Fig. 3 is the second veneer schematic diagram；
Fig. 4 is front panel schematic diagram；
Fig. 5 is backboard schematic diagram.
Embodiment
To enable goal of the invention, feature, the advantage of the present invention more obvious and understandable, will use below specific Embodiment and accompanying drawing, the technical scheme protected to the present invention are clearly and completely described, it is clear that implementation disclosed below Example is only part of the embodiment of the present invention, and not all embodiment.Based on the embodiment in this patent, the common skill in this area All other embodiment that art personnel are obtained under the premise of creative work is not made, belong to the model of this patent protection Enclose.
The present embodiment provides a kind of multipath server interacted system, as shown in Fig. 1 to 5, including：First veneer 10, second Veneer 20, front panel 26, backboard 36；First veneer 10 is provided with first processor 1, second processor 2, the 3rd processor 3, and the 4th Processor 4, and first processor interface 11, second processor interface 12, the 3rd processor interface 13, fourth processor interface 14；Second veneer 20 is provided with the 5th processor 5, the 6th processor 6, the 7th processor 7, eight processor 8, and the 5th processing Device interface 15, the 6th processor interface 16, the 7th processor interface 17, eight processor interface 18；
First processor 1, second processor 2, the 3rd processor 3, fourth processor 4 are connected with each other, the 5th processor 5, 6th processor 6, the 7th processor 7, eight processor 8 are connected with each other；First processor 1, second processor 2, the 3rd processing Device 3, fourth processor 4 corresponds to respectively and first processor interface 11, second processor interface 12, the 3rd processor interface 13, Fourth processor interface 14 connects, the 5th processor 5, the 6th processor 6, the 7th processor 7, and eight processor 8 corresponds to respectively Connected with the 5th processor interface 15, the 6th processor interface 16, the 7th processor interface 17, eight processor interface 18；
Plate interface 21 before front panel 26 is provided with first, plate interface 22 before second, plate interface 23 before the 3rd, plate interface before the 4th 24, backboard 36 is provided with the first backplane interface 31, the second backplane interface 32, the 3rd backplane interface 33, the 4th backplane interface 34；First Processor interface 11 is connected with plate interface before first 21, and second processor interface 12 is connected with plate interface before second 22, at the 5th Reason device interface 15 is connected with plate interface 23 before the 3rd, and the 6th processor interface 16 is connected with plate interface 24 before the 4th；3rd processing Device interface 23 is connected with the first backplane interface 31, and fourth processor interface 24 is connected with the second backplane interface 32, the 7th processor Interface 17 is connected with the 3rd backplane interface 33, and eight processor interface 18 is connected with the 4th backplane interface 34.
First processor 1 is connected with first processor interface 11, and second processor 2 is connected with second processor interface 12, 3rd processor 3 is connected with the 3rd processor interface 13, and fourth processor 4 is connected with fourth processor interface 14, the 5th processing Device 5 is connected with the 5th processor interface 15, and the 6th processor 6 is connected with the 6th processor interface 16, the 7th processor 7 and the 7th Processor interface 17 is connected, and eight processor 8 is connected with eight processor interface 18.
First processor 1 passes sequentially through first processor interface 11, plate interface 21 before first, plate interface 24 before the 4th, and Six processor interfaces 16 are connected with the 6th processor 6.Second processor 2 passes sequentially through second processor interface 12, the second foreboard Interface 22, plate interface 23 before the 3rd, the 5th processor interface 15 are connected with the 5th processor 5.3rd processor 3 passes sequentially through Three processor interfaces 13, the first backplane interface 31, the 3rd backplane interface 33, the 7th processor interface 17 connect with the 7th processor 7 Connect.Fourth processor 4 passes sequentially through fourth processor interface 14, the second backplane interface 32, the 4th backplane interface 34, the 8th processing Device interface 18 is connected with eight processor 8.So optimize the topological structure interconnected between processor.It is long to avoid cabling, Beyond the driving force of processor.
Connected on first veneer 10 and the second veneer 20 between processor using QPI buses, processor and processor interface Between connected using QPI buses, the first veneer 10, the second veneer 20, front panel 26, the connection between backboard 36 uses QPI Bus connects.
First processor interface 11, second processor interface 12, the 3rd processor interface 13, fourth processor interface 14, 5th processor interface 15, the 6th processor interface 16, the 7th processor interface 17, eight processor interface 18 use QPI EBI；
Plate interface 21 before first, plate interface 22 before second, plate interface 23 before the 3rd, plate interface 24 before the 4th, the first backboard Interface 31, the second backplane interface 32, the 3rd backplane interface 33, the 4th backplane interface 34 use QPI bus buckle interfaces.
First processor 1 is connected with second processor 2, and second processor 2 is connected with fourth processor 4, fourth processor 4 It is connected with the 3rd processor 3, the 3rd processor 3 is connected with first processor 1.
5th processor 5 is connected with the 6th processor 6, and the 6th processor 6 is connected with eight processor 8, eight processor 8 It is connected with the 7th processor 7, the 7th processor 7 is connected with the 5th processor 5.
Term " first ", " second ", " the 3rd " " in description and claims of this specification and above-mentioned accompanying drawing Four " etc.（If there is）It is for distinguishing similar object, without for describing specific order or precedence.It should manage The data that solution so uses can exchange in the appropriate case, so as to embodiments of the invention described herein can with except Here the order beyond those for illustrating or describing is implemented.In addition, term " comprising " and " having " and their any deformation, It is intended to cover non-exclusive include.

Claims (10)

  1. A kind of 1. multipath server interacted system, it is characterised in that including：First veneer, the second veneer, front panel, backboard；The One veneer is provided with first processor, second processor, the 3rd processor, fourth processor, and first processor interface, and second Processor interface, the 3rd processor interface, fourth processor interface；
    Second veneer is provided with the 5th processor, the 6th processor, the 7th processor, eight processor, and the 5th processor and connect Mouthful, the 6th processor interface, the 7th processor interface, eight processor interface；
    First processor, second processor, the 3rd processor, fourth processor are connected with each other, the 5th processor, the 6th processing Device, the 7th processor, eight processor are connected with each other；First processor, second processor, the 3rd processor, fourth processor Correspond to and connected with first processor interface, second processor interface, the 3rd processor interface, fourth processor interface respectively, the Five processors, the 6th processor, the 7th processor, eight processor correspond to and the 5th processor interface, the 6th processor respectively Interface, the 7th processor interface, the connection of eight processor interface；
    Plate interface before front panel is provided with first, plate interface before second, plate interface before the 3rd, plate interface before the 4th, backboard are provided with the One backplane interface, the second backplane interface, the 3rd backplane interface, the 4th backplane interface；
    First processor interface is connected with plate interface before first, and second processor interface is connected with plate interface before second, at the 5th Reason device interface is connected with plate interface before the 3rd, and the 6th processor interface is connected with plate interface before the 4th；
    3rd processor interface is connected with the first backplane interface, and fourth processor interface is connected with the second backplane interface, at the 7th Reason device interface is connected with the 3rd backplane interface, and eight processor interface is connected with the 4th backplane interface.
  2. 2. multipath server interacted system according to claim 1, it is characterised in that
    First processor is connected with first processor interface, and second processor is connected with second processor interface, the 3rd processor It is connected with the 3rd processor interface, fourth processor is connected with fourth processor interface, and the 5th processor connects with the 5th processor Mouth connection, the 6th processor are connected with the 6th processor interface, and the 7th processor is connected with the 7th processor interface, the 8th processing Device is connected with eight processor interface.
  3. 3. multipath server interacted system according to claim 1, it is characterised in that
    First processor passes sequentially through first processor interface, plate interface before first, plate interface before the 4th, the 6th processor interface It is connected with the 6th processor.
  4. 4. multipath server interacted system according to claim 1, it is characterised in that
    Second processor passes sequentially through second processor interface, plate interface before second, plate interface before the 3rd, the 5th processor interface It is connected with the 5th processor.
  5. 5. multipath server interacted system according to claim 1, it is characterised in that
    3rd processor passes sequentially through the 3rd processor interface, the first backplane interface, the 3rd backplane interface, the 7th processor interface It is connected with the 7th processor.
  6. 6. multipath server interacted system according to claim 1, it is characterised in that
    Fourth processor passes sequentially through fourth processor interface, the second backplane interface, the 4th backplane interface, eight processor interface It is connected with eight processor.
  7. 7. according to the multipath server interacted system described in claim 1 or 2 or 3 or 4 or 5 or 6, it is characterised in that
    Connected using QPI buses between processor on first veneer and the second veneer, used between processor and processor interface QPI buses are connected, the first veneer, the second veneer, front panel, and the connection between backboard is connected using QPI buses.
  8. 8. multipath server interacted system according to claim 7, it is characterised in that
    First processor interface, second processor interface, the 3rd processor interface, fourth processor interface, the 5th processor connect Mouth, the 6th processor interface, the 7th processor interface, eight processor interface use QPI EBIs；
    Plate interface before first, plate interface before second, plate interface before the 3rd, plate interface before the 4th, the first backplane interface, the second backboard Interface, the 3rd backplane interface, the 4th backplane interface use QPI bus buckle interfaces.
  9. 9. multipath server interacted system according to claim 1, it is characterised in that
    First processor is connected with second processor, and second processor is connected with fourth processor, at fourth processor and the 3rd Device connection is managed, the 3rd processor is connected with first processor.
  10. 10. multipath server interacted system according to claim 1, it is characterised in that
    5th processor is connected with the 6th processor, and the 6th processor is connected with eight processor, at eight processor and the 7th Device connection is managed, the 7th processor is connected with the 5th processor.
CN201720501286.0U 2017-05-08 2017-05-08 A kind of multipath server interacted system Expired - Fee Related CN206757612U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201720501286.0U CN206757612U (en) 2017-05-08 2017-05-08 A kind of multipath server interacted system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201720501286.0U CN206757612U (en) 2017-05-08 2017-05-08 A kind of multipath server interacted system

Publications (1)

Publication Number Publication Date
CN206757612U true CN206757612U (en) 2017-12-15

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201720501286.0U Expired - Fee Related CN206757612U (en) 2017-05-08 2017-05-08 A kind of multipath server interacted system

Country Status (1)

Country Link
CN (1) CN206757612U (en)

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CF01 Termination of patent right due to non-payment of annual fee
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Granted publication date: 20171215

Termination date: 20180508