CN206757345U - A kind of industry screen display control circuit - Google Patents
A kind of industry screen display control circuit Download PDFInfo
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- CN206757345U CN206757345U CN201720419117.2U CN201720419117U CN206757345U CN 206757345 U CN206757345 U CN 206757345U CN 201720419117 U CN201720419117 U CN 201720419117U CN 206757345 U CN206757345 U CN 206757345U
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Abstract
A kind of industry screen display control circuit is the utility model is related to, it includes：LDO power converting circuits, the fpga chips of GW1NR 4, download circuit, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit and reset circuit；The LDO power converting circuits, download circuit, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit connect with reset circuit with the fpga chips of GW1NR 4.This programme is the industry screen display control circuit for the fpga chips of GW1NR 4 that SDRAM is embedded based on high cloud semiconductor, and the fpga chips of GW1NR 4 have it is non-volatile, without plug-in Flash storages code, be embedded with Large Copacity SDRAM, the features such as high integration, high-performance；Using QFN88 compact package forms so that circuit is compacter, succinct, efficient.
Description
Technical field
Technical field of circuit design is the utility model is related to, more particularly, to a kind of industry screen display control circuit.
Background technology
Industry screen is derived from industrial serial ports screen, is rapidly developed after 2010 and extensive use, data transmission interface is not
Only with UART/SPI, various new interfaces are more and more, and the interface of screen also begins to the interface using LVDS, MIPI etc, extensively
It is general to be applied to industrial automation, electric power, telecommunications, environmental protection, medical treatment, finance, oil, chemical industry, traffic, the energy, geology, metallurgy, public affairs
Dozens of industry and the field such as inquiry and monitoring altogether.
Industry at present shields display control circuit mainly by the way of the plug-in SDRAM of FPGA, due to plug-in SDRAM memory
Need to take substantial amounts of I/O resources, fpga chip package dimension requires to become big, adds circuit complexity and cost of manufacture.
Utility model content
The utility model is to overcome at least one defect (deficiency) described in above-mentioned prior art, there is provided a kind of industrial screen display
Show control circuit.
The utility model is intended at least solve above-mentioned technical problem to a certain extent.
In order to reach above-mentioned technique effect, the technical solution of the utility model is as follows：
A kind of industry screen display control circuit, including：LDO power converting circuits, GW1NR-4 fpga chips, download electricity
Road, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit and reset circuit；The LDO power converting circuits, download electricity
Road, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit connect with reset circuit with GW1NR-4 fpga chips.
Preferably, the LDO power converting circuits include：First LDO linear transformations power supply chip and the 2nd LDO linearly become
Change power supply chip.
Preferably, the GW1NR-4 fpga chips include：Clock module, MCU interface modules, sdram controller, data
Read-write Catrol module, back read data cache module, display data cache module and driver module.
Preferably, the MCU interface circuit includes：33 ohm of exclusions and 26PIN dual-in-lines row's pin.
Preferably, the industry screen interface circuit includes：33 ohm of exclusions and 50PIN FPC connectors.
Preferably, the crystal oscillating circuit includes：50MHz crystal oscillator chips, the first electric capacity and first resistor.
Preferably, the reset circuit includes：Touch-switch, reset chip, second resistance and the second electric capacity.
Compared with prior art, the beneficial effect of technical solutions of the utility model is：
This programme is the industry screen display control electricity for the GW1NR-4 fpga chips that SDRAM is embedded based on high cloud semiconductor
Road, and GW1NR-4 fpga chips have it is non-volatile, without plug-in Flash storages code, be embedded with Large Copacity SDRAM, it is high
The features such as integrated level, high-performance；Using QFN88 compact package forms so that circuit is compacter, succinct, efficient.
Brief description of the drawings
Fig. 1 is the industry screen display control circuit schematic diagram of an embodiment；
Fig. 2 is the schematic diagram of the GW1NR-4 fpga chips of Fig. 1 industry screen display control circuits.
Embodiment
Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；
In order to more preferably illustrate the present embodiment, some parts of accompanying drawing have omission, zoomed in or out, and do not represent actual product
Size；
To those skilled in the art, it is to be appreciated that some known features and its explanation, which may be omitted, in accompanying drawing
's.
The technical solution of the utility model is described further with reference to the accompanying drawings and examples.
A kind of industry screen display control circuit, including：LDO power converting circuits 2, GW1NR-4 fpga chips 1, download electricity
Road 3, MCU interface circuit 4, industry screen interface circuit 5, crystal oscillating circuit 6 and reset circuit 7；The LDO power converting circuits 2, under
Carry circuit 3, MCU interface circuit 4, industry screen interface circuit 5, crystal oscillating circuit 6 and reset circuit 7 and GW1NR-4 fpga chips
1 connection.
As a preferred embodiment, the LDO power converting circuits 2 include：First LDO linear transformations power supply chip and
Two LDO linear transformation power supply chips.First LDO linear transformations power supply chip and the 2nd LDO linear transformation power supply chips, there is pole
Low power supply noise, good power supply signal is provided for circuit board.Wherein, the first LDO linear transformation power supply chips realize DC5P0
Converted to DC3P3, the 2nd LDO linear transformation power supply chips realize that DC3P3 to DC1P2 is converted；Or the 2nd LDO linear transformations electricity
Source chip realizes that DC5P0 to DC3P3 is converted, and the first LDO linear transformation power supply chips realize that DC3P3 to DC1P2 is converted.It is described
LDO power converting circuits 2 also include：TPS74801RGWR chips, filter capacitor, build-out resistor and magnetic bead, pass through build-out resistor
DC3P3 and DC1P2 voltages are produced respectively, and power supply is provided for FPGA and other IC chips.By placing necessary electric capacity and magnetic bead
Effectively power supply is filtered, in order to reduce interference of the power circuit part to other circuits, power supply chip region is spread
Ground, and ensure its good connectivity with stratum.
As a preferred embodiment, as shown in Fig. 2 the GW1NR-4 fpga chips 1 include：Clock module 11, MCU connect
Mouth mold block 12, sdram controller 13, data read-write control module 14, back read data cache module 15, display data cache module
16 and driver module 17.Clock module 11：It is responsible for producing work clock needed for internal each module.MCU interface modules 12：It is complete
Into with the SECO of MCU interfaces and reading and writing data, realize MCU interface protocols parsing, SDRAM data write-in and read control.
Data read-write control module 14：Realize the view data write-in between MCU interface modules 12 and read；According to display module timing
Refresh requirements, a line view data is regularly read from SDRAM memory.Back read data cache module 15：MCU as needed can
The retaking of a year or grade view data from SDRAM cachings, the caching are used for the interim storage of retaking of a year or grade view data.Display data cache module
16：Display is shielded according to industry and requires that a line view data, deposit display data cache module 16 are read in timing.Driver module
17：Produce industry screen interface sequence and read view data from display data cache module 16.Fpga chip is mainly realized and MCU
Between bus data communication, realize industry screen display control, the processing of MCU interface protocols, carry out view data write-in and reading
SDRAM。
As a preferred embodiment, the MCU interface circuit 4 includes：33 ohm of exclusions and 26PIN dual-in-lines row's pin.
The interface mainly completes the data interaction between MCU, including image read-write data, busy-idle condition, cls control, foreground are set
Put, background colour is set.Wherein interface signal includes D15~D0 data, CS pieces select, WR writes enabled, RD and reads enabled, A2~A1 controls
System, MLED back read datas prepare instruction and 5V power supplys.
In the present embodiment, JTAG download interfaces, pin is arranged by biserial and upper pull down resistor forms, jtag interface circuit is mainly real
Existing PC programs to FPGA SRAM programmings and internal Flash.
As a preferred embodiment, the industry screen interface circuit 5 includes：33 ohm of exclusions and 50PIN FPC connectors,
Realize that the signal between display screen connects, and power supply is provided to display screen.Interface signal include R7~R0, G7~G0, B7~B0,
MODE, DE, HS, VS, DLCK, U/D, R/L and AVDD, VCOM, VLED+, VLED-, VGH, VGL power supply.
As a preferred embodiment, the crystal oscillating circuit 6 includes：50MHz crystal oscillator chips, the first electric capacity and first resistor,
Clock signal is provided for fpga chip.The clock frequency of crystal oscillating circuit 6 is 50MHz, and the 3rd pin of crystal oscillator chip is connected to FPGA's
Pll clock dedicated pin, clock source is provided for FPGA internal logics.Clock cabling will be avoided by other signals during PCB layout
Interference.
As a preferred embodiment, the reset circuit 7 includes：Touch-switch, reset chip, second resistance and the second electricity
Hold, reset signal is provided for fpga chip.
This programme is the industry screen display control electricity for the GW1NR-4 fpga chips 1 that SDRAM is embedded based on high cloud semiconductor
Road, and GW1NR-4 fpga chips 1 have it is non-volatile, without plug-in Flash storage code, be embedded with Large Copacity SDRAM, have
There is the features such as high integration, high-performance；Using QFN88 compact package forms so that circuit is compacter, succinct, efficient.
Same or analogous label corresponds to same or analogous part；
Position relationship is used for being given for example only property explanation described in accompanying drawing, it is impossible to is interpreted as the limitation to this patent；
Obviously, above-described embodiment of the present utility model is only intended to clearly illustrate the utility model example, and
It is not the restriction to embodiment of the present utility model.For those of ordinary skill in the field, in described above
On the basis of can also make other changes in different forms.There is no need and unable to give all embodiments
It is exhaustive.All made within spirit of the present utility model and principle all any modification, equivalent and improvement etc., should be included in
Within the protection domain of the utility model claims.
Claims (7)
- A kind of 1. industry screen display control circuit, it is characterised in that including：LDO power converting circuits, GW1NR-4FPGA chips, Download circuit, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit and reset circuit；The LDO power converting circuits, download circuit, MCU interface circuit, industry screen interface circuit, crystal oscillating circuit and reset electricity Road connects with GW1NR-4FPGA chips.
- 2. industry screen display control circuit according to claim 1, it is characterised in that the LDO power converting circuits bag Include：First LDO linear transformations power supply chip and the 2nd LDO linear transformation power supply chips.
- 3. industry screen display control circuit according to claim 1, it is characterised in that the GW1NR-4FPGA chips bag Include：Clock module, MCU interface modules, sdram controller, data read-write control module, back read data cache module, display number According to cache module and driver module.
- 4. industry screen display control circuit according to claim 1, it is characterised in that the MCU interface circuit includes：33 Ohm exclusion and 26PIN dual-in-lines row's pin.
- 5. industry screen display control circuit according to claim 1, it is characterised in that the industry screen interface circuit bag Include：33 ohm of exclusions and 50PIN FPC connectors.
- 6. industry screen display control circuit according to claim 1, it is characterised in that the crystal oscillating circuit includes：50MHz Crystal oscillator chip, the first electric capacity and first resistor.
- 7. industry screen display control circuit according to claim 1, it is characterised in that the reset circuit includes：Touch Switch, reset chip, second resistance and the second electric capacity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720419117.2U CN206757345U (en) | 2017-04-20 | 2017-04-20 | A kind of industry screen display control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720419117.2U CN206757345U (en) | 2017-04-20 | 2017-04-20 | A kind of industry screen display control circuit |
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| Publication Number | Publication Date |
|---|---|
| CN206757345U true CN206757345U (en) | 2017-12-15 |
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ID=60614408
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720419117.2U Active CN206757345U (en) | 2017-04-20 | 2017-04-20 | A kind of industry screen display control circuit |
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| Country | Link |
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| CN (1) | CN206757345U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114005406A (en) * | 2021-10-28 | 2022-02-01 | 西安微电子技术研究所 | OLED display circuit |
-
2017
- 2017-04-20 CN CN201720419117.2U patent/CN206757345U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114005406A (en) * | 2021-10-28 | 2022-02-01 | 西安微电子技术研究所 | OLED display circuit |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP02 | Change in the address of a patent holder |
Address after: 510000 room 1001, science Avenue, Whampoa District, Guangzhou, Guangdong, 1001 Patentee after: Guangdong high cloud semiconductor technologies limited company Address before: 528303 No. 16, Rong Qi Avenue, Shunde District, Foshan, Guangdong. Patentee before: Guangdong high cloud semiconductor technologies limited company |
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| CP02 | Change in the address of a patent holder |