CN206711902U

CN206711902U - Table top PIN side passivation structure

Info

Publication number: CN206711902U
Application number: CN201720420864.8U
Authority: CN
Inventors: 刘志锋; 唐琦; 许海明
Original assignee: Wuhan Guanganlun Optoelectronic Technology Co Ltd
Current assignee: Hubei guanganlun chip Co.,Ltd.
Priority date: 2017-04-21
Filing date: 2017-04-21
Publication date: 2017-12-05
Anticipated expiration: 2027-04-21

Abstract

The utility model provides a kind of table top PIN side passivation structure, including semi-insulating InP substrate and the cushion grown successively on semi-insulating InP substrate, N++ type layer of InP, InGaAs absorbed layers, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers, the cushion grown successively above the semi-insulating InP substrate, N++ type layer of InP, InGaAs absorbed layers, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers constitutes flight table top, growth has eigen I nP layers in the side wall of the flight table top, growth has SIO2 layers and SINx layers successively on the eigen I nP layers.The utility model provides to have used and mesa sides is buried with chip material identical eigen I nP, the problems such as dark current is uncontrollable, high temperature reliability is poor is overcome while chip photoelectric performance is met, the preparation technology to the high speed reception chip of mesa type provides a kind of new method.

Description

Table top PIN side passivation structure

Technical field

It the utility model is related to technical field of optical fiber communication, more particularly to a kind of table top PIN side passivation structure.

Background technology

Existing table top PIN side passivation technology be mainly perforate diffusion technique, somatomedin film, coating it is organic thin Film and ion implanting passive surface mode.

Can be in P++ and i-InP contact surface just as the plane PIN of routine using " quasi- table top " technique that perforate is spread Larger parasitic capacitance is formed, does not possess preferable bandwidth effect, the processing chip is usually applied in quasi high-speed system.

Somatomedin film mainly grows SIO2/SINx films including PECVD modes, and technique is simple, and shortcoming is SIO2/ SINx non crystalline structure is difficult to carry out Lattice Matching, and the growth technique under plasmoid with mesa material InP/InGaAs Mesa material oxidation is easily caused, further deteriorates the Id performances of chip.

The material for coating organic film is mainly BCB, and the material has the dielectric constant of very little, can obtain good electricity Hold effect, but because BCB heat conductivility is poor, so as to cause the high temperature Id characteristics of chip poor, and ESD threshold values are very Small, chip anti-electric impact capacity is very poor, causes that the performance reliably and with long-term of chip is poor, and failure risk is larger in use. Other BCB preparation and storage are cumbersome, and process repeatability is not high, cause complex process, and yield rate is low.

Ion implanting mainly forms high resistance area by way of injecting H+, O+, He+, and the major defect of the program is to use In ion implanting equipment costly, and inject depth and injection after the more difficult removal of lattice damage, under electric field action Easily form dark current source.

Utility model content

The purpose of this utility model is to provide a kind of table top PIN side passivation structure, it is intended to existing for solving There is poor parasitic capacitance, chip performance, complex process in table top PIN side passivation structure, yield rate is low, dark current is uncontrollable Problem.

What the utility model was realized in：

The utility model provides a kind of table top PIN side passivation structure, including semi-insulating InP substrate and semi-insulating The cushion that is grown successively above InP substrate, N++ types layer of InP, InGaAs absorbed layers, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers, the cushion grown successively above the semi-insulating InP substrate, N++ types layer of InP, InGaAs absorb Layer, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers constitute flight table top, the flight table top Growth has eigen I nP layers in side wall, and being grown successively on the eigen I nP layers has SIO2 layers and SINx layers.

Further, the thickness of the eigen I nP layers is 0.4-1um.

Further, the flight table top is two-stage ladder mesa structure, wherein InGaAs absorbed layers, InGaAsP mistakes Cross layer, P++ types InP CAP layers and InGaAs contact layers and constitute first order ladder table top, cushion is formed with N++ types layer of InP Second level ladder table top.

Further, the flight table top is the trapezoidal table top of positive exponent.

Further, the eigen I nP layers cover the flight table top whole sidewall areas.

Compared with prior art, the utility model has the advantages that：

This table top PIN provided by the utility model side passivation structure, has been used and chip material identical is intrinsic The passivation scheme that InP is buried to mesa sides, PECVD modes are overcome while chip photoelectric performance is met SIO2 side passivations and the dark current caused by photosensitive Benzocyclobutene (BCB) side passivation are uncontrollable, high temperature is reliable The problems such as property difference, the preparation technology to the high speed reception chip of mesa type provides a kind of new method.

Brief description of the drawings

Fig. 1 is the schematic cross-section for the table top PIN epitaxial slice structures that the utility model embodiment provides；

Fig. 2 is the chip cross-section pattern schematic diagram after the completion of the one-level table top that the utility model embodiment provides；

Fig. 3 is the chip cross-section pattern schematic diagram after the completion of the two level table top that the utility model embodiment provides

Fig. 4 is chip cross-section pattern schematic diagram after the completion of the eigen I nP that the utility model embodiment provides is buried；

Fig. 5 is chip cross-section pattern schematic diagram after the RIE techniques SIO2 etchings that the utility model embodiment provides；

Fig. 6 is chip cross-section pattern schematic diagram after the completion of the metal electrode that the utility model embodiment provides；

Fig. 7 is chip surface morphology schematic diagram after the completion of the metal electrode that the utility model embodiment provides；

Fig. 8 is the chip dark current test chart that the utility model embodiment provides.

Embodiment

Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the embodiment of the utility model is carried out Clearly and completely describing, it is clear that described embodiment is only the utility model part of the embodiment, rather than whole Embodiment.Based on the embodiment in the utility model, those of ordinary skill in the art are not under the premise of creative work is made The all other embodiment obtained, belong to the scope of the utility model protection.

As shown in figure 1, the utility model embodiment provides a kind of table top PIN side passivation structure, including semi-insulating InP Substrate 1 and the cushion 2 grown successively on semi-insulating InP substrate 1, N++ types layer of InP 3, InGaAs absorbed layers 4, The CAP layers 6 and InGaAs contact layers 7 of InGaAsP transition zones 5, P++ types InP, what the semi-insulating InP substrate 1 grew successively above Cushion 2, N++ types layer of InP 3, InGaAs absorbed layers 4, InGaAsP transition zones 5, P++ types InP CAP layers 6 and InGaAs contacts Layer 7 constitutes flight table top, and being grown in the side wall of the flight table top has eigen I nP layers 8, on the eigen I nP layers 8 successively Growth has SIO2 layers and SINx layers, and being made respectively on the flight table top has N electrode 9 and P electrode 9.Wherein：It is semi-insulating InP substrate 1 is High resistivity substrate, and purpose of design is to reduce caused ghost effect between chip operation process chips and base； The purpose of design of cushion 2 is preferably matches between semi-insulating InP substrate 1 and N++ types layer of InP 3 because doping concentration and doping The difference of lattice constant caused by the difference of species, to ensure the growth quality of crucial epitaxial layer；N++ types layer of InP 3 connects for electricity Contact layer（Reverse-biased is high potential access port）, it is general to use to make to form resistance as small as possible between metal level and off-chip circuitry Weight S is adulterated and is needed the high-temperature process in later stage to form Ohmic contact；InGaAs absorbed layers 4 are photoelectric conversion layer, purpose of design To absorb the photon energy between 1.1um-1.6um as far as possible；InGaAsP transition zones 5 are what two energy gaps differed greatly Transition zone between InP and InGaAs, its energy gap were being migrated between both materials with reducing photo-generated carrier Accumulation in journey, improve respective rate；P++ types InP CAP floor 6 is PIN P areas, general to be adulterated using weight Zn to be easier Ohmic contact is formed, while InP energy gap is 1.35ev under normal temperature condition, can effectively filter and be inhaled into InGaAs The light wave of layer 4 is received, improves the optical responsivity Re of device；InGaAs contact layers 7 are also electric contacting layer, using weight Zn doping As electrical contact ring Ohmic contact is more readily formed than InP, so as to obtain smaller contact resistance in InGaAs.

Preferably, the flight table top is the trapezoidal table top of positive exponent.The flight table top is two-stage ladder table top Structure, wherein InGaAs absorbed layers 4, InGaAsP transition zones 5, P++ types InP CAP layers 6 and InGaAs contact layers 7 constitute Step table top, cushion 2 constitute second level ladder table top with N++ types layer of InP 3.The eigen I nP layers 8 cover the rank Terraced layer table top whole sidewall areas.The thickness of the eigen I nP layers 8 is 0.4-1um.

As shown in Fig. 2 in one-level table top manufacturing process, using inductive couple plasma（ICP）Etch to complete, etch The preceding structure that step cutting pattern is transferred to Fig. 1 by pattern transfer, using Br+HBr+H2O according to certain after the completion of etching Proportioning carries out wet etching, and the purpose of wet etching is carried out after dry etching in removing in ICP etching processes to chip material Physical damnification layer caused by expecting surface, because during chip operation, side is the dangling bonds of physical damnification layer, boundary defect Very big dark current will be produced.The purpose for selecting this kind of corrosive liquid is it to the non-selective of InP and InGaAs materials, simultaneously Adjustment Br and HBr proportioning is needed in corrosion process, to ensure that the corrosion of P++ types InP CAP layers 6 and InGaAs absorbed layers 4 is inclined Oblique angle is identical, different materials interface N/D, the burial of follow-up eigen I nP layers 8 is capable of the completion of high quality.

As shown in figure 3, two level table top is made using rotten using HCL and H3PO4 mixed liquor progress wet method after ICP etchings Erosion.Purpose using two-stage ladder mesa structure is to reduce the parasitic capacitance between the pad of electrode 9 and N++ types InP.

As shown in figure 4, eigen I nP layers 8 bury the committed step controlled for the utility model for dark current, its specific stream Cheng Wei：The protective layer that SIO2 is used as eigen I nP burials is grown by the way of PECVD after completing the technique such as Fig. 3, using corresponding Photolithography plate and photoetching process carry out figure conversion, retain one-level step Protection glue be used as next step wet etching stop Layer, BOE remove SIO2 after using acetone ultrasound mode Protection glue is removed, except be put into after water process in MOCVD carry out it is intrinsic InPDE is buried, and the extension for obtaining Fig. 4 using the SIO2 protective layers on step are removed using BOE after the completion of burial is illustrated Figure.Have in process above and what time should be noted：After the sample for completing Fig. 3 being prepared after completion mesa etch, step side Material is no any protection, and any corona treatment can all cause to damage to side, so removing what SIO2 was used It is BOE solution, material side material is passivated while SIO2 is removed；The reason for removing Protection glue is identical, it is impossible to makes With the mode of aura, so selection is completed using the mode of acetone ultrasound；Needed before the eigen I nP layers 8 for carrying out MOCVD grow Baking before being grown to material in the environment of PH3, the temperature of baking is 600-700 DEG C, carries out this after the completion of baking again The growth of layer of InP 8 is levied, growth temperature is 650-750 DEG C, and the burial thickness of eigen I nP layers 8 is traditionally arranged to be 0.4um-1.0um Scope.

As shown in figure 5, SIO2 protective layers quarter decorations purpose of design for protection bury after the completion of eigen I nP layers 8 and Strengthen the pulling force of subsequent electrode pad.

As shown in fig. 6-7, table top is entered by photosurface for the section after the completion of sample and plane pattern, incident light The absorbed layer of PIN chips, the flowing of photo-generated carrier is produced in the presence of working inverse voltage, photoproduction is produced in external circuit Electric current, complete opto-electronic conversion.

It is as shown in the table, it is the conventional photo performance indications of the utility model table top PIN chips.

As shown in figure 8, to return the dark current performance of normal temperature, the condition of aging after the utility model table top PIN chip high temperature For the reverse biased of -10V at a high temperature of 175 DEG C.The reliability index of dark current is judge fine or not important of this type chip Index, it can be seen that under such harsh aging condition, chip still being capable of normal work.

Preferred embodiment of the present utility model is the foregoing is only, it is all at this not to limit the utility model Within the spirit and principle of utility model, any modification, equivalent substitution and improvements made etc., the utility model should be included in Protection domain within.

Claims

A kind of 1. table top PIN side passivation structure, it is characterised in that：Served as a contrast including semi-insulating InP substrate and in semi-insulating InP Cushion, N++ types layer of InP, InGaAs absorbed layers, InGaAsP transition zones, the P++ types InP CAP layers grown successively above bottom With InGaAs contact layers, the cushion grown successively above the semi-insulating InP substrate, N++ types layer of InP, InGaAs absorbed layers, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers constitute flight table top, the side of the flight table top Growth has eigen I nP layers on wall, and being grown successively on the eigen I nP layers has SIO2 layers and SINx layers.
2. table top PIN as claimed in claim 1 side passivation structure, it is characterised in that：The thickness of the eigen I nP layers is 0.4-1um。
3. table top PIN as claimed in claim 1 side passivation structure, it is characterised in that：The flight table top is two-stage Ladder mesa structure, wherein InGaAs absorbed layers, InGaAsP transition zones, P++ types InP CAP layers and InGaAs contact layers are formed First order ladder table top, cushion constitute second level ladder table top with N++ type layer of InP.
4. table top PIN as claimed in claim 1 side passivation structure, it is characterised in that：The flight table top is positive exponent Trapezoidal table top.
5. table top PIN as claimed in claim 1 side passivation structure, it is characterised in that：The eigen I nP layers cover the rank Terraced layer table top whole sidewall areas.