CN206709976U - A kind of anti-back scattering superconducting single-photon detector - Google Patents
A kind of anti-back scattering superconducting single-photon detector Download PDFInfo
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- CN206709976U CN206709976U CN201720392352.5U CN201720392352U CN206709976U CN 206709976 U CN206709976 U CN 206709976U CN 201720392352 U CN201720392352 U CN 201720392352U CN 206709976 U CN206709976 U CN 206709976U
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Abstract
The utility model provides a kind of anti-back scattering superconducting single-photon detector, including clock generation module, laser, gate source table and nano wire chip, gate source table includes analog-digital chip and load resistance, and the output end of analog-digital chip connects nano wire chip by load resistance；The clock generation module is used to provide PWM ripple signals for laser and analog-digital chip；The laser is used to launch photon, and the nano wire chip is used to receive photon；Gate source table is used to control nano wire chip operation.The utility model can shield closely interior reflection photon in detection process so that photon acceptor is not influenceed by closely reflection photon, efficiently solves the problems, such as superconducting nano-wire single-photon detector backlight blinding；Laser ranging and laser radar application under the strong back scattering environment such as application extension of superconducting nano-wire single-photon detector to thick fog can be improved the reliability that detector uses in endoatmosphere.
Description
Technical field
The utility model belongs to SUPERCONDUCTING SINGLE-PHOTON DETECTION field, more particularly to a kind of anti-back scattering superconducting single-photon is visited
Survey device.
Background technology
Single-photon detector is the key technology in quantum information field, be realize single quantum state is manipulated, handle and
The basic fundamental means of research.Superconducting nano-wire single photon detector be it is a kind of utilize superconducting nano lines carry out photon detection
Highly sensitive detector.Detector launches photon by laser to distant object, and the photographic department of detector is divided into film nano
Cable architecture, electric current during work on nano wire are biased in the position of slightly less than critical current.After nanometer line absorption photon, inhale
The superconducting state for receiving region is destroyed in short-term, can then automatically restore to superconducting state.Shown as on circuit rapid increase, then
The electric pulse of exponential damping.By the way that this pulse signal is amplified, we identify single photon at can.
When traditional superconducting single-photon detector measures ground target in laser ranging application, it can be faced closely interior
Backlight blinding problem, i.e., aerosol within about 30km can scattering laser beam, the light particle for having served as multiple scattering returns along original route
Return after detected system captures, superconduction detection chip can be caused to be constantly in the state of quenching, so that detector work is obstructed,
This phenomenon is referred to as detector backlight blinding.When the particulate in air is excessive, back scattering is very strong, backlight blinding problem just occurs
.Backlight blinding problem seriously hinders application of the superconducting single-photon detector in the laser radar of endoatmosphere, constrains spy
Device is surveyed further to develop.
The existing method for optically proposing to solve the problems, such as backlight blinding is to be opened in detector receiving terminal using high-frequency light
Close, i.e., a kind of electromagnetic wave attenuation device.But photoswitch the problem of existing is that decay when photoswitch is closed to incident light is maximum only
There are 10 times, can still result in blinding problem；When photoswitch is opened, incident light is still suffered from and decayed to a certain degree, does not meet detection
Device job requirement.
Utility model content
Purpose of utility model：In order to solve the problems, such as detector backlight blinding existing for prior art, the utility model provides
A kind of anti-back scattering superconducting single-photon detector.
Technical scheme：A kind of anti-back scattering superconducting single-photon detector, it is characterised in that generate mould including clock signal
Block, laser, gate source table and nano wire chip, gate source table include analog-digital chip and load resistance, and digital-to-analogue turns
The output end for changing chip connects nano wire chip by load resistance；It is laser sum that the clock generation module, which is used for,
Mould conversion chip provides PWM ripple signals；The laser is used to launch photon, and the nano wire chip is used to receive photon；Institute
Gate source table is stated to be used to control nano wire chip operation.
Further, the clock generation module includes the first output port, the second output port and the 3rd output
Port；The control port of analog-digital chip includes the 5th pin, the 6th pin and the 7th pin, and the 7th pin is used for serial number
According to input, the 6th pin inputs for serial clock, and the 5th pin is used for input data frame synchronizing signal；Clock signal generates mould
First output port of block exports normal high level, connects the 6th pin of analog-digital chip；The of clock generation module
Two output ports export normal low level, connect the 5th pin of analog-digital chip；3rd output of clock generation module
Port output PWM involves serial data, connects the 7th pin of analog-digital chip；The output port of analog-digital chip includes
3rd pin and the 4th pin, the 4th pin connect the load resistance, and the 3rd pin is empty.
Further, when the PWM ripples are high level, the 3rd output port of clock generation module is simultaneously to digital-to-analogue
7th pin input serial data of conversion chip；When PWM ripples are low level, the 3rd output port of clock generation module
Simultaneously 0 is inputted to the 7th pin of analog-digital chip.
Further, the analog-digital chip uses the working method of serial date transfer, and the serial data is 24
Position data, wherein first 8 are control signal, the level value of rear 16 decisions output voltage, the output voltage is used to drive institute
State nano wire chip.
Further, the cycle of the PWM ripples signal is 1ms, and the dutycycle for making PWM ripple signals is T, 80% ＜ T ＜
99%.
Further, the clock generation module includes FPGA.
Further, the triggering mode of the laser triggers for external clock trailing edge.
Further, when the working method of the nano wire chip is PWM wave height level, chip normal work；PWM ripples are low
During level, chip is stopped.
Beneficial effect：Compared with prior art, a kind of anti-back scattering superconducting single-photon detector provided by the utility model,
Nano wire chip power supply is given by gating source table, laser is triggered by PWM ripples signal, while receive by the control of PWM ripples signal
The non-working time of rice noodles, photon is launched and reception separates in time, launch and receive two step operation rooms in photon and stay
Going out one section of standby time, shield closely interior reflection photon so that photon acceptor will not be influenceed by closely reflection photon,
Efficiently solve the problems, such as superconducting nano-wire single-photon detector backlight blinding.By adjusting the dutycycle of PWM ripples, further regulation
The non-working time of nano wire chip, to meet to shield the needs of different distance internal reflection photon.The utility model avoids existing
Not the problem of processing for having technology to be brought using electromagnetic wave attenuation device does not still result in blinding thoroughly；Also transmitting photon will not be declined
Subtract, transmitting photon is still met the job requirement of detector.The utility model can be by superconducting nano-wire single-photon detector
Application extension to laser ranging and laser radar application under the strong back scattering environment such as thick fog, improve detector in endoatmosphere
The reliability used.
Brief description of the drawings
Fig. 1 is the structured flowchart of the anti-back scattering superconducting single-photon detector of the utility model；
Fig. 2 is working timing figure of the present utility model；
Fig. 3 is the circuit theory diagrams that source matrix section is gated in the utility model.
Embodiment
The utility model is described in further detail with specific embodiment below in conjunction with the accompanying drawings.
As shown in figure 1, anti-back scattering superconducting single-photon detector includes clock generation module, laser, gate source
Table and nano wire chip, gate source table include analog-digital chip and load resistance, and the digital-to-analogue used in the present embodiment turns
Change the model DAC8552 of chip, naturally it is also possible to using the analog-digital chip of other models.Analog-digital chip DAC's
Output end connects nano wire chip by load resistance；It is laser and digital-to-analogue conversion core that the clock generation module, which is used for,
Piece provides PWM ripple signals.The laser is used to launch photon to testee 1, and the direction for launching photon is A directions；It is described
Nano wire chip is used to receive photon, and the direction for receiving photon is B directions.
Photon is exactly launched and received by the principle of gate source table control nano wire chip to be separated in time,
Photon is launched and received two step operation rooms and reserves adjustable standby time, thus can effectively shield a range of reflection
Photon.Standby time might as well be set as t*, according to distance and time, the relation of speed：
S=ct* (1)
In formula (1), s, which is photon, receives distance back and forth from being transmitted into, and c is the light velocity.If we to shield and detector
Distance is d all reflection photons, then：
From formula (1), formula (2), if to shield the reflection photon within 1.5~30km, the calculating of standby time
See formula (3)：
T is calculated*For 10~200 μ s.That is, set 10 between transmitting photon and the step operation of reception photon two
~200 μ s standby times, it is possible to effectively shield the reflection photon within 1.5~30km.
It is 10~200 μ s by standby time, the selection range that can further extrapolate the dutycycle T of PWM ripple signals is：
80% ＜ T ＜ 99%.
Clock generation module uses FPGA of the dominant frequency for 100MHz in the present embodiment, and reference clock signal is
10ns.PWM ripples are generated by FPGA, the dutycycle of PWM ripples is set by code can.As shown in Fig. 2 it is not drawn into figure whole
FPGA, only depict FPGA output interface part P2 (P3 for can short-circuit double-row needle), FPGA output port and digital-to-analogue conversion
Chip DAC control port connection, specific annexation are：P2 is 6 row's pins in figure；In figure (wherein, P3 arranges pins for 8
The short circuit of 1,2 pin；The short circuit of 3,4 pins；The short circuit of 5,6 pins；7,8 pins short circuit).Analog-digital chip DAC control port is drawn including the 7th
Pin Din, the 6th pin SCLK and the 5th pin SYNC, the 7th pin Din are used for serial date transfer, and the 6th pin SCLK is used for
Serial clock inputs, and the 5th pin SYNC is used for input data frame synchronizing signal；FPGA output port includes the first output end
Mouth, the second output port, the 3rd output port.P2 5 pin (not shown)s, defeated in FPGA the first output port connection figure
Go out normal high level, and then connect the 6th pin SCLK of analog-digital chip；The 3 of P2 in FPGA the second output port connection figure
Pin (not shown), normal low level is exported, and then connect the 5th pin SYNC of analog-digital chip；FPGA the 3rd output
P2 4 pin (not shown)s in the connection figure of port, output PWM involves 24 Bits Serial data, and then connects analog-digital chip
The 7th pin Din.Analog-digital chip DAC output port include the 3rd pin VoutB and the 4th pin VoutA the two
Output port is selective, and we select the 4th pin VoutA connections load resistance (not shown), load resistance here
Value is 100k Ω, and load resistance is connected between the 4th pin VoutA and nano wire chip, and output voltage passes through load resistance
Nano wire chip operation is controlled, the 3rd pin VoutB is empty.Ref6125 generations 2.5V reference voltage draws from 5,6 pins in figure
Go out, there is provided give analog-digital chip DAC.
DAC three control ports include the 7th pin Din, the 6th pin SCLK and the 5th pin SYNC, these three controls
The effect of port processed is serial date transfer, serial clock input, input data frame synchronizing signal respectively.Serial date transfer
(being inputted from the 7th pin Din) is 24 data, wherein first 8 are control signal, latter 16 are data, and 16 data are just
It is the level value for controlling digital-to-analogue output voltage.The triggering mode of nano wire chip triggers for high level, high level nano wire chip
Work, low level nano wire chip do not work.When the PWM ripples of the 7th pin Din inputs are high level, while FPGA is by 24
Data input the 7th pin Din, DAC normal work, output voltage control nano wire chip operation；When the 7th pin Din is inputted
PWM ripples when being low level, then DAC outputs are 0, and nano wire chip does not work.
The device of detector transmitting photon is pulsed laser, and laser pulse width is psec to nanosecond order, be can be set outer
Mode of operation is triggered, trailing edge triggering, i.e., when external clock trailing edge reaches, laser sends extremely narrow laser pulse, work
Cycle is adjustable.It is 1kHz that the present embodiment, which sets system operating frequency, i.e. the work period is 1 millisecond, is touched using external clock is unified
Hair.Clock signal, laser, gate source table working timing figure are as shown in figure 3, uppermost sequential is 1kHz clock signal；
Middle one is laser, and pulsewidth is very narrow, and pulsewidth can be neglected compared with standby time, work period；Bottom one is
Gate source table working timing figure.Cycle by the PWM ripple signals of FPGA generations is 1ms, can set accounting for for PWM ripples by code
Empty ratio.For example it is 90% to set dutycycle, then PWM wave height level time is 900 μ s, and low level is 100 μ s, and we are this
PWM ripples are input to the 7th port Din ports of laser and digital analog converter ADC, when trailing edge reaches, laser wink simultaneously
Between send pulse, and the 7th port Din ports are low level in 100 μ s thereafter, DAC output voltage 0, and nano wire chip is not
Work.In ensuing 900 μ s, PWM ripples are high level, while FPGA inputs 24 data, DAC output relevant voltages, nanometer
Core piece is in running order.(in this process, DAC the 6th port SCLK is constantly in high level, fifth port SYNC
Low level is constantly in, is controlled by FPGA, we actually only change the input of DAC the 7th port Din this port
State) which achieves nano wire chip idle 100 μ s standby times.
In addition, in order to meet the needs of shielding different distance internal reflection photon, standby time can be adjusted, the method for regulation
Actually control the dutycycle of PWM ripple signals caused by FPGA.Standby time is low level time, and adjusts dutycycle
Size can be realized by code.By adjusting the ＜ T ＜ 99% of dutycycle 80% i.e. settable 10~200 μ s standby times,
Reflection photon within can effectively 1.5~30km of shielding.
Claims (8)
1. a kind of anti-back scattering superconducting single-photon detector, it is characterised in that including clock generation module, laser, door
Control source table and nano wire chip, gate source table include analog-digital chip and load resistance, the output of analog-digital chip
End connects nano wire chip by load resistance；The clock generation module is used to carry for laser and analog-digital chip
For PWM ripple signals；The laser is used to launch photon, and the nano wire chip is used to receive photon；Gate source table is used
In control nano wire chip operation.
2. anti-back scattering superconducting single-photon detector according to claim 1, it is characterised in that the clock signal generation
Module includes the first output port, the second output port and the 3rd output port；The control port of analog-digital chip includes the
Five pins, the 6th pin and the 7th pin, the 7th pin are used for serial date transfer, and the 6th pin inputs for serial clock,
5th pin is used for input data frame synchronizing signal；First output port of clock generation module exports normal high level, even
Connect the 6th pin of analog-digital chip；Second output port of clock generation module exports normal low level, connects digital-to-analogue
5th pin of conversion chip；The 3rd output port output PWM of clock generation module involves serial data, connects digital-to-analogue
7th pin of conversion chip；The output port of analog-digital chip includes the 3rd pin and the 4th pin, the connection of the 4th pin
The load resistance, the 3rd pin are empty.
3. anti-back scattering superconducting single-photon detector according to claim 2, it is characterised in that the PWM ripples are high electricity
Usually, the 3rd output port of clock generation module is simultaneously to the 7th pin input serial data of analog-digital chip；
When PWM ripples are low level, the 3rd output port of clock generation module is simultaneously defeated to the 7th pin of analog-digital chip
Enter 0.
4. the anti-back scattering superconducting single-photon detector according to claim 1 or 2 or 3, it is characterised in that the digital-to-analogue turns
The working method that chip uses serial date transfer is changed, the serial data is 24 data, wherein first 8 are control signal,
The level value of 16 decision output voltages afterwards, the output voltage are used to drive the nano wire chip.
5. the anti-back scattering superconducting single-photon detector according to claim 1 or 2 or 3, it is characterised in that the PWM ripples
The cycle of signal is 1ms, and the dutycycle for making PWM ripple signals is T, 80% ＜ T ＜ 99%.
6. the anti-back scattering superconducting single-photon detector according to claim 1 or 2 or 3, it is characterised in that the clock letter
Number generation module includes FPGA.
7. the anti-back scattering superconducting single-photon detector according to claim 1 or 2 or 3, it is characterised in that the laser
Triggering mode be external clock trailing edge triggering.
8. the anti-back scattering superconducting single-photon detector according to claim 1 or 2 or 3, it is characterised in that the nano wire
When the working method of chip is PWM wave height level, chip normal work；During PWM ripple low levels, chip is stopped.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201720392352.5U CN206709976U (en) | 2017-04-14 | 2017-04-14 | A kind of anti-back scattering superconducting single-photon detector |
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|---|---|---|---|
| CN201720392352.5U CN206709976U (en) | 2017-04-14 | 2017-04-14 | A kind of anti-back scattering superconducting single-photon detector |
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