CN206658193U

CN206658193U - A kind of multi channel signals sampling system of time sharing sampling

Info

Publication number: CN206658193U
Application number: CN201720391743.5U
Authority: CN
Inventors: 邹国辉; 刘铁军; 陶泽安
Original assignee: Hunan Li'neng Science & Technology Co Ltd
Current assignee: Weisheng Energy Technology Co ltd
Priority date: 2017-04-14
Filing date: 2017-04-14
Publication date: 2017-11-21
Anticipated expiration: 2027-04-14

Abstract

The utility model proposes a kind of multi channel signals sampling system of time sharing sampling, including input filter circuit, the CPLD, the DSP with AD mouths and the sampling channel selection circuit that produce control signal, wherein, the input filter circuit is RC low-pass filter circuits；Filtered multi-channel sampling signal carries out channel selecting single channel output again by sampling channel selection circuit；The CPLD of control signal is produced, receives the two pulse signals that DSP is sent, exports gating signal, gating signal is used to which specific sampled signal output realized；DSP with AD mouths, the sampled signal for being chosen to export, which enters in DSP AD mouths, to be handled.It realizes the continuous sampling of multichannel analog signals using the principle of analog multiplexer, so as to realize that multiple signals sample in single passage, greatlys save the AD mouth resources of multiple signals sample circuit, reduces cost.

Description

A kind of multi channel signals sampling system of time sharing sampling

Technical field

It the utility model is related to field of signal processing, the multi channel signals sampling system of more particularly to a kind of time sharing sampling.

Background technology

Existing Intermediate Frequency Digital Receiver is mainly made up of single analog-digital converter (ADC) and digital down converter, Wherein analog-to-digital conversion module mainly completes the sampling of analog if signal, and converts and obtain digitized intermediate-freuqncy signal, under numeral Frequency converter changes signal interested to base band, while does sampling rate conversion and filtering process, after obtaining orthogonal I, Q signal Follow-up digital signal processor is sent to carry out base band signal process, digital down converter is whole inside whole intermediate-frequency receiver The core of Intermediate Frequency Digital Receiver, but under normal circumstances, existing Intermediate Frequency Digital Receiver is only capable of realizing single pass letter Number sampling, operating efficiency is low, and working method is single.With the popularization and development of electronic product, industry and consumer electronics product Function it is more and more, it is necessary to the signal of acquisition process is also more, so signal sampling channel is just with increasing.For existing The implementation method of some multichannel intermediate-frequency receivers, typically provided with multiple AD passages, the corresponding ADC mould of each AD passages Block, after ADC sample conversion, it is connected again with FPGA module after digital down converter is handled, although such design can be protected The accurate rate of multi-channel sampling processing is demonstrate,proved, but each AD passage just needs one piece of corresponding digital down converter, so It is not only with high costs with regard to needing to take substantial amounts of AD mouths, while also add the difficulty of plank design.

The content of the invention

The technical problems to be solved in the utility model is：A kind of multi channel signals sampling system of time sharing sampling is provided, its The AD mouth resources of sample circuit can be saved, reduce cost.

What solution of the present utility model was realized in：A kind of multi channel signals sampling system of time sharing sampling, bag Including input filter circuit, produce the CPLD of control signal and the DSP with AD mouths, it also includes sampling channel selection circuit, wherein,

The input filter circuit is RC low-pass filter circuits, for being filtered to the multi-channel sampling signal of input；

Filtered multi-channel sampling signal carries out channel selecting single channel output again by sampling channel selection circuit；

The CPLD of control signal is produced, receives the two pulse signals that DSP is sent, exports gating signal, gating signal is used In which specific sampled signal output of realization；

DSP with AD mouths, the sampled signal for being chosen to export, which enters in DSP AD mouths, to be handled.

Another technical scheme of the present utility model is that on above-mentioned basis the sampling channel selection circuit includes 8 Channel analog multiplexer, after filtering after multi-channel sampling signal and 8 channel analog multiplexer input Pin is connected.

Another technical scheme of the present utility model be it is above-mentioned basis on, the 8 channel analog multiplexer type Number it is SN74LV4051ADR.

Another technical scheme of the present utility model is that on above-mentioned basis two GPIO of the DSP and CPLD are managed Pin is direct-connected, and GP configuring IO sense is to be exported from DSP, into CPLD.

Another technical scheme of the present utility model be it is above-mentioned basis on, three GPIO pins of the CPLD with The channel selecting pin of SN74LV4051ADR chips is connected.

Another technical scheme of the present utility model is on above-mentioned basis, the two pulse signals that the DSP is sent For CP1 and CP2, in pulse signal CP1 a cycle, pulse signal CP2 has the rising edge of more than 8.

As can be seen from the above technical solutions, the multi channel signals sampling system of time sharing sampling described in the utility model, By the sampling channel selection circuit of design, realize that the continuous of multichannel analog signals is adopted using the principle of analog multiplexer Sample, so as to realize that multiple signals sample in single passage, greatly save the AD mouth resources of multiple signals sample circuit, drop Low cost.

Brief description of the drawings

Form a part of accompanying drawing of the present utility model to be used for providing further understanding to of the present utility model, this practicality is new The schematic description and description of type is used to explain the utility model, does not form to improper restriction of the present utility model.

Fig. 1 is the circuit theory of the multi channel signals sampling system of time sharing sampling in a kind of embodiment of the utility model Figure；

Fig. 2 is the sequential logic of the control passage selection in the multi channel signals sampling system of time sharing sampling described in Fig. 1 Figure；

Fig. 3 is the operational flow diagram of the multi channel signals sampling system of time sharing sampling shown in Fig. 1.

Embodiment

The utility model is described in detail below in conjunction with the accompanying drawings, the description of this part be only it is exemplary and explanatory, There should not be any restriction effect to the scope of protection of the utility model.In addition, those skilled in the art's retouching according to this document State, respective combination can be carried out to the feature in embodiment in this document and in different embodiments.

Term " first " in specification and claims of the present utility model and above-mentioned accompanying drawing, " second ", " the 3rd " (if present)s such as " the 4 " is for distinguishing similar object, without for describing specific order or precedence.Should The data that the understanding so uses can exchange in the appropriate case, so as to embodiment of the present utility model described herein, example If implemented with the order in addition to those for illustrating or describing herein.In addition, term " comprising " and " having " and Their any deformation, it is intended that cover it is non-exclusive include, for example, containing the process of series of steps or unit, side Method, system, product or equipment are not necessarily limited to those steps clearly listed or unit, but may include not list clearly Or for the intrinsic other steps of these processes, method, product or equipment or unit.

The utility model embodiment is as follows, as shown in figure 1, a kind of multi channel signals sampling system of time sharing sampling, timesharing The multi channel signals sampling system of sampling, including input filter circuit, the CPLD of generation control signal and the DSP with AD mouths, its Also include sampling channel selection circuit, wherein, the input filter circuit is RC low-pass filter circuits, for the more logical of input Road sampled signal is filtered；Filtered multi-channel sampling signal carries out channel selecting list again by sampling channel selection circuit Passage exports；The CPLD of control signal is produced, receives the two pulse signals that DSP is sent, exports gating signal, gating signal is used In which specific sampled signal output of realization；DSP with AD mouths, the sampled signal for being chosen output enter in DSP AD mouths Handled.

On the basis of above-described embodiment, in another embodiment of the utility model, the sampling channel selection circuit includes 8 Channel analog multiplexer, after filtering after multi-channel sampling signal and 8 channel analog multiplexer input Pin is connected.

On the basis of above-described embodiment, in another embodiment of the utility model, the 8 channel analog multiplexer type Number it is SN74LV4051ADR.

On the basis of above-described embodiment, in another embodiment of the utility model, two GPIO pipes of the DSP and CPLD Pin is direct-connected, and GP configuring IO sense is to be exported from DSP, into CPLD.

On the basis of above-described embodiment, in another embodiment of the utility model, three GPIO pins of the CPLD with The channel selecting pin of SN74LV4051ADR chips is connected.

On the basis of above-described embodiment, in another embodiment of the utility model, as shown in Fig. 2 the two of DSP transmissions Road pulse signal is CP1 and CP2, and in pulse signal CP1 a cycle, pulse signal CP2 has 8 rising edges.

As shown in figure 3, the multi channel signals sampling system running of sampling is as follows：

S1, DSP send two pulse signals CP1 and CP2 to CPLD；

S2, CPLD are detecting that CP1 is in high level, while when CP2 has a rising edge, and this rising edge is as counting The edging trigger signal of clearing, CPLD counter O resets simultaneously start counting up；

S3, the level combinations signal to be matched according to count value, CPLD outputs with counting；

S4, the level combinations signal exported according to CPLD, the sampled signal of respective channel is selected to export the AD mouths for entering DSP Complete sampling.

Wherein, in pulse signal CP1 a cycle, pulse signal CP2 has 8 rising edges.

Specifically, sampled signal TEMP1~TEMP7 enters circuit from connector P1, by prime RC low-pass filter circuits Afterwards, into the signal input pin IN0-IN6 of U1 (SN74LV4051ADR) chip, now U3 (CPLD) gives U1 9,10,11 pin three Individual different combination level can correspond to the input signal for exporting respective channel.U1 6 pin INH are that the control of chip independent switch is drawn Pin, there is the independent function of opening and closing chip, when INH is high level, chip output is closed；When INH is low level, core Piece output is opened, can be with normal output signal.We are directly grounded INH pins herein, in order that allowing chip to be in always The working condition of opening.Which input signal what the level combinations of U1 9,10,11 pin determined output is.ABC combines A A high position, C are lowest order, then ABC combinations have 000,001,010,011,100,101,110,111, it is corresponding be exactly passage 0, 1、2、3、4、5、6、7.When ABC pins have input one group of level, the sampled signal of corresponding selected passage will be from U1 3 pin Output.Such as level is sometime being set low entirely to tri- pin of ABC, then the input signal of passage 0 is selected, can be from 3 pin Output.So we can be by distributing different level which road signal determined to export, if we are needed to these to ABC Signal real-time sampling (from the uninterruptedly circulation output of passage 0~7), then only need within a certain period of time by ABC level from 000 ~111 carry out cycle assignment, and the signal of such passage 0 to 7 ceaselessly can be sequentially output from pin 3.U2 (DSP) and U3 are provided with Two GPIO direct connections, CP1 is triggering frame pulse, CP2 is count pulse, and CP1 and the group pulses of CP2 two are to be sent to U3 from U2.Arteries and veins Signal concrete form is rushed as shown in Fig. 2 wherein, CP2 number of pulses is relevant with the channel number of required sampling, is adopted in this example 8 passages of sample, therefore 8 pulses are sent, U3 is while count pulse CP2 rising edges are detected, if frame pulse CP1 is height Level, then U3 internal counters reset and started counting up.When being counted as 1, first channel sample signal output is selected.When When system judges have selected first passage output, U3 56,57,58 3 pins are controlled to export required level 000, Now the signal of U3 3 pin output is the sampled signal of first passage.By above step, TEMP0~TEMP7 8 tunnels altogether The AD mouth that TEMP signals finally sequentially enter processor is handled.Wherein, SN74LV4051ADR is that 8 tunnels analogies are more Path multiplexer, chip technology data and pin explanation are known technology, be will not be repeated here.CPLD(Complex Programmable Logic Device) CPLD, it is the device come out from PAL and GAL device developments, Belong to large scale integrated circuit scope.DSP is digital signal processor, can select existing model, is no longer situated between in detail herein Continue.

Described above is only preferred embodiment of the present utility model, it is noted that for the common skill of the art For art personnel, on the premise of the utility model principle is not departed from, some improvements and modifications can also be made, these improve and Retouching also should be regarded as the scope of protection of the utility model.

Claims

1. a kind of multi channel signals sampling system of time sharing sampling, including input filter circuit, produce control signal CPLD and DSP with AD mouths, it is characterised in that also including sampling channel selection circuit, wherein,

The CPLD of control signal is produced, receives the two pulse signals that DSP is sent, exports gating signal, gating signal is used for real Which now specific sampled signal output；

2. the multi channel signals sampling system of time sharing sampling according to claim 1, it is characterised in that the sampling channel Selection circuit includes 8 channel analog multiplexers, after filtering after multi-channel sampling signal and the 8 tunnels analogy multichannel The input pin of multiplexer is connected.

3. the multi channel signals sampling system of time sharing sampling according to claim 2, it is characterised in that the 8 passage mould Intend multiplexer model SN74LV4051ADR.

4. the multi channel signals sampling system of time sharing sampling according to claim 3, it is characterised in that the DSP and CPLD two GPIO pins are direct-connected, and GP configuring IO sense is to be exported from DSP, into CPLD.

5. the multi channel signals sampling system of time sharing sampling according to claim 4, it is characterised in that the three of the CPLD Individual GPIO pins are connected with the channel selecting pin of SN74LV4051ADR chips.

6. the multi channel signals sampling system of time sharing sampling according to any one of claim 1 to 5, it is characterised in that The two pulse signals that the DSP is sent are CP1 and CP2, and in pulse signal CP1 a cycle, pulse signal CP2 has 8 Individual rising edge.