CN206649512U - The AD process circuits and electric automobile of multi-breal switch signal - Google Patents
The AD process circuits and electric automobile of multi-breal switch signal Download PDFInfo
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Abstract
The utility model provides the AD process circuits and electric automobile of multi-breal switch signal, including：In the case that multigroup combinational is used to close at least one first switch, and at least one second switch disconnects, analog voltage is exported；Signal processing circuit is used to analog voltage being converted into digital voltage；Single-chip microcomputer is used to read digital voltage, and carries out corresponding computing, so as to effectively reduce rigid line arrangement, improves the utilization rate of signal processing circuit signaling interface.
Description
Technical Field
The utility model belongs to the technical field of AD processing circuit and specifically relates to AD processing circuit and electric automobile who relates to multiple switching signal.
Background
At present, a plurality of groups of switch signals are input at the input end of a signal processing circuit, each group of switch signals needs a hard wire and a corresponding circuit to be connected with the signal processing circuit, and each hard wire occupies an AD interface of the signal processing circuit, so that the hard wire interface of the signal processing circuit is complicated, and a fault addiction is easily caused.
SUMMERY OF THE UTILITY MODEL
In view of this, the utility model aims at providing a AD processing circuit and electric automobile of multiple switching signal can effectively reduce the hardwire and arrange, improves the rate of utilization of signal processing circuit signal interface.
In a first aspect, an embodiment of the present invention provides an AD processing circuit for multiple switching signals, including: the system comprises a plurality of groups of combined switch circuits, a signal processing circuit and a single chip microcomputer, wherein the plurality of groups of combined switch circuits, the signal processing circuit and the single chip microcomputer are sequentially connected;
the multi-group combined switch circuit is used for outputting analog voltage under the condition that at least one first switch is closed and at least one second switch is opened;
the signal processing circuit is used for converting the analog voltage into a digital voltage;
and the singlechip is used for reading the digital voltage and carrying out corresponding operation.
In combination with the first aspect, the present invention provides a first possible implementation manner of the first aspect, wherein the multi-group combination switch circuit includes a plurality of switch circuits connected in parallel, one end of each of the switch circuits is connected to a power supply voltage, the other end of each of the switch circuits is connected to one end of a resistor R5 and an input end of the signal processing circuit, and the other end of the resistor R5 is grounded.
In combination with the first aspect, the present invention provides a second possible implementation manner of the first aspect, wherein the multi-group combination switch circuit includes a plurality of switch circuits connected in parallel, one end of each of the switch circuits is grounded, the other end of each of the switch circuits is connected to one end of a resistor R10 and an input end of the signal processing circuit, and the other end of the resistor R10 is connected to a power supply voltage.
With reference to the first possible implementation manner of the first aspect, an embodiment of the present invention provides a third possible implementation manner of the first aspect, wherein the plurality of switch circuits are respectively a first switch circuit, a second switch circuit, a third switch circuit, and a fourth switch circuit;
when the first switch S1 in the first switch circuit is closed and the second switch S2 in the second switch circuit, the third switch S3 in the third switch circuit, and the fourth switch S4 in the fourth switch circuit are open, a first analog voltage is calculated according to the following equation:
V1＝Vcc*(R5/(R1+R5))
wherein, V1Is the first analog voltage, VccIs the supply voltage;
or,
when the second switch S2 in the second switch circuit is closed and the first switch S1 in the first switch circuit, the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are open, calculating a second analog voltage according to:
V2＝Vcc*(R5/(R2+R5))
wherein, V2Is said second analog voltage, VccIs the supply voltage;
or,
when the third switch S3 in the third switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the fourth switch S4 in the fourth switch circuit are open, calculating a third analog voltage according to:
V3＝Vcc*(R5/(R3+R5))
wherein, V3Is said third analog voltage, VccIs the supply voltage;
or,
when the fourth switch S4 in the fourth switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the third switch S3 in the third switch circuit are open, a fourth analog voltage is calculated according to the following equation:
V4＝Vcc*(R5/(R4+R5))
wherein, V4Is said fourth analog voltage, VccIs the supply voltage.
In combination with the third possible implementation manner of the first aspect, the present invention provides a fourth possible implementation manner of the first aspect, wherein when the first switch S1 in the first switch circuit and the second switch S2 in the second switch circuit are closed, and the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are opened, a fifth analog voltage is calculated according to the following formula:
wherein, V5Is the fifth analog voltage, VccIs the supply voltage.
In combination with the fourth possible implementation manner of the first aspect, the present invention provides a fifth possible implementation manner of the first aspect, wherein when the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the third switch S3 in the third switch circuit are closed, and the fourth switch S4 in the fourth switch circuit is opened, a sixth analog voltage is calculated according to the following formula:
wherein, V6Is the sixth analog voltage, VccIs the supply voltage.
With reference to the second possible implementation manner of the first aspect, an embodiment of the present invention provides a sixth possible implementation manner of the first aspect, wherein the plurality of switch circuits are a fifth switch circuit, a sixth switch circuit, a seventh switch circuit, and an eighth switch circuit, respectively;
when the fifth switch S5 in the fifth switch circuit is closed and the sixth switch S6 in the sixth switch circuit, the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are open, a seventh analog voltage is calculated according to the following equation:
V7＝Vcc*(R6/(R10+R6))
wherein, V7Is the seventh analog voltage, VccIs the power supplyA voltage;
or,
when the sixth switch S6 in the sixth switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are open, an eighth analog voltage is calculated according to the following equation:
V8＝Vcc*(R7/(R10+R7))
wherein, V8Is the eighth analog voltage, VccIs the supply voltage;
or,
when a seventh switch S7 in the seventh switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit and the eighth switch S8 in the eighth switch circuit are open, a ninth analog voltage is calculated according to the following equation:
V9＝Vcc*(R8/(R10+R8))
wherein, V9Is the ninth analog voltage, VccIs the supply voltage;
or,
when an eighth switch S8 in the eighth switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit and the seventh switch S7 in the seventh switch circuit are open, a tenth analog voltage is calculated according to the following equation:
V10＝Vcc*(R9/(R10+R9))
wherein, V10Is the tenth analog voltage, VccIs the supply voltage.
In combination with the sixth possible implementation manner of the first aspect, the present invention provides a seventh possible implementation manner of the first aspect, wherein when the fifth switch S5 in the fifth switch circuit and the sixth switch S6 in the sixth switch circuit are closed, and the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are opened, an eleventh analog voltage is calculated according to the following formula:
wherein, V11Is the eleventh analog voltage, VccIs the supply voltage.
In combination with the seventh possible implementation manner of the first aspect, the present invention provides an eighth possible implementation manner of the first aspect, wherein when the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit, and the seventh switch S7 in the seventh switch circuit are closed, and the eighth switch S8 in the eighth switch circuit is opened, a twelfth analog voltage is calculated according to the following formula:
wherein, V12Is the twelfth analog voltage, VccIs the supply voltage.
In a second aspect, the present invention further provides an electric vehicle, including the AD processing circuit for multiple switching signals as described above.
The embodiment of the utility model provides a multiple switch signal's AD treatment circuit and electric automobile, include: the multi-group combined switch circuit is used for outputting analog voltage under the condition that at least one first switch is closed and at least one second switch is opened; the signal processing circuit is used for converting the analog voltage into digital voltage; the singlechip is used for reading the digital voltage and carrying out corresponding operation, thereby effectively reducing the hard wire arrangement and improving the utilization rate of the signal interface of the signal processing circuit.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of an AD processing circuit for multiple switching signals according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a multi-group combination switch circuit according to a second embodiment of the present invention;
fig. 3 is a second schematic diagram of a multi-group combination switch circuit according to a third embodiment of the present invention;
fig. 4 is a flowchart of an AD processing method for multiple switching signals according to a fourth embodiment of the present invention.
Icon:
10-multiple groups of combined switch circuits; 20-a signal processing circuit; 30-single chip microcomputer.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
To facilitate understanding of the present embodiment, the following detailed description will be given of embodiments of the present invention.
The first embodiment is as follows:
fig. 1 is a schematic diagram of an AD processing circuit for multiple switching signals according to an embodiment of the present invention.
Referring to fig. 1, the circuit includes a plurality of groups of combination switch circuits 10, a signal processing circuit 20 and a single chip microcomputer 30, wherein the plurality of groups of combination switch circuits 10, the signal processing circuit 20 and the single chip microcomputer 30 are connected in sequence;
a multi-bank combination switch circuit 10 for outputting an analog voltage in a case where at least one first switch is closed and at least one second switch is open;
here, the multi-group combination switch circuit includes a plurality of parallel switch circuits including switches and resistors, and outputs different analog voltages when at least one of the switches is closed and at least one of the switches is open.
A signal processing circuit 20 for converting the analog voltage into a digital voltage;
and the singlechip 30 is used for reading the digital voltage and carrying out corresponding operation.
Here, the signal processing circuit 20 and the single chip microcomputer 30 can determine whether the combination switch is in a closed state or an open state, thereby performing corresponding operations.
An electric vehicle includes the AD processing circuit of the multiple switching signal as described above.
Example two:
fig. 2 is a schematic diagram of a multi-group combination switch circuit according to a second embodiment of the present invention.
Referring to fig. 2, the multi-group combination switch circuit includes a plurality of switch circuits connected in parallel, one ends of the plurality of switch circuits are all connected to a power supply voltage, the other ends of the plurality of switch circuits are respectively connected to one end of a resistor R5 and an input end of the signal processing circuit, and the other end of the resistor R5 is grounded.
The plurality of switch circuits are respectively a first switch circuit, a second switch circuit, a third switch circuit and a fourth switch circuit; wherein the first switch circuit comprises a first switch S1 and a resistor R1; the second switch circuit comprises a second switch S2 and a resistor R2; the third switch circuit comprises a third switch S3 and a resistor R3; the fourth switching circuit includes a fourth switch S4 and a resistor R4.
The first switch circuit, the second switch circuit, the third switch circuit and the fourth switch circuit are finally connected in parallel to form a hard line for the signal processing circuit 20, so that the hard line arrangement can be effectively reduced, and the utilization rate of a signal interface of the signal processing circuit is improved.
When one of the first switch S1, the second switch S2, the third switch S3 and the fourth switch S4 is closed and the other three switches are open, the specific conditions are as follows:
when the first switch S1 in the first switch circuit is closed and the second switch S2 in the second switch circuit, the third switch S3 in the third switch circuit, and the fourth switch S4 in the fourth switch circuit are open, the first analog voltage is calculated according to equation (1):
V1＝Vcc*(R5/(R1+R5)) (1)
wherein, V1Is the first analog voltage, VccIs the supply voltage;
or,
when the second switch S2 in the second switch circuit is closed and the first switch S1 in the first switch circuit, the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are open, the second analog voltage is calculated according to equation (2):
V2＝Vcc*(R5/(R2+R5)) (2)
wherein, V2Is a second analog voltage, VccIs the supply voltage;
or,
when the third switch S3 in the third switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the fourth switch S4 in the fourth switch circuit are open, the third analog voltage is calculated according to formula (3):
V3＝Vcc*(R5/(R3+R5)) (3)
wherein, V3Is a third analog voltage, VccIs the supply voltage;
or,
when the fourth switch S4 in the fourth switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the third switch S3 in the third switch circuit are open, the fourth analog voltage is calculated according to equation (4):
V4＝Vcc*(R5/(R4+R5)) (4)
wherein, V4Is a fourth analog voltage, VccIs the supply voltage.
When two of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed and the other two are open, the following is the specific case:
when the first switch S1 in the first switch circuit and the second switch S2 in the second switch circuit are closed and the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are open, a fifth analog voltage is calculated according to formula (5):
wherein, V5Is a fifth analog voltage, VccIs the supply voltage.
When the first switch S1 in the first switch circuit and the second switch S2 in the second switch circuit are open and the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are closed, a thirteenth analog voltage is calculated according to formula (6):
it should be noted that when two of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed and the other two are open, only the formula (5) and the formula (6) are used for explanation, which includes various cases, and details are not described here.
When three of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed and the other is open, the following is the specific case:
when the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, the third switch S3 in the third switch circuit are closed, and the fourth switch S4 in the fourth switch circuit is open, the sixth analog voltage is calculated according to equation (7):
wherein, V6Is a sixth analog voltage, VccIs the supply voltage.
It should be noted that when three of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 are closed and the other is open, only the formula (7) is used for explanation, which also includes various cases, and details are not described here.
Example three:
fig. 3 is a second schematic diagram of a multi-group combination switch circuit according to a second embodiment of the present invention.
Referring to fig. 3, the multi-group combination switch circuit includes a plurality of switch circuits connected in parallel, one ends of the plurality of switch circuits are all grounded, the other ends of the plurality of switch circuits are respectively connected to one end of a resistor R10 and an input end of the signal processing circuit, and the other end of a resistor R10 is connected to a power supply voltage.
The plurality of switch circuits are respectively a fifth switch circuit, a sixth switch circuit, a seventh switch circuit and an eighth switch circuit, wherein the fifth switch circuit comprises a fifth switch S5 and a resistor R5; the sixth switching circuit comprises a sixth switch S6 and a resistor R6; the seventh switching circuit comprises a seventh switch S7 and a resistor R7; the eighth switching circuit comprises an eighth switch S8 and a resistor R8;
the fifth switch circuit, the sixth switch circuit, the seventh switch circuit and the eighth switch circuit are finally connected in parallel to form a hard line for the signal processing circuit 20, so that the hard line arrangement can be effectively reduced, and the utilization rate of the signal interface of the signal processing circuit is improved.
When one of the fifth switch S5, the sixth switch S6, the seventh switch S7 and the eighth switch S8 is closed, the other three switches are opened, as follows:
when the fifth switch S5 in the fifth switch circuit is closed and the sixth switch S6 in the sixth switch circuit, the seventh switch S7 in the seventh switch circuit, and the eighth switch S8 in the eighth switch circuit are opened, the seventh analog voltage is calculated according to formula (8):
V7＝Vcc*(R6/(R10+R6)) (8)
wherein, V7Is a seventh analog voltage, VccIs the supply voltage;
or,
when the sixth switch S6 in the sixth switching circuit is closed and the fifth switch S5 in the fifth switching circuit, the seventh switch S7 in the seventh switching circuit, and the eighth switch S8 in the eighth switching circuit are opened, the eighth analog voltage is calculated according to the formula (9):
V8＝Vcc*(R7/(R10+R7)) (9)
wherein, V8Is the eighth analog voltage, VccIs the supply voltage;
or,
when the seventh switch S7 in the seventh switching circuit is closed and the fifth switch S5 in the fifth switching circuit, the sixth switch S6 in the sixth switching circuit and the eighth switch S8 in the eighth switching circuit are opened, the ninth analog voltage is calculated according to the formula (10):
V9＝Vcc*(R8/(R10+R8)) (10)
wherein, V9Is a ninth analog voltage, VccIs the supply voltage;
or,
when the eighth switch S8 in the eighth switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit and the seventh switch S7 in the seventh switch circuit are opened, the tenth analog voltage is calculated according to the formula (11):
V10＝Vcc*(R9/(R10+R9)) (11)
wherein, V10Is the tenth analog voltage, VccIs the supply voltage.
When two of the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are closed and the other two are open, the specific conditions are as follows:
when the fifth switch S5 in the fifth switch circuit and the sixth switch S6 in the sixth switch circuit are closed, and the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are opened, the eleventh analog voltage is calculated according to formula (12):
wherein, V11Is the eleventh analog voltage, VccIs the supply voltage.
It should be noted that when two of the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are closed and the other two are open, only the formula (12) is used for explanation, which also includes various cases, and details are not described here.
When the fifth switch S5, the sixth switch S6, and the seventh switch S7 are closed, and the eighth switch S8 is open, the following is the case:
when the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit, and the seventh switch S7 in the seventh switch circuit are closed, and the eighth switch S8 in the eighth switch circuit is opened, the twelfth analog voltage is calculated according to the formula (13):
wherein, V12Is the twelfth analog voltage, VccIs the supply voltage.
It should be noted that when the fifth switch S5, the sixth switch S6, and the seventh switch S7 are closed and the eighth switch S8 is opened, only the formula (13) is used for explanation, which includes various cases, and details are not described here.
Example four:
fig. 4 is a flowchart of an AD processing method for multiple switching signals according to a fourth embodiment of the present invention.
Referring to fig. 4, the method includes the steps of:
step S101, outputting analog voltage under the condition that at least one first switch is closed and at least one second switch is opened;
step S102, converting the analog voltage into digital voltage;
step S103, reading the digital voltage and performing corresponding operation.
The embodiment of the present invention provides a computer program product, which includes a computer readable storage medium storing a program code, wherein the instruction included in the program code can be used to execute the method described in the foregoing method embodiment, and the specific implementation can refer to the method embodiment, which is not described herein again.
It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the system and the apparatus described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In addition, in the description of the embodiments of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present invention, and are not intended to limit the technical solution of the present invention, and the protection scope of the present invention is not limited thereto, although the present invention is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: those skilled in the art can still modify or easily conceive of changes in the technical solutions described in the foregoing embodiments or make equivalent substitutions for some technical features within the technical scope of the present disclosure; such modifications, changes or substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. An AD processing circuit for multiple switching signals, comprising: the system comprises a plurality of groups of combined switch circuits, a signal processing circuit and a single chip microcomputer, wherein the plurality of groups of combined switch circuits, the signal processing circuit and the single chip microcomputer are sequentially connected;
the multi-group combined switch circuit is used for outputting analog voltage under the condition that at least one first switch is closed and at least one second switch is opened;
the signal processing circuit is used for converting the analog voltage into a digital voltage;
and the singlechip is used for reading the digital voltage and carrying out corresponding operation.
2. The multiple switch signal AD processing circuit of claim 1, wherein the multiple combination switch circuit includes a plurality of switch circuits connected in parallel, one end of each of the plurality of switch circuits is connected to a power supply voltage, the other ends of the plurality of switch circuits are respectively connected to one end of a resistor R5 and an input terminal of the signal processing circuit, and the other end of the resistor R5 is grounded.
3. The multiple switch signal AD processing circuit of claim 1, wherein the multiple combination switch circuit includes a plurality of switch circuits connected in parallel, one end of each of the plurality of switch circuits is connected to ground, the other ends of the plurality of switch circuits are respectively connected to one end of a resistor R10 and an input end of the signal processing circuit, and the other end of the resistor R10 is connected to a power supply voltage.
4. The AD processing circuit for multiple switching signals according to claim 2, wherein the plurality of switching circuits are a first switching circuit, a second switching circuit, a third switching circuit, and a fourth switching circuit, respectively;
when the first switch S1 in the first switch circuit is closed and the second switch S2 in the second switch circuit, the third switch S3 in the third switch circuit, and the fourth switch S4 in the fourth switch circuit are open, a first analog voltage is calculated according to the following equation:
V1＝Vcc*(R5/(R1+R5))
wherein, V1Is the first analog voltage, VccIs the supply voltage;
or,
when the second switch S2 in the second switch circuit is closed and the first switch S1 in the first switch circuit, the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are open, calculating a second analog voltage according to:
V2＝Vcc*(R5/(R2+R5))
wherein, V2Is said second analog voltage, VccIs the supply voltage;
or,
when the third switch S3 in the third switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the fourth switch S4 in the fourth switch circuit are open, calculating a third analog voltage according to:
V3＝Vcc*(R5/(R3+R5))
wherein, V3Is said third analog voltage, VccIs the supply voltage;
or,
when the fourth switch S4 in the fourth switch circuit is closed and the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, and the third switch S3 in the third switch circuit are open, a fourth analog voltage is calculated according to the following equation:
V4＝Vcc*(R5/(R4+R5))
wherein, V4Is said fourth analog voltage, VccIs the supply voltage.
5. The multi-switch signal AD processing circuit of claim 4, wherein when the first switch S1 in the first switch circuit and the second switch S2 in the second switch circuit are closed and the third switch S3 in the third switch circuit and the fourth switch S4 in the fourth switch circuit are open, a fifth analog voltage is calculated according to:
<mrow> <msub> <mi>V</mi> <mn>5</mn> </msub> <mo>=</mo> <mi>V</mi> <mi>c</mi> <mi>c</mi> <mo>*</mo> <mrow> <mo>(</mo> <mfrac> <mrow> <mi>R</mi> <mn>5</mn> </mrow> <mrow> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>1</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>2</mn> </mrow> </mfrac> </mrow> </mfrac> <mo>+</mo> <mi>R</mi> <mn>5</mn> </mrow> </mfrac> <mo>)</mo> </mrow> </mrow>
wherein, V5Is the fifth analog voltage, VccIs the supply voltage.
6. The multi-switch signal AD processing circuit of claim 5, wherein when the first switch S1 in the first switch circuit, the second switch S2 in the second switch circuit, the third switch S3 in the third switch circuit are closed, and the fourth switch S4 in the fourth switch circuit is open, a sixth analog voltage is calculated according to the following equation:
<mrow> <msub> <mi>V</mi> <mn>6</mn> </msub> <mo>=</mo> <mi>V</mi> <mi>c</mi> <mi>c</mi> <mo>*</mo> <mrow> <mo>(</mo> <mfrac> <mrow> <mi>R</mi> <mn>5</mn> </mrow> <mrow> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>1</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>2</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>3</mn> </mrow> </mfrac> </mrow> </mfrac> <mo>+</mo> <mi>R</mi> <mn>5</mn> </mrow> </mfrac> <mo>)</mo> </mrow> </mrow>
wherein, V6Is the sixth analog voltage, VccIs the supply voltage.
7. The AD processing circuit for multiple switching signals according to claim 3, wherein the plurality of switching circuits are a fifth switching circuit, a sixth switching circuit, a seventh switching circuit, and an eighth switching circuit, respectively;
when the fifth switch S5 in the fifth switch circuit is closed and the sixth switch S6 in the sixth switch circuit, the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are open, a seventh analog voltage is calculated according to the following equation:
V7＝Vcc*(R6/(R10+R6))
wherein, V7Is the seventh analog voltage, VccIs the supply voltage;
or,
when the sixth switch S6 in the sixth switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the seventh switch S7 in the seventh switch circuit and the eighth switch S8 in the eighth switch circuit are open, an eighth analog voltage is calculated according to the following equation:
V8＝Vcc*(R7/(R10+R7))
wherein, V8Is the eighth analog voltage, VccIs the supply voltage;
or,
when a seventh switch S7 in the seventh switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit and the eighth switch S8 in the eighth switch circuit are open, a ninth analog voltage is calculated according to the following equation:
V9＝Vcc*(R8/(R10+R8))
wherein, V9Is the ninth analog voltage, VccIs the supply voltage;
or,
when an eighth switch S8 in the eighth switch circuit is closed and the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit and the seventh switch S7 in the seventh switch circuit are open, a tenth analog voltage is calculated according to the following equation:
V10＝Vcc*(R9/(R10+R9))
wherein, V10Is the tenth analog voltage, VccIs the supply voltage.
8. The multiple switching signal AD processing circuit of claim 7, wherein when the fifth switch S5 in the fifth switching circuit and the sixth switch S6 in the sixth switching circuit are closed, and the seventh switch S7 in the seventh switching circuit and the eighth switch S8 in the eighth switching circuit are open, an eleventh analog voltage is calculated according to:
<mrow> <msub> <mi>V</mi> <mn>11</mn> </msub> <mo>=</mo> <mi>V</mi> <mi>c</mi> <mi>c</mi> <mo>*</mo> <mrow> <mo>(</mo> <mfrac> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>6</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>7</mn> </mrow> </mfrac> </mrow> </mfrac> <mrow> <mi>R</mi> <mn>10</mn> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>6</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>7</mn> </mrow> </mfrac> </mrow> </mfrac> </mrow> </mfrac> <mo>)</mo> </mrow> </mrow>
wherein, V11Is the eleventh analog voltage, VccIs the supply voltage.
9. The multiple switching signal AD processing circuit of claim 8, wherein when the fifth switch S5 in the fifth switch circuit, the sixth switch S6 in the sixth switch circuit, the seventh switch S7 in the seventh switch circuit are closed, and the eighth switch S8 in the eighth switch circuit is opened, a twelfth analog voltage is calculated according to:
<mrow> <msub> <mi>V</mi> <mn>12</mn> </msub> <mo>=</mo> <mi>V</mi> <mi>c</mi> <mi>c</mi> <mo>*</mo> <mrow> <mo>(</mo> <mfrac> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>6</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>7</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>8</mn> </mrow> </mfrac> </mrow> </mfrac> <mrow> <mi>R</mi> <mn>10</mn> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>6</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>7</mn> </mrow> </mfrac> <mo>+</mo> <mfrac> <mn>1</mn> <mrow> <mi>R</mi> <mn>8</mn> </mrow> </mfrac> </mrow> </mfrac> </mrow> </mfrac> <mo>)</mo> </mrow> </mrow>
wherein, V12Is the twelfth analog voltage, VccIs the supply voltage.
10. An electric vehicle comprising the AD processing circuit for the multiple switching signal according to any one of claims 1 to 9.
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