CN114268516B - Slave station address detection device and slave station equipment - Google Patents
Slave station address detection device and slave station equipment Download PDFInfo
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Abstract
The invention discloses a slave station address detection device and slave station equipment, which comprise a processor of a slave station, N groups of A first row pins, N groups of A second row pins, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and N is a positive integer which is not more than 10; the processor sequentially outputs a first detection level to a jth ten-bit detection signal input end, detects a 1 st signal detection end to an A-th signal detection end, and determines a ten-bit numerical value based on the signal detection end outputting the first detection level; and a second detection level is sequentially output to the kth bit detection signal input end, the 1 st signal detection end is detected to the A signal detection end, a bit value is determined based on the signal detection end outputting the second detection level, a dial switch and a knob switch are not required to be arranged, the cost is reduced, in addition, the address of the slave station can be determined only by detecting 2N + A detection signals, and the signal detection amount is relatively small.
Description
Technical Field
The present invention relates to the field of signal detection, and in particular, to a slave station address detection apparatus and a slave station device.
Background
The field bus control system comprises a master station and a plurality of slave stations, when the master station sends a signal needing to communicate with the slave station with a certain address, the slave stations can detect the addresses of the slave stations through own processors, and if the addresses of the slave stations are consistent with the addresses of the slave stations which the master station requires to communicate, the slave stations can realize the communication with the master station. In the prior art, the slave station processor detects the slave station address by detecting the state of the dial switch or the rotary switch, but the cost of the dial switch or the rotary switch is relatively high. In addition, when 100 kinds of addresses of the slave station need to be detected, the processor needs to detect 20 detection signals of 2 dial switches with 10 bits, and the detection signal quantity is large.
Disclosure of Invention
The invention aims to provide a slave station address detection device and a slave station device, which do not need to be provided with a dial switch and a knob switch, reduce the cost and have relatively small signal detection amount.
In order to solve the technical problem, the invention provides a slave station address detection device which comprises a processor of a slave station, N groups of A first row pins, N groups of A second row pins, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and NA is a positive integer which is not more than 10, the first short circuit cap is arranged on one first row pin, and the second short circuit cap is arranged on one second row pin; the first row of pins represents a tens value and the second row of pins represents a units value;
the first end of the ith first row of pins is connected with the first end of the ith second row of pins, and the connected common end is used as an ith signal detection end, the ith signal detection ends in each group are connected, the second end of the jth group A of first row of pins is connected with the connected common end as a jth ten-bit detection signal input end, the second end of the kth group A of second row of pins is connected with the connected common end as a kth bit detection signal input end, i is more than or equal to 1 and less than or equal to A, j is more than or equal to 1 and less than or equal to K, and k is less than or equal to N;
the processor is used for sequentially outputting a first detection level to a jth ten-bit detection signal input end, detecting a 1 st signal detection end to an A-th signal detection end and determining a ten-bit numerical value based on the signal detection end outputting the first detection level; sequentially outputting a second detection level to a kth unit detection signal input end and detecting a 1 st signal detection end to an A signal detection end, determining a unit number value based on the signal detection end outputting the second detection level, and determining the address of the slave station according to the determined tens number value and the unit number value; the first detection level and the second detection level are the same.
Preferably, N =2,a =5.
Preferably, the processor is specifically configured to output a first detection level to the 1 st ten-bit detection signal input end and detect the 1 st signal detection end to the 5 th signal detection end, and if it is detected that one of the 1 st signal detection end to the 5 th signal detection end outputs a signal of the first detection level, determine a ten-bit value based on the signal detection end outputting the first detection level;
if the signal of the first detection level is not detected to be output by one of the 1 st signal detection end to the 5 th signal detection end, outputting a first detection level to the 2 nd tenth detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if the signal of the first detection level is output by one of the 1 st signal detection end to the 5 th signal detection end, determining a ten-bit value based on the signal detection end outputting the first detection level;
outputting a second detection level to the 1 st bit detection signal input terminal and detecting the 1 st signal detection terminal to the 5 th signal detection terminal, and if one of the 1 st signal detection terminal to the 5 th signal detection terminal is detected to output a signal of the second detection level, determining a bit value based on the signal detection terminal outputting the second detection level;
if the signal of the second detection level is not detected to be output by one of the 1 st signal detection end to the 5 th signal detection end, outputting a second detection level to the 2 nd bit detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if the signal of the second detection level is output by one of the 1 st signal detection end to the 5 th signal detection end, determining a bit value based on the signal detection end outputting the second detection level;
and determining the address of the slave station according to the determined ten-bit numerical value and the determined one-bit numerical value.
Preferably, the first detection level and the second detection level are both high levels.
Preferably, the system further comprises a prompting module, configured to prompt the determined address of the slave station.
In order to solve the technical problem, the invention further provides the slave station equipment, which comprises the slave station address detection device.
The invention discloses a slave station address detection device and slave station equipment, which comprise a processor of a slave station, N groups of A first row pins, N groups of A second row pins, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and N is a positive integer which is not more than 10; the processor sequentially outputs a first detection level to a jth ten-bit detection signal input end, detects a 1 st signal detection end to an A-th signal detection end, and determines a ten-bit numerical value based on the signal detection end outputting the first detection level; the second detection level is sequentially output to the kth unit detection signal input end, the 1 st signal detection end is detected to the A signal detection end, the unit number value is determined based on the signal detection end outputting the second detection level, the address of the slave station is determined according to the determined tens number value and the unit number value, the slave station can realize communication with the master station when the address of the slave station is consistent with the address of the slave station requiring communication of the master station, a dial switch and a knob switch are not needed, and cost is reduced. In addition, the address of the slave station can be determined only by 2N + A detection signals, and the signal detection amount is relatively small.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a slave station address detection apparatus provided in the present invention;
fig. 2 is a schematic diagram of an operating principle of a slave station address detection apparatus according to the present invention.
Detailed Description
The core of the invention is to provide a slave station address detection device and a slave station device, a dial switch and a knob switch are not needed, the cost is reduced, and the signal detection amount is relatively small.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a slave station address detection apparatus provided in the present application.
The invention provides a slave station address detection device which comprises a processor 1 of a slave station, N groups of A first row pins 2, N groups of A second row pins 3, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and N is a positive integer which is not more than 10, the first short circuit cap is arranged on one first row pin 2, and the second short circuit cap is arranged on one second row pin 3; the first row of pins 2 represents tens numerical value, and the second row of pins 3 represents units numerical value;
the first end of the ith first row of pins 2 is connected with the first end of the ith second row of pins 3, the connected public end is used as an ith signal detection end, the ith signal detection ends in each group are connected, the second end of the jth group A of first row of pins 2 is connected with the connected public end and is used as a jth ten-bit detection signal input end, the second end of the kth group A of second row of pins 3 is connected with the connected public end and is used as a kth bit detection signal input end, i is more than or equal to 1 and less than or equal to A, j is more than or equal to 1 and less than or equal to N, and k is less than or equal to N;
the processor 1 is used for sequentially outputting a first detection level to a jth ten-bit detection signal input end, detecting a 1 st signal detection end to an A-th signal detection end and determining a ten-bit numerical value based on the signal detection end outputting the first detection level; sequentially outputting a second detection level to a kth unit detection signal input end and detecting a 1 st signal detection end to an A signal detection end, determining a unit number value based on the signal detection end outputting the second detection level, and determining the address of a slave station according to the determined tens number value and the unit number value; the first detection level and the second detection level are the same.
In the field bus control system, in order to realize the communication between the master station and the slave station, an address needs to be set for the slave station, when the master station sends out a communication signal, the processor 1 of the slave station detects the address set by the slave station, so that the communication with the master station is realized when the address of the slave station is consistent with the address required by the master station to communicate. In the prior art, addresses are set for the slave stations through dial switches or knob switches, cost is relatively high, in addition, when the processor 1 of the slave station detects the addresses of the slave stations, states of each bit of the dial switches or the knob switches need to be detected, and detection signal quantity is relatively large.
In order to solve the technical problem, in the application, the slave station address detection device comprises a processor 1 of a slave station, N groups of A first row pins 2, N groups of A second row pins 3, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and NA are positive integers which are not more than 10, the first short circuit cap is arranged on one first row pin 2, and the second short circuit cap is arranged on one second row pin 3; the first row of pins 2 represents the tens value and the second row of pins 3 represents the units value. The processor 1 sequentially outputs a first detection level to a jth ten-bit detection signal input end and detects a 1 st signal detection end to an A-th signal detection end, and the ten-bit values corresponding to each of the 1 st signal detection end to the A-th signal detection end are different, so that the ten-bit values can be determined based on the signal detection end outputting the first detection level. The processor 1 also sequentially outputs a second detection level to a kth bit detection signal input end and detects a 1 st signal detection end to an A signal detection end, bit values corresponding to each of the 1 st signal detection end to the A signal detection end are different, so that the bit values can be determined based on the signal detection end outputting the second detection level, the first detection level and the second detection level are the same, the first detection level and the second detection level can be simultaneously high level and low level, and finally, the address of the slave station is determined according to the determined ten bit values and the bit values, so that the slave station can realize communication with the master station when the address of the slave station is consistent with the address of the slave station requiring communication of the master station according to the address of the slave station. Therefore, the processor 1 determines the address of the slave station by inputting the detection level signal to the detection signal input end connected by the pin header and detecting the output signal detection level of the common end connected by the pin header as the signal detection end, so that the flexibility of the whole detection device is high, and the signal detection end can realize multiplexing.
In conclusion, the slave station address detection device does not need to be provided with a dial switch and a knob switch, so that the cost is reduced, the address of the slave station can be determined only by 2N + A detection signals, and the signal detection amount is relatively small.
On the basis of the above-described embodiment:
referring to fig. 2, fig. 2 is a schematic diagram illustrating an operating principle of a slave address detection apparatus according to the present application.
As a preferred embodiment, N =2,a =5.
In view of the fact that 20 detection signals of two 10-bit dial switches or knob switches are usually used for detecting 100 addresses of the slave station, which has relatively high cost and increases the complexity of signal detection, in this embodiment, 2 sets of 5 first pins 2, 2 sets of 5 second pins 3, a first short-circuit cap and a second short-circuit cap are used to solve the above technical problem, where the first short-circuit cap is disposed on one first pin 2, the second short-circuit cap is disposed on one second pin 3, the first pin 2 represents a tens value, and the second pin 3 represents a units value. When detecting the address of the slave station, the processor 1 of the slave station can output the signal detection end of the first detection level to determine the ten-digit numerical value by sequentially outputting the first detection level to the jth ten-digit detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end. Processor 1 also will output a second detection level to kth detection signal input end and detect the 1 st signal detection end to the 5 th signal detection end in proper order, the unit number value is confirmed based on the signal detection end that outputs the second detection level, can confirm the address of slave station according to ten bit number values and unit number value confirmed finally, therefore, the scheme of this embodiment need not set up dial switch or knob switch, the cost is relatively low, and processor 1 only needs to detect 9 detection signals and can confirm the address of slave station, the signal detection volume is relatively less.
As a preferred embodiment, the processor 1 is specifically configured to output a first detection level to the 1 st ten-bit detection signal input terminal and detect the 1 st signal detection terminal to the 5 th signal detection terminal, and if it is detected that one of the 1 st signal detection terminal to the 5 th signal detection terminal outputs a signal of the first detection level, determine a ten-bit value based on the signal detection terminal outputting the first detection level;
if one of the 1 st signal detection end to the 5 th signal detection end is not detected to output a signal of a first detection level, outputting the signal of the first detection level to a 2 nd tenth detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if one of the 1 st signal detection end to the 5 th signal detection end is detected to output the signal of the first detection level, determining a ten-digit numerical value based on the signal detection end outputting the first detection level;
outputting a second detection level to the 1 st bit detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if one of the 1 st signal detection end to the 5 th signal detection end is detected to output a signal of the second detection level, determining a bit value based on the signal detection end outputting the second detection level;
if the signal of the second detection level is not detected to be output by one of the 1 st signal detection end to the 5 th signal detection end, outputting the second detection level to the 2 nd bit detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if the signal of the second detection level is output by one of the 1 st signal detection end to the 5 th signal detection end, determining a bit value based on the signal detection end outputting the second detection level;
and determining the address of the slave station according to the determined ten-bit numerical value and the determined one-bit numerical value.
In this embodiment, the processor 1 may specifically output a first detection level to the 1 st ten-bit detection signal input end COM1, and may detect the 1 st signal detection end No.1 to the 5 th signal detection end No.5, and if it is detected that one of the 1 st signal detection end to the 5 th signal detection end outputs a signal of the first detection level, the ten-bit value of the slave station address may be determined based on the ten-bit value corresponding to the signal detection end outputting the first detection level; if the signal detection end from the 1 st signal detection end to the 5 th signal detection end outputs the signal of the first detection level is not detected, the first detection level to the 2 nd tenth detection signal input end COM2 and the signals from the 1 st signal detection end to the 5 th signal detection end COM 5 are output, and if the signal detection end from the 1 st signal detection end to the 5 th signal detection end outputs the signal of the first detection level, the tenth value is determined based on the signal detection end outputting the first detection level. The processor 1 will output a second detection level to the 1 st bit detection signal input end COM3 and detect the 1 st signal detection end No.1 to the 5 th signal detection end No.5, if it is detected that one of the 1 st signal detection end to the 5 th signal detection end outputs a signal of the second detection level, the bit value can be determined based on the signal detection end outputting the second detection level; if one of the 1 st signal detection end No.1 to the 5 th signal detection end No.5 is not detected to output a signal of a second detection level, outputting the second detection level to the 2 nd signal detection signal input end COM4 and detecting the 1 st signal detection end No.1 to the 5 th signal detection end No.5, if one of the 1 st signal detection end No.1 to the 5 th signal detection end No.5 is detected to output a signal of the second detection level, determining a unit number value based on the signal detection end outputting the second detection level, and finally determining an address of a slave station according to the determined tens number value and the unit number value, so that the detection of the address of the slave station is convenient and quick.
As a preferred embodiment, the first detection level and the second detection level are both high.
In this embodiment, both the first detection level and the second detection level may be at a high level, specifically, the processor 1 first outputs a high level to the 1 st tens detection signal input end COM1, and outputs a low level to COM2, COM3, and COM4, and detects the 1 st through 5 th signal detection ends No.1 through 5, and if it is detected that one of the 1 st through 5 th signal detection ends outputs a high level signal, for example, the 1 st signal detection end No.1 outputs a high level signal, and the levels detected by nos. 2, 3, 4, and 5 are at a low level, it may determine that the tens value is 0 based on the tens value of the slave station address corresponding to the 1 st signal detection end No. 1. Similarly, if the 2 nd signal detection terminal No.2 outputs a high-level signal and the levels detected by nos. 1, 3, 4, and 5 are low, it is possible to determine that the tens value is 1 based on the tens value of the slave station address corresponding to the 2 nd signal detection terminal No. 2. The situation that the signal detection terminal 3, 4 or 5 outputs a high-level signal can be analogized, and the detailed description of the application is omitted.
If it is not detected that one of the 1 st to 5 th signal detection terminals outputs a high-level signal, the processor 1 outputs a high-level signal to the 2 nd tenth detection signal input terminal COM2, outputs a low-level signal to COM1, COM3, COM4, and detects the 1 st to 5 th signal detection terminals No.1 to 5, and if it is detected that one of the 1 st to 5 th signal detection terminals outputs a high-level signal, for example, the 1 st signal detection terminal No.1 outputs a high-level signal, and the 1 st signal detection terminal No.2, no.3, no.4, no.5 detects a low-level signal, it is possible to determine that the slave station has a ten-digit value of 5 based on the ten-digit value of the address corresponding to the 1 st signal detection terminal No. 1. Similarly, if the 2 nd signal detection terminal No.2 outputs a high-level signal and the levels detected by nos. 1, 3, 4, and 5 are low, the tens value can be determined to be 6 based on the tens value of the slave station address corresponding to the 2 nd signal detection terminal No. 2. The situation that the signal detection terminal 3, 4 or 5 outputs a high-level signal can be analogized, and the detailed description of the application is omitted.
The processor 1 outputs a high level to the 1 st bit detection signal input terminal COM3, outputs a low level to the COM1, COM2, COM4, and detects the 1 st to 5 th signal detection terminals No.1 to No.5, and if it is detected that one of the 1 st to 5 th signal detection terminals outputs a high level signal, for example, the 1 st signal detection terminal No.1 outputs a high level signal, and the levels detected by nos. 2, no.3, no.4, no.5 are low levels, it may determine that the bit value is 0 based on the bit value of the slave station address corresponding to the 1 st signal detection terminal No. 1. Similarly, if the 2 nd signal detection end No.2 outputs a high-level signal and the levels detected by nos. 1, 3, 4, and 5 are low, the bit value can be determined to be 1 based on the bit value of the slave station address corresponding to the 2 nd signal detection end No. 2. The situation that the signal detection terminal 3, 4 or 5 outputs a high-level signal can be analogized, and the detailed description of the application is omitted.
If one of the 1 st signal detection end to the 5 th signal detection end is not detected to output a high level signal, the processor 1 outputs a high level signal to the 2 nd signal detection signal input end COM4, outputs a low level signal to COM1, COM2, COM3, and detects the 1 st signal detection end No.1 to the 5 th signal detection end No.5, and if one of the 1 st signal detection end to the 5 th signal detection end is detected to output a high level signal, for example, the 1 st signal detection end No.1 outputs a high level signal, and the levels detected by nos. 2, 3, 4, and 5 are low, the unit value of the slave station is determined to be 5 based on the unit value of the address corresponding to the 1 st signal detection end No. 1. Similarly, if the 2 nd signal detection end No.2 outputs a high level signal and the levels detected by nos. 1, 3, 4 and 5 are low levels, the bit value can be determined to be 6 based on the bit value of the slave station address corresponding to the 2 nd signal detection end No. 2. The situation that the 3 rd or 4 th or 5 th signal detection end outputs a high-level signal can be analogized, and the description is omitted here, and finally the address of the slave station can be determined according to the determined ten-digit numerical value and the determined one-digit numerical value, so that the flexibility is strong, and the signal detection amount is relatively small.
As a preferred embodiment, the system further comprises a prompting module, configured to prompt the determined address of the slave station.
In order to facilitate the more intuitive checking of the address of the slave station, in this embodiment, the slave station address detection device further includes a prompt module, which can prompt the determined address of the slave station, so that the practicability is higher.
The invention also provides slave station equipment which comprises the slave station address detection device.
For introducing the slave station device provided by the present invention, please refer to the above method embodiment, and the present invention is not described herein again.
It is to be noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (6)
1. A slave station address detection device is characterized by comprising a slave station processor, N groups of A first row pins, N groups of A second row pins, a first short circuit cap and a second short circuit cap, wherein N is more than or equal to 1 and less than or equal to 2, A is more than 2 and less than 10, and N A is a positive integer which is not more than 10; the first row of pins represents a tens value and the second row of pins represents a units value;
the first end of the ith first row of pins is connected with the first end of the ith second row of pins, and the connected public end is used as an ith signal detection end, the ith signal detection ends in each group are connected, the second end of the jth group A of first row of pins is connected with the connected public end and is used as a jth ten-bit detection signal input end, the second end of the kth group A of second row of pins is connected with the connected public end and is used as a kth bit detection signal input end, i is more than or equal to 1 and less than or equal to A, j is more than or equal to 1 and k is less than or equal to N;
the processor is used for sequentially outputting a first detection level to a jth ten-bit detection signal input end, detecting a 1 st signal detection end to an A-th signal detection end and determining a ten-bit numerical value based on the signal detection end outputting the first detection level; sequentially outputting a second detection level to a kth unit detection signal input end and detecting a 1 st signal detection end to an A signal detection end, determining a unit number value based on the signal detection end outputting the second detection level, and determining the address of the slave station according to the determined tens number value and the unit number value; the first detection level and the second detection level are the same.
2. A slave address detection apparatus as claimed in claim 1, wherein N =2,a =5.
3. The slave address detecting apparatus of claim 2, wherein the processor is specifically configured to output a first detection level to the 1 st ten-bit detection signal input terminal and detect the 1 st signal detection terminal to the 5 th signal detection terminal, and if it is detected that one of the 1 st signal detection terminal to the 5 th signal detection terminal outputs the signal of the first detection level, determine a ten-bit value based on the signal detection terminal outputting the first detection level;
if the signal of the first detection level is not detected to be output by one of the 1 st signal detection end to the 5 th signal detection end, outputting a first detection level to the 2 nd tenth detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if the signal of the first detection level is output by one of the 1 st signal detection end to the 5 th signal detection end, determining a ten-bit value based on the signal detection end outputting the first detection level;
outputting a second detection level to the 1 st bit detection signal input terminal and detecting the 1 st signal detection terminal to the 5 th signal detection terminal, and if one of the 1 st signal detection terminal to the 5 th signal detection terminal is detected to output a signal of the second detection level, determining a bit value based on the signal detection terminal outputting the second detection level;
if the signal of the second detection level is not detected to be output by one of the 1 st signal detection end to the 5 th signal detection end, outputting a second detection level to the 2 nd bit detection signal input end and detecting the 1 st signal detection end to the 5 th signal detection end, and if the signal of the second detection level is output by one of the 1 st signal detection end to the 5 th signal detection end, determining a bit value based on the signal detection end outputting the second detection level;
and determining the address of the slave station according to the determined tens numerical value and units numerical value.
4. A secondary station address detection apparatus as claimed in claim 3, characterised in that the first detection level and the second detection level are both high levels.
5. A secondary station address detection apparatus as claimed in any one of claims 1 to 4, further comprising a prompt module for prompting for the determined address of the secondary station.
6. A slave device comprising a slave address detection means as claimed in any of claims 1 to 5.
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| CN101813935A (en) * | 2010-03-17 | 2010-08-25 | 南京航空航天大学 | Non-polar field bus system and realization method |
| CN101976074A (en) * | 2010-11-03 | 2011-02-16 | 浙江工业大学 | Industrial control system based on field bus and control network |
| CN107734082A (en) * | 2017-10-23 | 2018-02-23 | 顺丰科技有限公司 | A kind of address distribution method and system |
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