CN214954644U - Detection circuit and energy storage inverter of DRED controller - Google Patents
Detection circuit and energy storage inverter of DRED controller Download PDFInfo
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- CN214954644U CN214954644U CN202121699108.6U CN202121699108U CN214954644U CN 214954644 U CN214954644 U CN 214954644U CN 202121699108 U CN202121699108 U CN 202121699108U CN 214954644 U CN214954644 U CN 214954644U
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Abstract
The utility model discloses a detection circuitry and energy storage inverter of DRED controller. A detection circuit for a DRED controller, comprising a controller, the detection circuit further comprising: a first communication line, a second communication line, a third communication line, a fourth communication line, and a fifth communication line; the detection circuit comprises a first detection resistor, a second detection resistor, a third detection resistor, a fourth detection resistor and a fifth detection resistor. The detection circuit has the advantages of less quantity of used electronic components, simple circuit structure, simple and clear logic, simplicity and convenience in operation, easiness in realization, capability of reducing cost, reducing occupied space and optimizing product volume.
Description
Technical Field
The utility model belongs to the inverter field relates to a detection circuitry and energy storage inverter of DRED controller.
Background
The latest safety standard "AS NZS 4777.2-2015" for australian and new zealand grid-connected photovoltaic inverters and energy-storage photovoltaic inverters was published by the grid company in australia in 2016. And requires that all photovoltaic inverters sold to australia and new zealand after 2016, 7 th of the middle of the month must comply with the latest safety regulations. DRMs (Demand Response models) are newly added in the safety standard of AS NZS 4777.2-2015): an external control box, namely a DRED (Demand Response Enabling Device) interface is used for transmitting commands so as to control the input and the output of the energy storage inverter.
The existing DRED detection circuit mainly comprises 8-3 encoders, an MCU (microprogrammed control unit), an operational amplifier, a detection resistor and other devices, six or eight communication lines are used for detecting the closed states of ten controlled switches, but the DRED has various controlled switch states, and the specific state of each controlled switch cannot be accurately detected; meanwhile, the circuit is complex, the volume is large, and the cost is high.
SUMMERY OF THE UTILITY MODEL
In order to solve the above technical problem, an object of the present invention is to provide a detection circuit for a DRED controller, which can accurately detect a controlled switch of the DRED controller by using fewer devices and simpler logic.
Another object of the present invention is to provide an energy storage inverter, which can realize accurate detection of the controlled switch of the DRED controller with fewer devices and simpler logic.
In order to achieve the above object, the utility model discloses a technical scheme do:
a detection circuit of a DRED controller, comprising a controller, the detection circuit further comprising:
a first communication line having one end connected to the first input port of the controller and the other end for connecting intermediate nodes of the controlled switches S1 and S5 of the DRED controller;
a second communication line having one end connected to the second input port of the controller and the other end for connecting to intermediate nodes of the controlled switches S2 and S6 of the DRED controller;
a third communication line having one end connected to the third input port of the controller and the other end for connecting to the middle nodes of the controlled switches S3 and S7 of the DRED controller;
a fourth communication line, one end of which is connected to the fourth input port of the controller, and the other end of which is used for connecting the middle nodes of the controlled switches S4 and S8 of the DRED controller;
a fifth communication line having one end connected to the fifth input port of the controller and the other end for being grounded through the controlled switches S9 and S0 of the DRED circuit;
one end of the first detection resistor is connected with a power supply, and the other end of the first detection resistor is connected with the first communication line;
one end of the second detection resistor is connected with the power supply, and the other end of the second detection resistor is connected with the second communication line;
one end of the third detection resistor is connected with the power supply, and the other end of the third detection resistor is connected with the third communication line;
one end of the fourth detection resistor is connected with the power supply, and the other end of the fourth detection resistor is connected with the fourth communication line; and
and one end of the fifth detection resistor is connected with the power supply, and the other end of the fifth detection resistor is connected with the fifth communication line.
In a preferred embodiment, the controller is an MCU chip, and the first input port, the second input port, the third input port, the fourth input port, and the fifth input port are AD ports of the MCU chip, respectively.
In a preferred embodiment, the detection circuit further comprises:
a signal sampling terminal DRM1/5 connected to the first input port and to the first communication line;
a signal sampling terminal DRM2/6 connected to the second input port and to the second communication line;
a signal sampling terminal DRM3/7 connected to the third input port and to the third communication line;
a signal sampling terminal DRM4/8 connected to the fourth input port and to the fourth communication line;
a signal sampling terminal COM LOAD connected to the fifth input port and connected to the fifth communication line;
the signal sampling terminal DRM1/5, the signal sampling terminal DRM2/6, the signal sampling terminal DRM3/7, the signal sampling terminal DRM4/8, and the signal sampling terminal COM LOAD are respectively configured to sample a voltage signal and output a sampled signal to the first input port, the second input port, the third input port, the fourth input port, and the fifth input port.
The utility model discloses still adopt following technical scheme:
an energy storage inverter comprises an inverter circuit and a detection circuit, wherein the controller is used for controlling the input and the output of the inverter circuit according to the detection result.
The utility model adopts the above scheme, compare prior art and have following advantage:
the utility model provides a detection circuitry and energy storage inverter of DRED controller, detection circuitry includes the controller, the controller self has five input ports, can use five communication lines to be connected controlled switch and five input ports respectively, so that every AD port can discern the level of the voltage sampling signal of input, thereby detect each controlled switch S0 to S9' S on-off state, the electronic components quantity that detection circuitry used is less, circuit structure is simple, therefore it is less to occupy the volume, be applicable to in the family uses the energy storage inverter; the energy storage inverter has the advantages that the number of electronic components is small, the cost can be reduced, the space occupied by the system is reduced, and the product volume is optimized.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a detection circuit diagram of a DRED controller according to an embodiment;
FIG. 2 is a circuit diagram of an energy storage inverter of an embodiment;
FIG. 3 is a diagram illustrating the correspondence between the detected values and the states of the controlled switches;
fig. 4 is a schematic diagram of the correspondence between the detected values and the failure conditions of the controlled switches.
1. A first input port; 2. a second input port; 3. a third input port; 4. a fourth input port; 5. a fifth input port; 6. a first communication line; 7. a second communication line; 8. a third communication line; 9. a fourth communication line; 10. a fifth communication line; 11. an MCU chip; 12. an inverter circuit.
Detailed Description
The following detailed description of the preferred embodiments of the invention, taken in conjunction with the accompanying drawings, enables the advantages and features of the invention to be more readily understood by those skilled in the art. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto.
Referring to fig. 1, the DRED circuit of the DRED controller includes ten controlled switches S0-S9, wherein the controlled switches S1 and S5 are connected in series to form a first branch, S2 and S6 are connected in series to form a second branch, S3 and S7 are connected in series to form a third branch, S4 and S8 are connected in series to form a fourth branch, the resistor R0 forms a fifth branch, and the five branches are connected in parallel. The method specifically comprises the following steps: one ends of S1, S2, S3 and S4 are connected in parallel, one ends of S5, S6, S7 and S8 are connected in parallel, and the parallel ends are grounded. One end of the controlled switch S9 is connected to the parallel end of S1, S2, S3 and S4. One end of the controlled switch S0 is grounded, and the other end is connected to the intermediate node between the parallel ends of the controlled switch S9 and the controlled switches S1, S2, S3, and S4.
The embodiment provides a detection circuit for the DRED controller. As shown in fig. 1, the detection circuit includes a controller. Specifically, in this embodiment, the controller specifically includes an MCU chip 11, where the MCU chip 11 has at least five AD ports, which are in turn: a first input port 1, a second input port 2, a third input port 3, a fourth input port 4 and a fifth input port 5. The detection circuit further comprises a first communication line 6, a second communication line 7, a third communication line 8, a fourth communication line 9 and a fifth communication line 10. One end of the first communication line 6 is connected with the first input port 1 of the MCU chip 11, and the other end is connected with the intermediate nodes of the controlled switches S1 and S5 of the DRED circuit; one end of the second communication line 7 is connected with the second input port 2 of the MCU chip 11, and the other end is connected with the middle nodes of the controlled switches S2 and S6 of the DRED circuit; one end of the third communication line 8 is connected with the third input port 3 of the MCU chip 11, and the other end is connected with the middle nodes of the controlled switches S3 and S7 of the DRED circuit; one end of the fourth communication line 9 is connected with the fourth input port 4 of the MCU chip 11, and the other end is connected with the middle nodes of the controlled switches S4 and S8 of the DRED circuit; one end of the fifth communication line 10 is connected to the fifth input port 5 of the MCU chip 11, the other end is connected to the controlled switch S9 of the DRED circuit, and the other end of the controlled switch S9 is connected to the parallel terminals of the controlled switches S1 to S4, and may be grounded through the controlled switch S0.
The control circuit further comprises a first detection resistor R1, a second detection resistor R2, a third detection resistor R3, a fourth detection resistor R4 and a fifth detection resistor R5. One end of the first detection resistor R1 is connected to the first communication line 6, one end of the second detection resistor R2 is connected to the second communication line 7, one end of the third detection resistor R3 is connected to the third communication line 8, one end of the fourth detection resistor R4 is connected to the fourth communication line 9, and one end of the fifth detection resistor R5 is connected to the fifth communication line 10. The other ends of the first detection resistor R1, the second detection resistor R2, the third detection resistor R3, the fourth detection resistor R4 and the fifth detection resistor R5 are respectively connected with a power supply Vcc.
The detection circuit further includes: a signal sampling terminal DRM1/5 connected to the first input port 1 and to the first communication line 6; a signal sampling terminal DRM2/6 connected to the second input port 2 and to the second communication line 7; a signal sampling terminal DRM3/7 connected to the third input port 3 and to the third communication line 8; a signal sampling terminal DRM4/8 connected to the fourth input port 4 and to the fourth communication line 9; a signal sampling terminal COM LOAD connected to the fifth input port 5 and to the fifth communication line 10; the sampling signal terminals are respectively used for sampling the voltage signal and respectively outputting the sampling signal to the first input port 1, the second input port 2, the third input port 3, the fourth input port 4 and the fifth input port 5. The MCU chip 11 can recognize the levels of the voltage sampling signals input from the first input port 1, the second input port 2, the third input port 3, the fourth input port 4, and the fifth input port 5, and determine the switching states of the controlled switches S0 to S9 of the DRED controller according to the levels of the voltage sampling signals. The levels of three voltage sampling signals can be obtained at the five AD ports respectively: vcc, 0V and Vm, Vm is a range voltage value with a large distinction from Vcc and 0V and a small interval. It is understood that the magnitude relationships of Vcc, 0V and Vm are: vcc > Vm > 0. Specifically, in the embodiment, the voltage provided by the power supply Vcc is 3.3V, and Vm is 1.9-2.13V.
The present embodiment further provides a detection method for a DRED controller, which uses the detection circuit as described above, and uses the first input port 1, the second input port 2, the third input port 3, the fourth input port 4, and the fifth input port 5 of the MCU chip 11 to identify the level of the voltage sampling signal input to each port, and determines the switching states of the controlled switches S0 to S9 of the DRED controller according to the level of each voltage sampling signal. Each of the input ports is an AD port of the MCU chip 11 itself. The levels of three voltage sampling signals can be obtained at the five AD ports respectively: vcc, 0V and Vm.
The level of the first input port 1 corresponds to the controlled switches S1 and S5, the level of the second input port 2 corresponds to the controlled switches S2 and S6, the level of the third input port 3 corresponds to the controlled switches S3 and S7, and the level of the fourth input port 4 corresponds to the controlled switches S4 and S8;
as shown in fig. 3 and 4, the normal operation state and the abnormal operation state of the controlled switch can be detected by identifying the levels of the voltage sampling signals of the five AD ports; the specific conditions of each controlled switch can be detected when the controlled switch is in a normal working state; and the specific condition of each controlled switch when the controlled switch is in an abnormal working state. Fig. 3 is a corresponding relationship between the input value of each AD port and the state of each controlled switch when each controlled switch is in a normal operating state, where "1" in the controlled switch column indicates that the switch is on, and "0" indicates that the switch is off; the "2" of the AD port column indicates that the level signal received by the port is Vcc, the "1" indicates that the level signal received by the port is Vm, and the "0" indicates that the level signal received by the port is 0V. Fig. 4 is a specific relationship between input values of the AD ports and the fault condition of the controlled switch when the controlled switch is in an abnormal operating state, where "1" in the controlled switch column indicates that the switch is on, "0" indicates that the switch is off, and "/" indicates that the switch is connected abnormally; in the AD port column, "2" indicates that the level signal received by the port is Vcc, "1" indicates that the level signal received by the port is Vm, "0" indicates that the level signal received by the port is 0V, and "/" indicates that the signal received by the port is an arbitrary level signal.
Referring to fig. 3, the detection method for detecting the normal operating state of the controlled switch comprises the following implementation steps:
when the levels of the first to fifth input ports are Vcc, Vcc and Vm in sequence, judging that the controlled switch S9 is turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, Vm and Vm in sequence, judging that the controlled switches S4 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, Vm, Vcc and Vm in sequence, judging that the controlled switches S3 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, Vm and Vm in sequence, the controlled switches S3, S4 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, Vm, Vcc and Vm in sequence, the controlled switches S2 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, Vm, Vcc, Vm and Vm in sequence, the controlled switches S2, S4 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, Vm, Vcc and Vm in sequence, the controlled switches S2, S3 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, Vm and Vm in sequence, the controlled switches S2, S3, S4 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vm, Vcc and Vm in sequence, judging that the controlled switches S1 and S9 are turned on, and turning off other controlled switches;
when the levels of the first to fifth input ports are Vm, Vcc, Vm and Vm in sequence, judging that the controlled switches S1, S4 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vm, Vcc, Vm, Vcc and Vm in sequence, judging that the controlled switches S1, S3 and S9 are turned on, and turning off other controlled switches;
when the levels of the first to fifth input ports are Vm, Vcc, Vm and Vm in sequence, judging that the controlled switches S1, S3, S4 and S9 are on, and other controlled switches are off;
when the levels of the first to fifth input ports are Vm, Vcc and Vm in sequence, judging that the controlled switches S1, S2 and S9 are turned on, and turning off other controlled switches;
when the levels of the first to fifth input ports are Vm, Vcc, Vm and Vm in sequence, judging that the controlled switches S1, S2, S4 and S9 are on, and other controlled switches are off;
when the levels of the first to fifth input ports are Vm, Vcc and Vm in sequence, judging that the controlled switches S1, S2, S3 and S9 are on, and other controlled switches are off;
when the levels of the first to fifth input ports are Vm, Vm and Vm in sequence, judging that the controlled switches S1, S2, S3, S4 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, 0V and Vm in sequence, the controlled switches S8 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, 0V and Vm in sequence, the controlled switches S8 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, 0V, Vcc and Vm in sequence, judging that controlled switches S7 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, 0V and Vm in sequence, the controlled switches S7, S8 and S9 are judged to be turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, 0V, Vcc and Vm in sequence, judging that the controlled switches S6 and S9 are turned on, and turning off other controlled switches;
when the levels of the first to fifth input ports are Vcc, 0V, Vcc, 0V and Vm in sequence, the controlled switches S6, S8 and S9 are judged to be on, and other controlled switches are judged to be off;
when the levels of the first to fifth input ports are Vcc, 0V, 0V, Vcc and Vm in sequence, judging that the controlled switches S6, S7 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are Vcc, 0V and Vm in sequence, judging that the controlled switches S6, S7, S8 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are 0V, Vcc and Vm in sequence, judging that the controlled switches S5 and S9 are turned on, and turning off other controlled switches;
when the levels of the first to fifth input ports are 0V, Vcc, 0V and Vm in sequence, the controlled switches S5, S8 and S9 are judged to be turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are 0V, Vcc, 0V, Vcc and Vm in sequence, judging that the controlled switches S5, S7 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are 0V, Vcc, 0V and Vm in sequence, judging that the controlled switches S5, S7, S8 and S9 are turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are 0V, Vcc and Vm in sequence, the controlled switches S5, S6 and S9 are judged to be turned on, and other controlled switches are turned off;
when the levels of the first to fifth input ports are 0V, 0V, Vcc, 0V and Vm in sequence, judging that the controlled switches S5, S6, S8 and S9 are on, and other controlled switches are off;
when the levels of the first to fifth input ports are 0V, 0V, Vcc and Vm in sequence, judging that the controlled switches S5, S6, S7 and S9 are on, and other controlled switches are off;
when the levels of the first to fifth input ports are 0V, 0V and Vm in sequence, it is determined that the controlled switches S5, S6, S7, S8 and S9 are turned on, and the other controlled switches are turned off;
referring to fig. 4, the detection method for detecting the abnormal operating state of the controlled switch comprises the following implementation steps:
when the levels of the first to fifth input ports are any level signal, any level signal and Vcc in sequence, the controlled switch S9 is judged to be disconnected, and other controlled switches are judged to be abnormally connected;
when the levels of the first to fifth input ports are any level signal, any level signal and 0V in sequence, the controlled switches S9 and S0 are judged to be disconnected, and the other controlled switches are abnormal in connection; or judging that the controlled switches S1, S5 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected; or judging that the controlled switches S2, S6 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected; or judging that the controlled switches S3, S7 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected; or judging that the controlled switches S4, S8 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are Vm, 0V, any level signal and Vm in sequence, judging that the controlled switches S1, S6 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are Vm, any level signal, 0V, any level signal and Vm in sequence, judging that the controlled switches S1, S7 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are Vm, 0V, any level signal and Vm in sequence, judging that the controlled switches S1, S8 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are 0V, Vm, any level signal and Vm in sequence, judging that the controlled switches S2, S5 and S9 are on, the controlled switch S0 is off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are any level signal, Vm, 0V, any level signal and Vm in sequence, judging that the controlled switches S2, S7 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are any level signal, Vm, 0V, any level signal and Vm in sequence, judging that the controlled switches S2, S8 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are 0V, any level signal, Vm, any level signal and Vm in sequence, judging that the controlled switches S3, S5 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are an arbitrary level signal, 0V, Vm, an arbitrary level signal and Vm in sequence, judging that the controlled switches S3, S6 and S9 are on, the controlled switch S0 is off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are any level signal, Vm, 0V and Vm in sequence, judging that the controlled switches S3, S8 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are 0V, any level signal, Vm and Vm in sequence, judging that the controlled switches S4, S5 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are sequentially any level signal, 0V, any level signal, Vm and Vm, judging that the controlled switches S4, S6 and S9 are switched on, the controlled switch S0 is switched off, and the other controlled switches are abnormally connected;
when the levels of the first to fifth input ports are an arbitrary level signal, 0V, Vm and Vm in sequence, judging that the controlled switches S4, S7 and S9 are on, the controlled switch S0 is off, and the other controlled switches are abnormally connected;
it can be understood that the above detection method is completed based on the AD port of the MCU chip 11 itself, the flexibility of MCU port resource selection is high, meanwhile, the MCU chip 11 has an analog-to-digital converter (ADC) capable of converting an input voltage analog electrical signal into a level digital signal, and the ADC can detect a voltage value with a wide range, so the reference values Vcc, Vm, and 0V used in this embodiment are only a preferred example, and do not represent a limitation to specific reference values. In the detection method, other reference values are also used to preferably complete the detection, and the accuracy of the detection should not be limited to the reference values given in the present embodiment.
The embodiment also provides an energy storage inverter, which comprises an inverter circuit 12, wherein the detection circuit is adopted to detect the state of the controlled switch, and the input and the output of the inverter circuit 12 are controlled according to the detection result.
The detection circuit of the DRED controller provided by the embodiment comprises an MCU chip 11, wherein the MCU chip 11 is provided with five AD ports, and the controlled switches are connected with the five AD ports through five communication lines, so that the AD ports correspond to the corresponding controlled switches, each AD port can identify the level of the input voltage sampling signal, and the on-off states of the controlled switches S0 to S9 are determined according to the identification result. The detection circuit can complete detection based on the port of the MCU chip 11, has a simple structure, uses a small number of electronic components, and can reduce the cost; the detection method provided by the embodiment can determine the switching states of the controlled switches S0 to S9 according to the levels of the voltage sampling signals input to the AD ports of the MCU chip 11. The detection method can detect the specific closing condition of each controlled switch in the normal working state of the controlled switches, can also detect the abnormal connection, disconnection or connection condition of each controlled switch in the abnormal working state of the controlled switches, is beneficial to accurately and quickly judging the closing condition of each controlled switch, can detect and troubleshoot faults if the working state is abnormal, and is simple to operate and easy to realize; the energy storage inverter provided by the embodiment can detect the state of the controlled switch, and change the input and the output of the inverter circuit 12 according to the state of the controlled switch; the energy storage inverter can respond to the state of the controlled switch in time, can execute corresponding operation according to the state of the controlled switch, and better meets the requirement of safety specifications; meanwhile, the energy storage inverter can form a detection circuit only by using the AD port, the communication line and the resistor of the MCU chip 11, the number of electronic components is small, the cost can be reduced, the space occupied by the system is reduced, and the product volume is optimized.
The above embodiments are only for illustrating the technical concept and features of the present invention, and are preferred embodiments, which are intended to enable persons skilled in the art to understand the contents of the present invention and to implement the present invention, and thus, the protection scope of the present invention cannot be limited thereby. All equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims (4)
1. A detection circuit for a DRED controller, comprising a controller, wherein the detection circuit further comprises:
a first communication line having one end connected to the first input port of the controller and the other end for connecting intermediate nodes of the controlled switches S1 and S5 of the DRED circuit;
a second communication line having one end connected to the second input port of the controller and the other end for connecting intermediate nodes of the controlled switches S2 and S6 of the DRED circuit;
a third communication line having one end connected to the third input port of the controller and the other end for connecting to the intermediate nodes of the controlled switches S3 and S7 of the DRED circuit;
a fourth communication line having one end connected to the fourth input port of the controller and the other end for connecting to the middle nodes of the controlled switches S4 and S8 of the DRED circuit;
a fifth communication line having one end connected to the fifth input port of the controller and the other end for being grounded through the controlled switches S9 and S0 of the DRED circuit;
one end of the first detection resistor is connected with a power supply, and the other end of the first detection resistor is connected with the first communication line;
one end of the second detection resistor is connected with the power supply, and the other end of the second detection resistor is connected with the second communication line;
one end of the third detection resistor is connected with the power supply, and the other end of the third detection resistor is connected with the third communication line;
one end of the fourth detection resistor is connected with the power supply, and the other end of the fourth detection resistor is connected with the fourth communication line; and
and one end of the fifth detection resistor is connected with the power supply, and the other end of the fifth detection resistor is connected with the fifth communication line.
2. The detection circuit according to claim 1, wherein the controller is an MCU chip, and the first input port, the second input port, the third input port, the fourth input port, and the fifth input port are AD ports of the MCU chip, respectively.
3. The detection circuit of claim 1, further comprising:
a signal sampling terminal DRM1/5 connected to the first communication line;
a signal sampling terminal DRM2/6 connected to the second communication line;
a signal sampling terminal DRM3/7 connected to the third communication line;
a signal sampling terminal DRM4/8 connected to the fourth communication line;
and a signal sampling terminal COM LOAD connected to the fifth communication line.
4. A tank inverter comprising an inverter circuit, wherein the tank inverter further comprises a detection circuit according to any one of claims 1 to 3, and the controller is configured to control an input and an output of the inverter circuit according to the detection result.
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