CN112782508B

CN112782508B - Bidirectional direct current charging pile Australia grid-connected DRED interface detection method and circuit

Info

Publication number: CN112782508B
Application number: CN202011633917.7A
Authority: CN
Inventors: 杜飞; 杨志; 杨立军
Original assignee: Guochuang Mobile Energy Innovation Center Jiangsu Co Ltd
Current assignee: Guochuang Mobile Energy Innovation Center Jiangsu Co Ltd
Priority date: 2020-12-31
Filing date: 2020-12-31
Publication date: 2022-04-19
Anticipated expiration: 2040-12-31
Also published as: CN112782508A

Abstract

The invention discloses a method and a circuit for detecting a bidirectional direct current charging pile Australia grid-connected DRED interface, belonging to the technical field of electric vehicles, and comprising a controller, a DRED interface, a detection sampling circuit and an analog switch circuit, wherein the detection sampling circuit is used for detecting the states of 9 switches in the DRED interface through six communication lines of the DRED interface and coding the states, so that the technical problem of quickly and accurately detecting the state of the DRED interface is solved; and the ADC ports can be switched by using an analog switch under the condition of less ADC ports, and the detection can be completed by using only one ADC port and three GPIOs.

Description

Bidirectional direct current charging pile Australia grid-connected DRED interface detection method and circuit

Technical Field

The invention belongs to the technical field of electric automobiles, and relates to a method and a circuit for detecting a Australia grid-connected DRED interface of a bidirectional direct-current charging pile.

Background

Along with new energy automobile and the development of direct current charging pile, electric automobile two-way charging pile develops rapidly, and two-way charging pile both can charge for the car, can regard the electric automobile of the state of stopping as portable energy memory again, and the response provides the stability of emergency power supply and electric wire netting at the electric wire netting demand side, realizes the interdynamic with the electric wire netting.

In australia AS/NZS 4777, a framework and a technical standard for grid control have been proposed, in which control commands are issued through a dred (demand Response energy utilization device) interface to control charging pile states and adjustment of charging and discharging power of the charging pile, and the power is divided into modes of import 75%/50%/0% and export 75%/50%/0%. The DRED interface adopts an RJ45 interface, the interface uses six communication lines to detect the closing states of 9 switches, the DRED interface has various states, each pin is connected with two switches, the detection of the MCU IO port cannot be directly performed, and the DRED interface is extremely easily interfered and the DRED state detection is influenced under the condition that the power is high and the use environment is complex.

Disclosure of Invention

The invention aims to provide a method and a circuit for detecting a Australia grid-connected DRED interface of a bidirectional direct-current charging pile, and the technical problem of rapidly and accurately detecting the state of the DRED interface is solved.

In order to achieve the purpose, the invention adopts the following technical scheme:

a bidirectional direct current charging pile Australia grid-connected DRED interface detection method comprises the following steps:

step 1: establishing a controller, wherein the controller is connected with six communication lines of the DRED interface through an AD interface of the controller, and is used for detecting states of 9 switches in the DRED interface through the six communication lines of the DRED interface, and the 9 switches comprise a switch S0, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5, a switch S6, a switch S7 and a switch S8;

the six communication lines comprise a communication line DRM1/5, a communication line DRM2/6, a communication line DRM3/7, a communication line DRM4/8, a communication line REF GE/0 and a communication line COM LOAD/0;

communication line DRM1/5 detects the states of switch S1 and switch S5, communication line DRM2/6 detects the states of switch S2 and switch S6, communication line DRM3/7 detects the states of switch S3 and switch S7, communication line DRM4/8 detects the states of switch S4 and switch S8, communication line REF GEN/0 is 3.3V power supply, and communication line COM LOAD/0 detects the state of switch S0;

step 2: judging whether the communication line COM LOAD is 3.3V: yes, indicating that switch S0 was pressed, switch S1 and switch S5 were pressed simultaneously or switch S2 and switch S6 were pressed simultaneously or switch S3 and switch S7 were pressed simultaneously or switch S4 and switch S8 were pressed simultaneously;

at this time, the controller needs to be switched to a DISCONNECT state, namely a disconnection state; executing the step 9;

if not, executing the step 3;

and step 3: judging whether the communication line COM LOAD is 0V: if yes, it indicates that the switch S0 is not pressed, the switch S1 and the switch S5 are not pressed at the same time, the switch S2 and the switch S6 are not pressed at the same time, the switch S3 and the switch S7 are not pressed at the same time, or the switch S4 and the switch S8 are not pressed at the same time;

and 4, step 4: the controller detects the communication line DRM1/5, if the communication line DRM1/5 is 1.65V, the switch S1 and the switch S5 are both disconnected, if the communication line DRM1/5 is 3.3V, the switch S5 is pressed, and if the communication line DRM1/5 is 0V, the switch S1 is pressed;

and 5: the controller detects the communication line DRM2/6, if the communication line DRM2/6 is 1.65V, the switch S2 and the switch S6 are disconnected, if the communication line DRM2/6 is 3.3V, the switch S6 is pressed, and if the communication line DRM2/6 is 0V, the switch S2 is pressed;

step 6: the controller detects the communication line DRM3/7, if the communication line DRM3/7 is 1.65V, the switch S3 and the switch S7 are disconnected, if the communication line DRM3/7 is 3.3V, the switch S7 is pressed, and if the communication line DRM3/7 is 0V, the switch S3 is pressed;

and 7: the controller detects the communication line DRM4/8, if the communication line DRM4/8 is 1.65V, the switch S4 and the switch S8 are both disconnected, if the communication line DRM4/8 is 3.3V, the switch S8 is pressed, and if the communication line DRM4/8 is 0V, the switch S4 is pressed;

and 8: the controller detects the pressed key through the methods from step 2 to step 7, and obtains a combined code through a coding mode, wherein the coding mode is that the switches S1 to S8 are regarded as 8-bit data to be used as a state judgment array;

the controller obtains the state of a switch in the DRED interface according to the state judgment array table lookup, so that the power of the DRED interface is adjusted;

and step 9: and (6) ending.

Preferably, the controller completes the detection of the six communication lines of the DRED interface within 2 seconds.

Preferably, an analog switch is disposed between the controller and six communication lines of the DRED interface, and a detection sequence of the six communication lines is selected through the analog switch.

Preferably, the switch S0 is connected between the communication line REF GE/0 and the communication line COM LOAD/0;

the switch S1 and the switch S5 are connected in series and then connected between the communication line REF GE/0 and the communication line COM LOAD/0, and the communication line DRM1/5 is connected to the connection node of the switch S1 and the switch S5;

the switch S2 and the switch S6 are connected in series and then connected between the communication line REF GE/0 and the communication line COM LOAD/0, and the communication line DRM2/6 is connected to the connection node of the switch S2 and the switch S6;

the switch S3 and the switch S7 are connected in series and then connected between the communication line REF GE/0 and the communication line COM LOAD/0, and the communication line DRM3/7 is connected to the connection node of the switch S3 and the switch S7;

the switch S4 and the switch S8 are connected in series and then connected between the communication line REF GE/0 and the communication line COM LOAD/0, and the communication line DRM4/8 is connected to a connection node between the switch S4 and the switch S8.

The utility model provides a two-way direct current fills electric pile Australia and is incorporated into power networks DRED interface detection circuitry, includes controller, DRED interface, detects sampling circuit and analog switch circuit, and the AD interface and the analog switch circuit's of controller output are connected, and analog switch circuit's input is connected with the output that detects sampling circuit, detects six communication lines of sampling circuit's input connection DRED interface.

The six communication lines include communication line DRM1/5, communication line DRM2/6, communication line DRM3/7, communication line DRM4/8, communication line REF GE/0 and communication line COM LOAD/0, and the communication line REF GE/0 is connected to an externally supplied 3.3V power supply.

Preferably, the detection sampling circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R7, a resistor R4, a resistor R8, a resistor R9 and a resistor R10;

after the resistor R7 and the resistor R10 are connected in series, one end of the resistor R7 is connected with a 3.3V power supply, the other end of the resistor R10 is connected with a ground wire, and the connection node of the resistor R7 and the resistor R10 is connected with the communication line DRM 1/5;

after the resistor R3 and the resistor R9 are connected in series, one end of the resistor R3 is connected with a 3.3V power supply, the other end of the resistor R9 is connected with a ground wire, and the connection node of the resistor R3 and the resistor R9 is connected with the communication line DRM 2/6;

after the resistor R2 and the resistor R8 are connected in series, one end of the resistor R2 is connected with a 3.3V power supply, the other end of the resistor R8 is connected with a ground wire, and the connection node of the resistor R2 and the resistor R8 is connected with the communication line DRM 3/7;

after the resistor R1 and the resistor R4 are connected in series, one end of the resistor R1 is connected with a 3.3V power supply, the other end of the resistor R4 is connected with a ground wire, and the connection node of the resistor R1 and the resistor R4 is connected with the communication wire DRM 4/8.

Preferably, a clamp protection circuit is further provided, and the clamp protection circuit comprises a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a clamp diode D1;

after the resistor R11 is connected with the capacitor C1 in series, one end of the resistor R11 is connected with the communication line DRM1/5, and the other end of the resistor R11 is connected with the ground line;

after the resistor R12 is connected with the capacitor C2 in series, one end of the resistor R12 is connected with the communication line DRM2/6, and the other end of the resistor R12 is connected with the ground wire;

after the resistor R13 is connected with the capacitor C3 in series, one end of the resistor R13 is connected with the communication line DRM3/7, and the other end of the resistor R13 is connected with the ground wire;

after the resistor R14 is connected with the capacitor C4 in series, one end of the resistor R14 is connected with the communication line DRM4/8, and the other end of the resistor R14 is connected with the ground wire;

after the resistor R11 is connected with the capacitor C1 in series, one end of the resistor R11 is connected with the communication line COM LOAD/0, and the other end of the resistor R11 is connected with the ground wire;

a pin 1 of the clamping diode D1 is connected with the ground wire, a pin 2 is connected with a connection node of the capacitor C1 and the resistor R11, and a pin 3 is connected with a 3.3V power supply.

Preferably, the analog switch circuit comprises an analog switch S9, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R16, a capacitor C6 and a clamping diode D2;

the 4 pin, the 5 pin, the 6 pin, the 7 pin and the 12 pin of the analog switch S9 are respectively connected with the communication line DRM1/5, the communication line DRM2/6, the communication line DRM3/7, the communication line DRM4/8 and the communication line COM LOAD/0 through a resistor R17, a resistor R18, a resistor R19, a resistor R20 and a resistor R21;

a pin 16, a pin 15 and a pin 2 of the analog switch S9 are respectively connected with 3 IO ports of the controller;

the pin 6 of the analog switch S9 is connected to an AD port of the controller through a resistor R16, the capacitor C6 is a filter capacitor of the pin 6 of the analog switch S9, and the clamp diode D2 is a clamp diode of the pin 6 of the analog switch S9.

The invention relates to a method and a circuit for detecting a bidirectional direct current charging pile Australia grid-connected DRED interface, which solve the technical problem of rapidly and accurately detecting the state of the DRED interface, and have the advantages of simple interface circuit, lower cost, wider voltage range of various states detected by an ADC (analog to digital converter), strong anti-interference capability, high flexibility in MCU port resource selection, and capability of detecting signals by five ADCs under the condition of richer MCU ADCs; and the ADC ports can be switched by using an analog switch under the condition of less ADC ports, and the detection can be completed by using only one ADC port and three GPIOs.

Drawings

FIG. 1 is a flow chart of the present invention;

FIG. 2 is a circuit diagram of the DRED interface and the detection sampling circuit of the present invention;

fig. 3 is a circuit diagram of an analog switch circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1:

as shown in fig. 1 to fig. 3, the method for detecting the australian grid-connected DRED interface of the bidirectional dc charging pile includes the following steps:

if not, executing the step 3;

taking DRM1/5 as an example, R7(100K) and R10(100K) in fig. 2 below divide the voltage, the initial state of the pin is 1/2VCC 1.65V, the ADC detects the voltage value, no key press occurs when the voltage value is 1.65 ± 0.5V, the voltage value is 3.3 ± 1V indicates S5 press, the voltage value is 0 ± 1V indicates S1 press, the voltage interval ranges of the three states are wide, and the interference resistance is strong.

step 6: the controller detects the communication line DRM3/7, the communication line DRM3/7 indicates that both the switch S3 and the switch S7 are off if it is 1.65V, i.e., the voltage at 1/2REF GEN, the communication line DRM3/7 indicates that the switch S7 is pressed if it is 3.3V, and the communication line DRM3/7 indicates that the switch S3 is pressed if it is 0V;

in the present embodiment, if S1 and S6 are pressed, the number of the calculated array is 2^5+2^0 ^ 33; the corresponding data bits are as follows:

fig. 3 shows a case where the switch S1, the switch S3, and the switch S6 are simultaneously pressed in this embodiment. The invention obtains the state of the DRED interface according to the coding table look-up of the data.

The DRED detection time in the Australian standard is 2S, software can read the values of all the ADC channels in sequence in a polling mode, under the condition that the ADC interfaces are relatively lacked, time-sharing detection can be performed through analog switching, one ADC interface detects the voltage values of the five interfaces in sequence, and ADC port resources are saved.

And step 9: and (6) ending.

Example 2:

the bidirectional direct-current charging pile Australia grid-connected DRED interface detection circuit is matched with the bidirectional direct-current charging pile Australia grid-connected DRED interface detection method in the embodiment 1, and comprises a controller, a DRED interface, a detection sampling circuit and an analog switch circuit, wherein an AD interface of the controller is connected with an output end of the analog switch circuit, an input end of the analog switch circuit is connected with an output end of the detection sampling circuit, and an input end of the detection sampling circuit is connected with six communication lines of the DRED interface.

in this embodiment, the resistor R7 and the resistor R10 are voltage dividing circuits, and the voltage value on the communication line DRM1/5 is obtained by the voltage dividing value, and which switch is pressed is determined by the voltage value.

In the present invention, any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present invention.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims

1. A bidirectional direct current charging pile Australia grid-connected DRED interface detection method is characterized by comprising the following steps: the method comprises the following steps:

the switch S0 is connected between the communication line REF GE/0 and the communication line COM LOAD/0;

the switch S4 and the switch S8 are connected in series and then connected between the communication line REF GE/0 and the communication line COM LOAD/0, and the communication line DRM4/8 is connected to the connection node of the switch S4 and the switch S8;

if not, executing the step 3;

and step 9: and (6) ending.

2. The method for detecting the Australia grid-connected DRED interface of the bidirectional direct-current charging pile of claim 1, wherein the method comprises the following steps: the controller completes the detection of six communication lines of the DRED interface within 2 seconds.

3. The method for detecting the Australia grid-connected DRED interface of the bidirectional direct-current charging pile of claim 1, wherein the method comprises the following steps: and an analog selector switch is arranged between the controller and the six communication lines of the DRED interface, and the detection sequence of the six communication lines is selected through the analog selector switch.

4. A bidirectional direct current charging pile Australia grid-connected DRED interface detection circuit is used for the bidirectional direct current charging pile Australia grid-connected DRED interface detection method according to claim 1, and is characterized in that: the system comprises a controller, a DRED interface, a detection sampling circuit and an analog switch circuit, wherein an AD interface of the controller is connected with an output end of the analog switch circuit, an input end of the analog switch circuit is connected with an output end of the detection sampling circuit, and an input end of the detection sampling circuit is connected with six communication lines of the DRED interface;

5. The circuit of claim 4, wherein the bidirectional DC charging pile Australian grid-connected DRED interface detection circuit comprises: the detection sampling circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R7, a resistor R4, a resistor R8, a resistor R9 and a resistor R10;

6. The circuit of claim 5, wherein the bidirectional DC charging pile Australian grid-connected DRED interface detection circuit comprises: the circuit is also provided with a clamping protection circuit which comprises a resistor R11, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5 and a clamping diode D1;

7. The circuit of claim 5, wherein the bidirectional DC charging pile Australian grid-connected DRED interface detection circuit comprises: the analog switch circuit comprises an analog switch S9, a resistor R17, a resistor R18, a resistor R19, a resistor R20, a resistor R21, a resistor R16, a capacitor C6 and a clamping diode D2;