CN206602115U - One kind is based on silicon substrate P-type channel field-effect transistor - Google Patents

Abstract

The utility model is related to field of semiconductor manufacture, disclose it is a kind of be based on silicon substrate P-type channel field-effect transistor, including on substrate from the bottom to top, low temperature GaSb/AlSb super-lattice buffer layers, AlGaSb cushions, GaSb channel layers, AlSb separation layers, AlGaSb barrier layers, the AlGaSb barrier layers end face first gradient In_XGa_1‑XSb cap layers and the second gradient In in opposite other end face_XGa_1‑XSb cap layers, in addition to it is formed at first gradient In_XGa_{1‑ X}Source electrode and the second gradient In in Sb cap layers_XGa_1‑XDrain electrode in Sb cap layers, is formed at first gradient In_XGa_1‑XSb cap layers and the second gradient In_XGa_1‑XGrid between Sb cap layers and on AlGaSb barrier layers, the AlGaSb barrier layers are specially p-type doped structure, two-dimensional hole gas is formed between GaSb channel layers, short-channel effect is brought during effective improvement transistor scaled down and reduces power consumption, overcome Moore's Law, break the limit, maintain semiconductor industry scaled down process.

Description

One kind is based on silicon substrate P-type channel field-effect transistor

Technical field

The utility model is related to field of semiconductor manufacture, more particularly to a kind of based on silicon substrate P-type channel field effect transistor Pipe.

Background technology

According to Moore's Law, " number of open ended component on integrated circuit will about increase every 18-24 months One times, performance will also lift one times." on the whole for, if the IC of same specification is produced under wafer of the same area, with processing procedure The progress of technology, every a year and a half, IC quantums of output can be doubled, and be scaled cost, i.e., can be reduced every a year and a half cost Fifty percent, every year on average cost can reduce by three into many.With regard to Moore's Law extension, IC technologies promote a generation every a year and a half.State Border semiconductor-on-insulator manufacturer all follows this law substantially.

But, maximum Intel of chip maker announces that skills will be manufactured based on 10 nanometers under postponement a few days ago in the world The issuing time of the Cannonlake chips of art, was postponed to the second half year in 2017, and Cannonlake chips original date of issue Phase is 2016.Intel company CEO Brian Krzanich are represented in videoconference, " due to using all kinds of phases Pass technology, and each technology has its own a series of complexity and difficulties, from 14 nanometers to 10 nanometers and from 22 nanometers It is not the same thing to 14 nanometers.If it is desired to large-scale production, photoetching technique can be more difficult, moreover, completing Suresh Kumar step Number can be continuously increased." Intel follows the timetable for every two years reducing transistor area half all the time, that is, it is commonly called as " Moore's Law ", above-mentioned message makes timetable slight crack occur, and it is that construction chip becomes less and less also more complicated to trace it to its cause, Power consumption is increasingly difficult to reduce, and various short-channel effects are difficult to overcome.

Therefore, although semiconductor technology is showing improvement or progress day by day, but is limited by physical law, and minimum dimension can not possibly be too small, to prolong The validity of continuous semiconductor Moore's Law, processor transistor is made using new material very urgent.At present Existing many research institutions, through the material that higher performance is integrated for silicon materials, for example with compound semiconductor materials such as GaAs/InP (such as InGaAsP and indium phosphide), forms the transistor of so-called broad stopband III-V raceway grooves, can promote p-type Mobility and offer high carrier speed and high driving current, this new compound semiconductor are expected to surmount silicon materials property itself Can, Moore's Law is maintained, realizes and continues scaled down.

But this scheme also encounters many problems at present, be primarily present of both challenge, on the one hand, silica-base material and It is poor to there is big lattice constant in compound semiconductor materials such as GaAs/InP etc., and atomic lattice is difficult between material can not be overcome always With the challenge of matching；On the other hand, usual Si based transistors are bonded by P-type channel transistor and n-channel transistor CMOS structure applies to large scale digital field, and n-channel device is easily realized generally in terms of III-V such as GaAs devices, and P ditches Road device is limited to doping engineering and epitaxial manufacture process is difficult to and low hole mobility (200-400cm²V^-1sec^-1), at present With reference to n- raceway grooves and P- raceway grooves GaAs transistors due to both mobilities difference can not realize very much the same circuit structures of CMOS greatly, Greatly hinder application of the GaAs devices in digital circuit field.

Utility model content

The utility model embodiment is a kind of based on silicon substrate P-type channel field-effect transistor by providing, and solves existing Transistor in technology uses N-channel and P-channel, because both mobilities differ too big, it is impossible to realize the same circuit knots of CMOS The technical problem of structure.

In order to solve the above-mentioned technical problem, the utility model embodiment provides a kind of based on silicon substrate P-type channel effect Answer transistor, including substrate, low temperature GaSb/AlSb super-lattice buffer layers, AlGaSb cushions, GaSb raceway grooves from the bottom to top Layer, AlSb separation layers, AlGaSb barrier layers, on the AlGaSb barrier layers end face first gradient In_XGa_1-XSb cap layers and The second gradient In in opposite other end face_XGa_1-XSb cap layers, in addition to it is formed at first gradient In_XGa_1-XSource electrode in Sb cap layers With the second gradient In_XGa_1-XDrain electrode in Sb cap layers, is formed at first gradient In_XGa_1-XSb cap layers and the second gradient In_XGa_1-XSb Grid between cap layers and on AlGaSb barrier layers, the AlGaSb barrier layers are specially p-type doped structure, with GaSb ditches Two-dimensional hole gas is formed between channel layer.

Further, the substrate is specially P type substrate, using any one in Si, SiC, GaN, sapphire, diamond Plant material.

Further, the low temperature GaSb/AlSb super-lattice buffer layers are specially sandwich construction, and thickness is 300~ 800nm。

Further, the AlGaSb cushions undope, and thickness is 300~800nm.

Further, the GaSb channel layers undope, and thickness is 30~100nm, the GaSb channel layers and AlGaSb Barrier layer contact position 5nm regions form two-dimensional hole gas.

Further, the AlSb separation layers undope, and thickness is 2~5nm.

Further, the thickness of the AlGaSb barrier layers is 15~40nm.

Further, the first gradient In_XGa_1-XSb cap layers and the second gradient In_XGa_1-XThe thickness of Sb cap layers is 15 ~40nm.

Using one or more technical scheme in the utility model, have the advantages that：

1st, the utility model forms the high mobility p-type MODFET based on silicon substrate and can at a high speed patrolled with conventional Si bases CMOS Circuit devcie process compatible is collected, using special LT GaSb/AISb multicycles superlattice structure formation quantum wells (amounts Sub- trap) and AlGaSb cushions, effectively overcome atomic lattice between cushioning layer material and silicon materials and be difficult to the challenge matched, Simultaneously available for absorbing between Si substrates and subsequent epitaxial layer because the stress that lattice mismatch is produced, dissipating for substrate generation is filtered out Hit the heart, it is to avoid produce lattice relaxation.

2nd, the P-channel MODFET devices that this utility model is formed can with n-channel GaAs HEMT, or pHEMT, or MHEMT devices constitute III-V CMOS structures, greatly widen application of the GaAs devices in digital circuit field.

3rd, the P-channel MODFET devices that the utility model is formed can provide higher p- by compound semiconductor materials Tpye mobility and high carrier speed and the iii-v transistor channels of high driving current and can improve in III-V n-type and The problem of P-type device mobility huge difference.

4th, the broad stopband P-channel MODFET devices that the utility model is formed effectively improve transistor scaled down mistake Short-channel effect is brought in journey and power consumption is reduced.

5th, the P-channel MODFET devices that the utility model is formed effectively overcome Moore's Law, break the limit, maintain half Conductor industry scaled down process.

Brief description of the drawings

Fig. 1 be the utility model embodiment in be based on silicon substrate P-type channel field-effect transistor structure schematic diagram.

Embodiment

The utility model embodiment is a kind of based on silicon substrate P-type channel field-effect transistor by providing, and solves existing Transistor in technology uses N-channel and P-channel, because both mobilities differ too big, it is impossible to realize the same circuit knots of CMOS The technical problem of structure.

In order to solve the above-mentioned technical problem, it is new to this practicality below in conjunction with Figure of description and specific embodiment The technical scheme of type is described in detail.

One kind that the utility model embodiment is provided is based on silicon substrate P-type channel field-effect transistor, as shown in figure 1, bag Include substrate 10 from the bottom to top, low temperature GaSb/AlSb super-lattice buffer layers 20, AlGaSb cushions 30, GaSb channel layers 40, AlSb separation layers 50, AlGaSb barrier layers 60, on the AlGaSb barrier layers 60 end face first gradient In_XGa_1-XSb cap layers The 701 and second gradient In in opposite other end face_XGa_1-XSb cap layers 702, in addition to it is formed at first gradient In_XGa_1-XSb cap layers Source S and the second gradient In on 701_XGa_1-XDrain D in Sb cap layers 702, is formed at first gradient In_XGa_1-XSb cap layers 701 With the second gradient In_XGa_1-XGrid G between Sb cap layers 702 and on AlGaSb barrier layers 60, the AlGaSb barrier layers 60 Specially two-dimensional hole gas is formed between p-type doped structure, with GaSb channel layers 40.

In a particular embodiment, the substrate 10 is specially P type substrate, using Si, SiC, GaN, sapphire, diamond In any one material, be mainly used in supporting role.

Low temperature GaSb/AlSb super-lattice buffer layers 20 are specially sandwich construction, form GaSb/AlSb SQWs, mainly Be use low temperature (LT) growth pattern, undope, thickness be 300~800nm, for absorb substrate and subsequent epitaxial layer between because The stress that lattice mismatch is produced, it is to avoid lattice relaxation is produced, while the defect at isolation liner bottom spreads to raceway groove.

The AlGaSb cushions 30 undope, and thickness is 300~800nm, and Al content is less than 40%, substrate to channel layer Between cushion, available for absorb substrate and subsequent epitaxial layer between because lattice mismatch produce stress.

The GaSb channel layers 40 undope, and thickness is 30~100nm, and the GaSb channel layers 40 and AlGaSb barrier layers 60 connect Synapsis 5nm regions form two-dimensional hole gas (2DHG).

The AlSb separation layers 50 undope, and thickness is 2~5nm, between GaSb channel layers 40 and AlGaSb barrier layers 60 The broader AlSb separation layers 50 of one layer of forbidden band are inserted, are mainly used to keep apart the scatterer unit of AlGaSb barrier layers 60 to GaSb The influence of channel layer two-dimensional hole gas, improves raceway groove 2DHG mobility and concentration.

The thickness of the AlGaSb barrier layers 60 is 15-40nm, is adulterated using P+ type, the dosage of body doping (Be or C or Mg) For 1 × 10¹⁸cm^-3~3 × 10¹⁸cm^-3, for the freedom with grid G metal formation Schottky contacts and offer GaSb channel layers 40 Hole.

First gradient In_XGa_1-XSb cap layers and the second gradient In_XGa_1-XThe thickness of Sb cap layers is 15~40nm, wherein In contents are progressively upgraded to 0.5 from 0, and thickness is 15~40nm, and P+ adulterates, and the dosage of body doping (Be or C or Mg) is 5 × 10¹⁸cm^-3~2 × 10¹⁹cm^-3, to protect barrier layer not oxidized, while to reduce ohmic contact resistance rate.

Specific manufacturing process：

Sequentially forming substrate 10, low temperature GaSb/AlSb super-lattice buffer layers 20, AlGaSb cushions 30, GaSb raceway grooves Layer 40, AlSb separation layers 50, AlGaSb barrier layers 60, In_XGa_1-XPass through following steps in Sb cap layers：

The first step, using photoetching and wet etching formation isolation table top, using H₃PO₄:H₂O₂:H₂O=3:1:50 formulas Chemical reagent performs etching isolation, etches In_XGa_1-XSb cap layers, AlGaSb barrier layers, GaSb channel layers, until AlGaSb bufferings Layer, forms an isolated area, etching time 80s completes 1800A isolation heights, with provide be mutually isolated close to planar structure Active area；

Ti/Pt/Au metals, then the source-drain electrode through conventional lift-off process formation Ohmic contact are evaporated in second step, photoetching, This usual layer is made on the cap of active layer the top (cap layers), to reduce contact resistivity, then be aided with high annealing (> 350 degree), form good ohmic contact；

3rd step, mask is made using photoresist, exposes device gate window areas, and wet etching falls the GaSb in gate regions cap。

4th step, completes grid technique, evaporates Ti/Pt/Au metals, then through conventional lift-off process formation gate metal.

Using the formation of above-mentioned technique based on silicon substrate P-type channel field-effect transistor, superelevation hole mobility can be achieved (nearly thousand mobilities), effectively lift p-type HFET mobilities to improve n-type and the huge difference of P-type device mobility in III-V The problem of.

Moreover, epitaxial structure is realized using the heterogeneous integration mode of silicon-based substrate, its special LT GaSb/AISb multicycle Superlattice structure formation quantum wells (SQW) and AlGaSb cushions, effectively overcome cushioning layer material and silicon Atomic lattice is difficult to the challenge matched between material, while being lost available for absorbing between Si substrates and subsequent epitaxial layer because of lattice Stress with generation, filters out the scattering center of substrate generation, it is to avoid produce lattice relaxation.The substrate used in the epitaxial structure For P-type Si substrates, realize heterogeneous integrated with silicon substrate.

Therefore, in the utility model, using MOCVD or MBE equipment, answer its special GaSb/AISb many by special Period superlattice formation quantum wells (SQW) buffer layer structure, solves silicon-based substrate and compound is partly led The unmatched problem of lattice of body material 8%, effectively overcomes atomic lattice between cushioning layer material and silicon materials and is difficult to The challenge matched somebody with somebody, filters out the scattering center of Si substrates generation.The Gao Qian based on silicon substrate is realized by p-type modulation doping simultaneously Shifting rate P-channel AlGaSb/GaSb MODFET structures simultaneously effectively lift p-type HFET mobilities to improve n-type and p-type in III-V The problem of device mobility huge difference.The present invention can combine other silicon substrates n- raceway groove GaAs HEMT, or pHEMT, or mHEMT Form so-called broad stopband III-V CMOS transistor structures, it is possible to provide higher carrier velocity and higher driving current, it is this new Compound semiconductor be expected to surmount silicon materials performance itself, maintain Moore's Law, effectively reduce chip area, realize brilliant Body pipe continues scaled down.

Although having been described for preferred embodiment of the present utility model, those skilled in the art once know substantially Creative concept, then can make other change and modification to these embodiments.So, appended claims are intended to be construed to bag Include preferred embodiment and fall into having altered and changing for the utility model scope.

Obviously, those skilled in the art can carry out various changes and modification without departing from this practicality to the utility model New spirit and scope.So, if these modifications and variations of the present utility model belong to the utility model claim and Within the scope of its equivalent technologies, then the utility model is also intended to comprising including these changes and modification.

Claims (8)

1. one kind is based on silicon substrate P-type channel field-effect transistor, it is characterised in that including substrate from the bottom to top, low temperature It is GaSb/AlSb super-lattice buffer layers, AlGaSb cushions, GaSb channel layers, AlSb separation layers, AlGaSb barrier layers, described The first gradient In of end face on AlGaSb barrier layers_XGa_1-XSb cap layers and the second gradient In in opposite other end face_XGa_1-XSb caps Layer, in addition to it is formed at first gradient In_XGa_1-XSource electrode in Sb cap layers and positioned at the second gradient In_XGa_1-XLeakage in Sb cap layers Pole, is formed at first gradient In_XGa_1-XSb cap layers and the second gradient In_XGa_1-XBetween Sb cap layers and on AlGaSb barrier layers Grid, the AlGaSb barrier layers are specially to form two-dimensional hole gas between p-type doped structure, with GaSb channel layers.

2. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the substrate tool Body is P type substrate, using any one material in Si, SiC, GaN, sapphire, diamond.

3. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the low temperature GaSb/AlSb super-lattice buffer layers are specially sandwich construction, and thickness is 300~800nm.

4. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the AlGaSb Cushion undopes, and thickness is 300~800nm.

5. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the GaSb ditches Channel layer undopes, and thickness is 30~100nm, and the GaSb channel layers form two dimension with AlGaSb barrier layers contact position 5nm regions Hole gas.

6. it is according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the AlSb every Absciss layer undopes, and thickness is 2~5nm.

7. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that the AlGaSb The thickness of barrier layer is 15~40nm.

8. according to claim 1 be based on silicon substrate P-type channel field-effect transistor, it is characterised in that first ladder Spend In_XGa_1-XSb cap layers and the second gradient In_XGa_1-XThe thickness of Sb cap layers is 15~40nm.