CN106952952B - A kind of III-V CMOS type is counterfeit to match heterojunction field effect transistor - Google Patents
A kind of III-V CMOS type is counterfeit to match heterojunction field effect transistor Download PDFInfo
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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Abstract
The present invention relates to semiconductor device processing technology fields, it is counterfeit with heterojunction field effect transistor more particularly to a kind of broad stopband III-V CMOS type based on silicon substrate, combining n-channel transistor and p-channel transistor, the type Heterostructure Field Effect Transistor Materials use the epitaxial growth of MOCVD or MBE equipment, by successively the first multilayer lattice strain buffer layer, InGaSb channel layer, AlGaSb barrier layer of epitaxial growth, GaSb cap layers, the second multilayer lattice strain buffer layer, InGaAs channel layer, AlGaAs barrier layer and In on high resistivity silicon substrateXGa1‑XAs cap layers are constituted.The present invention can effectively promote p-channel transistor mobility, the problem of to improve the huge difference of n-channel transistor and p-channel transistor mobility in III-V, and provide the broad stopband iii-v transistor channels of high carrier speed Yu high driving current, the effective transistor scaled down that improves brings short-channel effect in the process, reduce power consumption, overcome Moore's Law, break the limit, maintains semiconductor industry scaled down process.
Description
Technical field
The invention belongs to semiconductor device processing technology fields, and in particular to a kind of III-V CMOS type is counterfeit to match heterojunction field
Effect transistor.
Background technique
According to Moore's Law, " number of open ended component on integrated circuit will about increase every 18-24 months
One times, performance will also promote one times ".On the whole for, if the IC of same specification is produced under wafer of the same area, with processing procedure
The progress of technology, every a year and a half, IC quantum of output can be doubled, and be scaled cost, i.e., can reduce every a year and a half cost
Fifty percent, cost can reduce by three at more every year on average.Moore's Law is extended, IC technology promotes a generation every a year and a half.State
Border semiconductor-on-insulator manufacturer all follows this law substantially.
But maximum Intel, chip maker announces that 10 nanometers of manufacture skills will be based under postponement a few days ago in the world
The issuing time of the Cannonlake chip of art was postponed to the second half year in 2017, and the date of issue that Cannonlake chip is original
Phase is 2016.Intel company CEO Brian Krzanich is indicated in videoconference, " due to using all kinds of phases
Pass technology, and each technology has its own a series of complexity and difficulties, from 14 nanometers to 10 nanometer and from 22 nanometers
It is not the one thing to 14 nanometers.If it is desired to large-scale production, photoetching technique can be more difficult, moreover, completing Suresh Kumar step
Number can be continuously increased ".Intel follows the timetable for every two years reducing transistor volume all the time, that is, be commonly called as
" Moore's Law ", above-mentioned message enable timetable slight crack occur, and tracing it to its cause is that construction chip becomes to become increasingly complex, and power consumption is more next
It is more difficult to decrease, and various short-channel effects are difficult to overcome.
Therefore, although semiconductor technology is showing improvement or progress day by day, but is limited by physical law, and minimum dimension can not be too small, to prolong
The validity of continuous semiconductor Moore's Law, processor transistor is made of new material and is had been very urgent.At present
Have many research institutions, through the material for integrating higher performance for silicon materials, such as example, by using compound semiconductor materials
InGaAs/InP (such as InGaAsP and indium phosphide), forms the transistor of so-called broad stopband III-V channel, can promote p-
Type mobility and offer high carrier speed and high driving current, this new compound semiconductor are expected to surmount silicon materials sheet
Body performance maintains Moore's Law, realizes and continues scaled down.
But this scheme also encounters many problems at present, be primarily present of both challenge, on the one hand, silica-base material and
There are big lattice constant is poor between compound semiconductor materials such as GaAs/InP, atom between material can not be overcome brilliant always
Lattice are difficult to matched problem；On the other hand, usual Si based transistor is bonded by p channel transistor and n-channel transistor
CMOS structure applies to large scale digital field, and n-channel device is easy to accomplish usually in terms of III-V such as GaAs device, and p ditch
Road device is limited to doping engineering and epitaxial manufacture process, while the mobility of p-channel is far below n-channel, combine at present n- channel and
The GaAs transistor of p- channel cannot achieve the same circuit structure of CMOS since the two mobility differs too big (6500:300),
Greatly GaAs device is hindered in the application in digital circuit field.
Summary of the invention
It is counterfeit with heterojunction field effect transistor that the purpose of the present invention is to provide a kind of III-V CMOS type, and the field-effect is brilliant
Body pipe can well solve that existing transistor power consumption during scaled down is difficult to decrease, short-channel effect is difficult to overcome
The problem of.
To reach above-mentioned requirements, the technical solution adopted by the present invention is that: it is counterfeit with hetero-junctions to provide a kind of III-V CMOS type
Field effect transistor, including p channel transistor and n-channel transistor, p channel transistor are that AlGaSb/InGaSb pHFET is (counterfeit
With heterojunction field effect transistor), n-channel transistor is GaAspHEMT (pseudomorphic high electron mobility transistor)；P-channel is brilliant
Body pipe successively epitaxial growth the first multilayer lattice strain buffer layer, InGaSb channel layer and AlGaSb barrier layer on a silicon substrate,
One GaSb cap layers of growth regulation and the 2nd GaSb cap layers above AlGaSb barrier layer, the InGaSb channel layer and AlGaSb barrier layer
Form two-dimensional hole gas；It is formed with the first drain electrode in the first GaSb cap layers, and is formed with the first grid on AlGaSb barrier layer
Pole is formed with the first source electrode in the 2nd GaSb cap layers；N-channel transistor successively epitaxial growth in the 2nd GaSb cap layers
Two multilayer lattice strain buffer layers, InGaAs channel layer and AlGaAs barrier layer, AlGaAs barrier layer top growth regulation one
InXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers, the InGaAs channel layer and AlGaAs barrier layer form two-dimensional hole gas,
And the first InXGa1-XIt is formed with the second source electrode in As cap layers, second grid, the 2nd In are formed on AlGaAs barrier layerXGa1-XAs
The second drain electrode is formed in cap layers.The extension hetero-junctions of n-channel transistor of the present invention matches heterogeneous structure by AlGaAs/InGaAs is counterfeit
At p-channel transistor extension hetero-junctions is constituted by AlGaSb/InGaSb is counterfeit with heterogeneous.
Compared with prior art, the invention has the following advantages that
(1) counterfeit matched based on silicon substrate, the broad stopband III-V CMOS type for being integrated with n-channel transistor and p-channel transistor
Heterojunction field effect transistor can be effectively improved bring short-channel effect during transistor scaled down, and can reduce
Power consumption realizes the lasting scaled down of dimensions of semiconductor devices；
(2) AlGaSb barrier layer is formed using p-type doping, forms two-dimensional hole gas between InGaSb channel layer, can be had
Effect promotes the mobility of p channel transistor, huge to improve n-channel transistor and p-channel transistor mobility difference in III-V
The problem of；
(3) first multilayer lattice strain buffer layers can be used for absorbing between silicon-based substrate and subsequent epitaxial layer because lattice loses
Stress with generation, filter out substrate generation scattering center, avoid generate lattice relaxation, effectively overcome subsequent epitaxial layer with
Atomic lattice is difficult to the problem of matching between silicon-based substrate；
(4) second multilayer lattice strain buffer layers can be used for absorbing p channel transistor and subsequent n-channel transistor epitaxial layer
Between because lattice mismatch generate stress, avoid generate lattice relaxation；
(5) first multilayer lattice strain buffer layers and the second multilayer lattice strain buffer layer are the compound of multiple material composition
Buffer layer structure forms multiple quantum well structures due to the band difference between different materials, can effectively obstruct disconnected silicon substrate
Defect is spread to InGaSb channel layer, and the defect of the disconnected 2nd GaSb cap layers of barrier is spread to InGaAs channel layer；
(6) the first InXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers are highly doped cap, can compared with traditional cap layers
To provide better Ohmic contact for device preparation；
(7) InGaAs channel layer and AlGaAs barrier layer formation lattice are counterfeit with AlGaAs/InGaAs heterojunction structure, effectively mention
High device electronic mobility.
Detailed description of the invention
The drawings described herein are used to provide a further understanding of the present application, constitutes part of this application, at this
The same or similar part, the illustrative embodiments and their description of the application are indicated using identical reference label in a little attached drawings
For explaining the application, do not constitute an undue limitation on the present application.In the accompanying drawings:
Fig. 1 is the structural diagram of the present invention.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with drawings and the specific embodiments, to this
Application is described in further detail.For the sake of simplicity, it is omitted that well known to a person skilled in the art certain skills in being described below
Art feature.
As shown in Figure 1, the present embodiment provides a kind of III-V CMOS type it is counterfeit match heterojunction field effect transistor, use
MOCVD or MBE equipment epitaxial growth, including p channel transistor and n-channel transistor；P channel transistor is on a silicon substrate successively
Epitaxial growth the first multilayer lattice strain buffer layer, InGaSb channel layer and AlGaSb barrier layer, AlGaSb barrier layer top are raw
Long first GaSb cap layers and the 2nd GaSb cap layers, the InGaSb channel layer and the general region 5nm in AlGaSb barrier layer contact position
Two-dimensional hole gas is formed, as shown in figure 1 below shown in a dotted line；It is formed with the first drain electrode in the first GaSb cap layers, and
It is formed with first grid on AlGaSb barrier layer, the first source electrode is formed in the 2nd GaSb cap layers, first grid is located at the first leakage
Between pole and the first source electrode；N-channel transistor successively the second multilayer of epitaxial growth lattice strain in the 2nd GaSb cap layers
Buffer layer, InGaAs channel layer and AlGaAs barrier layer, AlGaAs barrier layer top one In of growth regulationXGa1-XAs cap layers 1 and
Two InXGa1-XAs cap layers 2, the general region 5nm of the InGaAs channel layer and AlGaAs barrier layer contact position form Two-Dimensional Hole
Gas, as shown in figure 1 above shown in a dotted line；And the first InXGa1-XThe second source electrode, AlGaAs barrier layer are formed in As cap layers 1
On be formed with second grid, the 2nd InXGa1-XIt is formed with the second drain electrode in As cap layers 2, second grid is located at the second drain electrode and the
Between two source electrodes.
Silicon substrate is high resistance p-type Si substrate, material Si, SiC, GaN, sapphire or diamond, mainly as branch
Timbering material.
First multilayer lattice strain buffer layer, for absorbing between silicon-based substrate and subsequent epitaxial layer material because lattice loses
Stress with generation；It undopes, with a thickness of 800~1800nm, from bottom to up first GaAs grown at low temperature buffer layer, then high growth temperature
GaAs/AlGaAs super-lattice buffer layer, then GaAs is grown using gradient-structureySb1-yAs buffer layer, regrowth GaSb/AlGaSb
Super-lattice buffer layer；The value of y is gradually reduced to 0 from 1；Al content is less than 30% in GaSb/AlGaSb super-lattice buffer layer.
InGaSb channel layer undopes, and with a thickness of 15~30nm, In content is less than 30%.
AlGaSb barrier layer for forming Schottky contacts with gate metal, and provides the freely empty of InGaSb channel layer
Cave；With a thickness of 15~40nm, Al content is less than 30%, and using p-type doping, body dopant material is Be, C or Mg, dopant dose 1
×1018cm-3~3 × 1018cm-3。
First GaSb cap layers and the 2nd GaSb cap layers, to protect AlGaSb barrier layer not oxidized, while to reduce
Ohmic contact resistance rate；With a thickness of 15~40nm, using p-type doping, body dopant material is Be, C or Mg, dopant dose is 5 ×
1018cm-3~2 × 1019cm-3。
Second multilayer lattice strain buffer layer, p channel transistor is to the buffer layer between n-channel transistor, for absorbing P
Because of the stress that lattice mismatch generates between channel transistor and subsequent n-channel transistor epitaxial layer, avoid generating lattice relaxation；
It undopes, 600~1500nm of thickness first grows GaAs using gradient-structure from bottom to upySb1-yBuffer layer, regrowth GaAs/
AlGaAs super-lattice buffer layer；The value of y is gradually upgraded to 1 from 0；Al content is less than 30% in GaAs/AlGaAs super-lattice buffer layer.
InGaAs channel layer undopes, and with a thickness of 15~30nm, In content is less than 30%；Crystalline substance is formed with AlGaAs barrier layer
Lattice are counterfeit to match AlGaAs/InGaAs heterojunction structure, to improve device electronic mobility.
AlGaAs barrier layer for forming Schottky contacts with gate metal, and provides the free hole of GaAs channel layer；
Using n-type doping, with a thickness of 15~40nm, Al content is less than 30%, using n-type doping, body adulterate the dosage of Si be 1 ×
1018cm-3~3 × 1018cm-3。
First InXGa1-XAs cap layers 1 and the 2nd InXGa1-XAs cap layers 2, to protect AlGaAs barrier layer not oxidized, together
When to reduce ohmic contact resistance rate；With a thickness of 15~40nm, wherein 0 < x < 0.5, In component x gradually rise from 0；Using n
Type doping, the dosage that body adulterates Si is 5 × 1018cm-3~2 × 1019cm-3。
Above embodiments only indicate several embodiments of the invention, and the description thereof is more specific and detailed, but can not manage
Solution is limitation of the scope of the invention.It should be pointed out that for those of ordinary skill in the art, not departing from this hair
Under the premise of bright design, various modifications and improvements can be made, these belong to the scope of the present invention.Therefore of the invention
Protection scope should be subject to claim.
Claims (9)
1. a kind of III-V CMOS type is counterfeit to match heterojunction field effect transistor, which is characterized in that including p channel transistor and n ditch
Road transistor；P channel transistor successively epitaxial growth the first multilayer lattice strain buffer layer, InGaSb channel layer on a silicon substrate
And AlGaSb barrier layer, AlGaSb barrier layer top one GaSb cap layers of growth regulation and the 2nd GaSb cap layers, the InGaSb channel
Layer forms two-dimensional hole gas with AlGaSb barrier layer；The first drain electrode, and AlGaSb potential barrier are formed in the first GaSb cap layers
It is formed with first grid on layer, is formed with the first source electrode in the 2nd GaSb cap layers；N-channel transistor is in the 2nd GaSb cap layers
On successively epitaxial growth the second multilayer lattice strain buffer layer, InGaAs channel layer and AlGaAs barrier layer, AlGaAs barrier layer
One In of top growth regulationXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers, the InGaAs channel layer and AlGaAs barrier layer shape
At two-dimensional hole gas, and the first InXGa1-XIt is formed with the second source electrode in As cap layers, is formed with second gate on AlGaAs barrier layer
Pole, the 2nd InXGa1-XThe second drain electrode is formed in As cap layers；
The first multilayer lattice strain buffer layer undopes, with a thickness of 800~1800nm, first GaAs grown at low temperature from bottom to up
Buffer layer, then high growth temperature GaAs/AlGaAs super-lattice buffer layer, then GaAs is grown using gradient-structureySb1-yAs buffer layer,
Regrowth GaSb/AlGaSb super-lattice buffer layer；The value of y is gradually reduced to 0 from 1；Al contains in GaSb/AlGaSb super-lattice buffer layer
Amount is less than 30%.
2. III-V CMOS type according to claim 1 is counterfeit to match heterojunction field effect transistor, which is characterized in that the silicon
Substrate is high resistance p-type Si substrate.
3. III-V CMOS type according to claim 1 is counterfeit to match heterojunction field effect transistor, which is characterized in that described
InGaSb channel layer undopes, and with a thickness of 15~30nm, In content is less than 30%.
4. III-V CMOS type according to claim 1 is counterfeit to match heterojunction field effect transistor, which is characterized in that described
AlGaSb barrier layer thickness is 15~40nm, and Al content is less than 30%, and using p-type doping, body dopant material is Be, C or Mg, is mixed
Miscellaneous dosage is 1 × 1018cm-3~3 × 1018cm-3。
5. III-V CMOS type according to claim 1 is counterfeit to match heterojunction field effect transistor, which is characterized in that described the
One GaSb cap layers and the 2nd GaSb cap layers with a thickness of 15~40nm, using p-type doping, body dopant material is Be, C or Mg, is mixed
Miscellaneous dosage is 5 × 1018cm-3~2 × 1019cm-3。
6. III-V CMOS type according to claim 1 is counterfeit to match heterojunction field effect transistor, which is characterized in that described the
Two multilayer lattice strain buffer layers undope, 600~1500nm of thickness, are first grown from bottom to up using gradient-structure
GaAsySb1-yBuffer layer, regrowth GaAs/AlGaAs super-lattice buffer layer；The value of y is gradually upgraded to 1 from 0；GaAs/AlGaAs is super
Al content is less than 30% in buffer layer lattice.
7. counterfeit with heterojunction field effect transistor, feature according to III-V CMOS type described in any claim of claim 3-6
It is, the InGaAs channel layer undopes, and with a thickness of 15~30nm, In content is less than 30%.
8. counterfeit with heterojunction field effect transistor, feature according to III-V CMOS type described in any claim of claim 3-6
Be, the AlGaAs barrier layer with a thickness of 15~40nm, Al content is less than 30%, and using n-type doping, body adulterates the agent of Si
Amount is 1 × 1018cm-3~3 × 1018cm-3。
9. counterfeit with heterojunction field effect transistor, feature according to III-V CMOS type described in any claim of claim 3-6
It is, the first InXGa1-XAs cap layers and the 2nd InXGa1-XAs cap layers with a thickness of 15~40nm, In component x=0~0.5,
And In component x gradually rises from 0；Using n-type doping, the dosage that body adulterates Si is 5 × 1018cm-3~2 × 1019cm-3。
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| CN201710192961.0A CN106952952B (en) | 2017-03-28 | 2017-03-28 | A kind of III-V CMOS type is counterfeit to match heterojunction field effect transistor |
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| JPH11186665A (en) * | 1997-12-25 | 1999-07-09 | Sony Corp | Semiconductor light emitting element |
| CN1797787A (en) * | 2004-12-30 | 2006-07-05 | 中国科学院半导体研究所 | Structure for improving Schottky performance of grid electrode of gallium nitride based transistor in high electron mobility |
| CN102054862A (en) * | 2009-10-28 | 2011-05-11 | 中国科学院半导体研究所 | Antimonide transistor with high electron mobility and manufacturing method thereof |
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| CN103258796A (en) * | 2013-05-14 | 2013-08-21 | 中国科学院半导体研究所 | Method for manufacturing silicon-substrate high-migration-rate channel CMOS |
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| JPH11186665A (en) * | 1997-12-25 | 1999-07-09 | Sony Corp | Semiconductor light emitting element |
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