CN115274826B - Pseudo-matched high electron mobility transistor, epitaxial structure and preparation method - Google Patents
Pseudo-matched high electron mobility transistor, epitaxial structure and preparation method Download PDFInfo
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Abstract
The invention provides a pseudo-matched high electron mobility transistor, an epitaxial structure and a preparation method thereof, wherein a composite buffer layer can fully prevent defects of a substrate from extending to a channel in a shorter growth time, so that the quality of a device is enhanced; the InGaAs composite channel layer is gradually changed In composition and thickness, so that the content of In the InGaAs channel is increased to the greatest extent, and good two-dimensional electron gas limitation is formed, so that the two-dimensional electron gas concentration and mobility are improved, and the quality of the device is further enhanced; the doping efficiency of Si can be improved by introducing AlAs thin layers and the change of the growth rate of GaAs materials into the pulse doping layers, the adsorption of impurities is effectively reduced, and the two-dimensional electron gas concentration in a channel is further improved; the composite buffer layer and the composite channel layer are grown by using a growth interruption method, so that high-quality growth of different materials is realized, smooth transition of band gaps among layers is realized, rough scattering of interfaces and disordered scattering of alloys are reduced, the concentration of two-dimensional electron gas in the channel layer is further improved, and the performance of a device is further enhanced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a pseudo-matched high electron mobility transistor, an epitaxial structure and a preparation method.
Background
Gallium arsenide is used as a mature compound semiconductor material, has higher breakdown voltage and is widely applied to ultra-high-speed and ultra-high-frequency devices. Gallium arsenide-based Pseudomorphic High Electron Mobility Transistor (PHEMT) has the characteristics of high frequency, high power gain, low noise and the like, and is widely applied to the communication fields of optical fiber communication, microwave communication, satellite communication and the like and integrated circuits. The quality of the epitaxial structure in gallium arsenide based PHEMT plays a decisive role in the important properties of the final product.
In the existing PHEMT epitaxial structure, an AlGaAs buffer layer and an InGaAs channel layer are mainly grown on a substrate, on one hand, defects of the substrate extend to the channel so as to influence the quality of a barrier layer and the channel layer, and further influence the quality of a device; on the other hand, electron traps are formed at the heterostructure interface of AlGaAs/InGaAs to form two-dimensional electron gas (2 DEG), and the mobility of the two-dimensional electron gas also has a certain influence on the device.
Along with the popularization of products in the fields of satellite communication, microwave communication and the like and the development of various functions, the gallium arsenide-based pseudomorphic high electron mobility transistor has higher and higher requirements on epitaxial structure growth, and how to prevent the defects of a substrate from extending to a barrier layer and a channel layer and improve the mobility of two-dimensional electron gas in the channel at the same time, so that the GaAs PHEMT device comprises transconductance gm and current gain cut-off frequency f T Maximum oscillation frequency f max Minimum noise figure F min Radio frequency performance parameters including power conversion efficiency and the like are the subject of current research.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pseudo-high electron mobility transistor, an epitaxial structure and a preparation method thereof, which are used for solving the problem that defects of a substrate in the epitaxial structure extend to a barrier layer and a channel layer in the prior art, and the mobility of two-dimensional electron gas in the channel layer is low, thereby influencing the performance of a PHEMT device.
To achieve the above and other related objects, the present invention provides an epitaxial structure of a pseudomorphic high electron mobility transistor, comprising:
the AlGaAs/GaAs composite buffer layer, the first AlGaAs barrier layer, the InGaAs composite channel layer, the AlGaAs isolation layer, the pulse doping layer, the second AlGaAs barrier layer, the first corrosion stop layer, the GaAs cap layer, the second corrosion stop layer and the composite cap layer are sequentially stacked on one side of the substrate from bottom to top;
wherein the AlGaAs/GaAs composite buffer layer is made of Al y Ga 1-y The superlattice structure formed by the As layer and the GaAs layer, and the composition of Al is increased from bottom to top;
the InGaAs composite channel layer is formed by In z Ga 1-z A superlattice structure composed of As, wherein the superlattice structure comprises a GaAs channel layer with z value of 0 at the upper end and the lower end, and an In component between the GaAs channel layers presents increasing change from bottom to top and has gradually changed thicknessIn of (a) z Ga 1-z An As channel layer.
Optionally, the AlGaAs/GaAs composite buffer layer includes a first composite buffer layer, a second composite buffer layer, a third composite buffer layer and a fourth composite buffer layer stacked in sequence from bottom to top, where the value of the component y of Al is 0 to 0.3.
Optionally, the first composite buffer layer is a GaAs buffer layer with a thickness ranging from 200 nm to 500nm, and the second composite buffer layer is Al 0.1 Ga 0.9 An As/GaAs buffer layer, wherein the superlattice period of the second composite buffer layer is 5 and Al 0.1 Ga 0.9 The thickness range of the As layer is 8-10 nm, the thickness range of the GaAs layer is 2-3 nm, and the third composite buffer layer is Al 0.17 Ga 0.83 An As/GaAs buffer layer, wherein the superlattice period of the third composite buffer layer is 5 and Al 0.17 Ga 0.83 The thickness range of the As layer is 8-10 nm, the thickness range of the GaAs layer is 2-3 nm, and the fourth composite buffer layer is Al 0.24 Ga 0.76 An As/GaAs buffer layer, wherein the superlattice period of the fourth composite buffer layer is 5 and Al 0.24 Ga 0.76 The thickness of the As layer ranges from 8nm to 10nm, and the thickness of the GaAs layer ranges from 2nm to 3nm.
Alternatively, the first AlGaAs barrier layer and the second AlGaAs barrier layer are denoted as Al x Ga 1-x As, wherein the value of the component x of Al is 0.2-0.3, the thickness range of the first AlGaAs barrier layer is 20-50 nm, and the thickness range of the second AlGaAs barrier layer is 15-30 nm.
Optionally, the InGaAs composite channel layer includes a first GaAs channel layer, a second InGaAs channel layer, a third InGaAs channel layer, a fourth InGaAs channel layer, a fifth InGaAs channel layer, and a sixth GaAs channel layer from bottom to top, where the component z of In has a value of 0 to 0.5.
Optionally, the thickness of the first GaAs channel layer and the sixth GaAs channel layer is 1-2 nm, and the second InGaAs channel layer is In 0.1 Ga 0.9 An As layer with a thickness ranging from 3 to 4nm, the third InGaAs channel layer being In 0.15 Ga 0.85 The layer of As is formed of an As,the thickness range is 1.5-2 nm, the fourth InGaAs channel layer is In 0.2 Ga 0.8 An As layer with a thickness ranging from 1 to 1.5nm, the fifth InGaAs channel layer being In 0.5 Ga 0.5 As layer, its thickness range is 0.5-1 nm.
Optionally, the pulse doping layer comprises a GaAs pulse doping layer and an AlAs pulse doping layer which are doped with Si, wherein the Si doping concentration of the GaAs pulse doping layer is 5-6E 12cm -2 The thickness range is 0.5-2 nm, and the thickness range of the AlAs pulse doped layer is 0.5-1 nm.
Optionally, the first corrosion stop layer and the second corrosion stop layer comprise AlAs corrosion stop layers, and the thickness ranges of the first corrosion stop layer and the second corrosion stop layer are respectively 0.5-1.5 nm.
Optionally, the composite cap layer comprises a high Si doped composite GaAs cap layer and a composite In which are stacked In sequence from bottom to top m Ga 1-m The As cap layer, wherein the doping concentration of Si in the composite GaAs cap layer is 0.5-1.5E19 cm -2 The thickness of the composite GaAs cap layer ranges from 30nm to 50nm, and the composite In m Ga 1-m The thickness range of the As cap layer is 10-20 nm, and the value of the component m of In is 0.15-0.25.
The invention also provides a preparation method of the epitaxial structure of the pseudo-matched high electron mobility transistor, which comprises the following steps:
1) Providing a substrate;
2) Forming an AlGaAs/GaAs composite buffer layer on one side of the substrate by a growth interruption method, and growing a first AlGaAs barrier layer on the AlGaAs/GaAs composite buffer layer;
3) Growing an InGaAs composite channel layer on the first AlGaAs barrier layer by a growth interruption method, wherein the growth interruption time is 3-5 seconds;
4) Reducing the temperature of a Ga source furnace, and growing an AlGaAs isolation layer on the InGaAs composite channel layer;
5) Growing a pulse doping layer on the AlGaAs isolating layer;
6) Continuously growing a second AlGaAs barrier layer on the pulse doping layer;
7) Growing a first corrosion stop layer on the second AlGaAs barrier layer by a growth interruption method, wherein the growth interruption time of the first corrosion stop layer is 2-3 seconds;
8) And continuously growing a GaAs cap layer, a second corrosion stop layer and a composite cap layer on the first corrosion stop layer.
The invention also provides a pseudo-matched high electron mobility transistor, which comprises a transistor main body, wherein any epitaxial structure is arranged on the transistor main body.
The invention provides a pseudo-matched high electron mobility transistor, an epitaxial structure and a preparation method, which have the following beneficial effects:
1. by introducing the composite buffer layer, the defect of the substrate is fully prevented from extending to the channel in a short growth time, the quality of the barrier layer and the channel layer adjacent to the buffer layer is ensured, and the influence of the defect of the substrate on the performance of the device is further weakened.
2. Through the structure of the InGaAs composite channel layer with the In component and the gradual change of each layer thickness, the In content In the InGaAs channel is increased to the maximum extent under the condition of not introducing dislocation and big lattice mismatch, and good two-dimensional electron gas limitation is formed, so that the two-dimensional electron gas concentration and mobility are improved, and the performance of the device is further enhanced.
3. By introducing the Si-doped GaAs pulse doping layer and the AlAs pulse doping layer into the pulse doping layer, the adsorption of impurities can be effectively reduced, the change of the growth rate of the GaAs pulse doping layer can also improve the doping efficiency of Si, and the two-dimensional electron gas concentration in a channel is further improved.
4. By introducing the double corrosion stop layer and the high silicon doped composite cap layer, the source-drain resistance is effectively reduced, and the gate leakage and gate-drain breakdown voltage of the PHEMT device are improved.
5. The composite buffer layer and the composite channel layer are grown by using a growth interruption method, so that high-quality growth of different materials is realized, smooth transition of band gaps among layers is realized, rough scattering of interfaces and disordered scattering of alloys are reduced, the concentration of two-dimensional electron gas in the channel layer is further improved, and the performance of a device is further enhanced.
Drawings
FIG. 1 is a schematic diagram of an epitaxial structure of a pseudomorphic HEMT of the present invention;
FIG. 2 is a schematic view showing the structure of an AlGaAs/GaAs composite buffer layer with an epitaxial structure in an embodiment of the present invention;
fig. 3 is a schematic diagram of an InGaAs composite channel layer in an epitaxial structure in accordance with an embodiment of the present invention;
fig. 4 shows a schematic diagram of conduction band energy levels of an InGaAs composite channel layer in an epitaxial structure in an embodiment of the invention;
FIG. 5 is a schematic diagram showing the structure of a pulse doped layer of an epitaxial structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a high silicon doped composite cap layer with an epitaxial structure according to an embodiment of the present invention;
fig. 7 is a flow chart of a method for fabricating an epitaxial structure of a pseudomorphic hemt of the present invention.
Description of element reference numerals
10. Substrate and method for manufacturing the same
20 AlGaAs/GaAs composite buffer layer
201. First composite buffer layer
202. Second composite buffer layer
203. Third composite buffer layer
204. Fourth composite buffer layer
30. First AlGaAs barrier layer
40 InGaAs composite channel layer
401. First GaAs channel layer
402. Second InGaAs channel layer
403. Third InGaAs channel layer
404. Fourth InGaAs channel layer
405. Fifth InGaAs channel layer
406. Sixth GaAs channel layer
50 AlGaAs isolation layer
60. Pulse doped layer
601 GaAs pulse doped layer
602 AlAs pulse doped layer
70. Second AlGaAs barrier layer
80. First corrosion cut-off layer
90 GaAs cap layer
100. Second corrosion stop layer
110. Composite cap layer
1101. Composite GaAs cap layer
1102. Composite InGaAs cap layer
S1-S8 Steps 1) -8)
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
It should be understood that the terms "first," "second," "third," and the like are used for defining the components, and are merely for convenience in distinguishing the components from each other, and the terms have no special meaning unless otherwise stated, so that they should not be construed as limiting the scope of the present invention.
Please refer to fig. 1 to 7. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1 to 7, the present invention provides an epitaxial structure of a pseudomorphic high electron mobility transistor and a method for manufacturing the same, the epitaxial structure comprising: a substrate 10; and an AlGaAs/GaAs composite buffer layer 20, a first AlGaAs barrier layer 30, an InGaAs composite channel layer 40, an AlGaAs isolation layer 50, a pulse doped layer 60, a second AlGaAs barrier layer 70, a first corrosion stop layer 80, a GaAs cap layer 90, a second corrosion stop layer 100, and a composite cap layer 110 which are stacked in this order from bottom to top on one side of the substrate 10; wherein the AlGaAs/GaAs composite buffer layer 20 has a superlattice structure composed of an AlyGa1-yAs layer and a GaAs layer, and the Al component is increasingly changed from bottom to top; the InGaAs composite channel layer 40 is a superlattice structure composed of InzGa1-zAs, and includes GaAs channel layers with z values of 0 at the upper and lower ends, and InzGa1-zAs channel layers with In components between the GaAs channel layers exhibiting increasing and varying thickness from bottom to top.
As an example, the AlGaAs/GaAs composite buffer layer 20 includes a first composite buffer layer 201, a second composite buffer layer 202, a third composite buffer layer 203, and a fourth composite buffer layer 204 stacked in this order from bottom to top, wherein the value of the component y of Al is 0 to 0.3, which may be 0.1, 0.17, or 0.24, for example.
Specifically, as shown in step S2 of fig. 2 and 7, in this embodiment, the AlGaAs/GaAs composite buffer layer 20 includes a first composite buffer layer 201, a second composite buffer layer 202, a third composite buffer layer 203 and a fourth composite buffer layer 204 sequentially stacked from bottom to top on the substrate, where the first composite buffer layer 201 is a GaAs buffer layer, and the second composite buffer layer 202, the third composite buffer layer 203 and the fourth composite buffer layer 204 are all made of Al y Ga 1-y The superlattice structure is composed of an As layer and a GaAs layer, wherein the value of the component y of Al is 0-0.3, and the Al components in the second composite buffer layer 202, the third composite buffer layer 203 and the fourth composite buffer layer 204 are required to meet incremental changes. Of course, the design of the AlGaAs/GaAs composite buffer layer 20 is not limited thereto, and may be changed adaptively as needed.
As an example, the first composite buffer layer 201 is a GaAs buffer layer and has a thickness ranging from 200 to 500nm, and the second composite buffer layer 202 is Al 0.1 Ga 0.9 An As/GaAs buffer layer, wherein the superlattice period of the second composite buffer layer 202 is 5 and Al 0.1 Ga 0.9 The thickness of the As layer ranges from 8nm to 10nm, the thickness of the GaAs layer ranges from 2nm to 3nm, and the third composite buffer layer 203 is Al 0.17 Ga 0.83 An As/GaAs buffer layer, wherein the superlattice period of the third composite buffer layer 203 is 5 and Al 0.17 Ga 0.83 The thickness of the As layer ranges from 8nm to 10nm, the thickness of the GaAs layer ranges from 2nm to 3nm, and the fourth composite buffer layer 204 is Al 0.24 Ga 0.76 An As/GaAs buffer layer, wherein the superlattice period of the fourth composite buffer layer 204 is 5 and Al 0.24 Ga 0.76 The thickness of the As layer ranges from 8nm to 10nm, and the thickness of the GaAs layer ranges from 2nm to 3nm.
Specifically, as shown in fig. 2, in the present embodiment, the first composite buffer layer 201 is a GaAs buffer layer with a thickness ranging from 200 to 500nm, and in the present embodiment, the GaAs buffer layer preferably has a thickness of 300nm, and the second composite buffer layer 202 is Al 0.1 Ga 0.9 An As/GaAs buffer layer, the third composite buffer layer 203 is Al 0.17 Ga 0.83 The As/GaAs buffer layer and the fourth composite buffer layer 204 are Al 0.24 Ga 0.76 An As/GaAs buffer layer, wherein the superlattice periods of the second composite buffer layer 202, the third composite buffer layer 203, and the fourth composite buffer layer 204 are all 5 and the thickness of the AlGaAs layer is preferably 8nm and the thickness of the GaAs layer is preferably 2nm in the present embodiment. Of course, the designs of the first composite buffer layer 201, the second composite buffer layer 202, the third composite buffer layer 203, and the fourth composite buffer layer 204 are not limited thereto, and may be changed adaptively as needed.
As an example, the first AlGaAs barrier layer 30 and the second AlGaAs barrier layer 70 are compositionally denoted as Al x Ga 1-x As, wherein the Al component x has a value of 0.2 to 0.3, for example, 0.2, 0.25 or 0.3, the first AlGaAs barrier layer 30 has a thickness in the range of 20nm to 50nm, for example, 20nm, 35nm or 50nm, and the second AlGaAs barrier layer 70 has a thickness in the range of 15nm to 30nm, for example, 15nm, 20nm, 25nm or 30nm.
Specifically, as shown in step S2 of fig. 1 and 7, in the present embodiment, a first AlGaAs barrier layer 30 is formed on the AlGaAs/GaAs composite buffer layer 20 formed on one side of the substrate 10, and the composition of the first AlGaAs barrier layer 30 is denoted as Al 0.2 Ga 0.8 As, the thickness of the first AlGaAs barrier layer 30 is preferably 35nm.
In the present embodiment, as shown in step S6 of fig. 1 and 7, a second AlGaAs barrier layer 70 is grown on the pulse doped layer 60, and the composition of the second AlGaAs barrier layer 70 is denoted as Al 0.25 Ga 0.75 As, the thickness of the second AlGaAs barrier layer 70 is preferably 20nm. Of course, regarding the design of the first AlGaAs barrier layer 30 and the second AlGaAs barrier layer 70Without limitation, adaptation may be performed as needed.
As an example, the InGaAs composite channel layer 40 includes a first GaAs channel layer 401, a second InGaAs channel layer 402, a third InGaAs channel layer 403, a fourth InGaAs channel layer 404, a fifth InGaAs channel layer 405, and a sixth GaAs channel layer 406 from bottom to top, where the component z of In has a value of 0 to 0.5, which may be 0, 0.1, 0.3, or 0.5, for example.
Specifically, as shown in step S3 of fig. 3 and fig. 7, an InGaAs composite channel layer 40 is grown on the side of the first AlGaAs barrier layer 30 facing away from the substrate 10 by a growth interruption method, where the InGaAs composite channel layer 40 includes the first GaAs channel layer 401, the second InGaAs channel layer 402, the third InGaAs channel layer 403, the fourth InGaAs channel layer 404, the fifth InGaAs channel layer 405 and the sixth GaAs channel layer 406, which are grown layer by layer from bottom to top, i.e. each layer of the InGaAs composite channel layer 40 is grown by a growth interruption method, where the interruption growth time is 3 to 5 seconds, for example, may be 4 seconds. The In composition In the second InGaAs channel layer 402, the third InGaAs channel layer 403, the fourth InGaAs channel layer 404, and the fifth InGaAs channel layer 405 shows increasing variation and thickness gradation. Of course, the design of the InGaAs composite channel layer 40 is not limited thereto, and may be changed adaptively as needed.
By way of example, the first GaAs channel layer 401 and the sixth GaAs channel layer 406 are GaAs layers having a thickness In the range of 1-2 nm, and the second InGaAs channel layer 402 is In 0.1 Ga 0.9 An As layer having a thickness In the range of 3-4 nm, the third InGaAs channel layer 403 being In 0.15 Ga 0.85 An As layer having a thickness In the range of 1.5-2 nm, the fourth InGaAs channel layer 404 being In 0.2 Ga 0.8 An As layer having a thickness In the range of 1-1.5 nm, the fifth InGaAs channel layer 405 being In 0.5 Ga 0.5 As layer, its thickness range is 0.5-1 nm.
Specifically, as shown in fig. 3, in the present embodiment, the first GaAs channel layer 401 and the sixth GaAs channel layer 406 are GaAs layers each having a thickness of 1nm, and the second InGaAsChannel layer 402 is In 0.1 Ga 0.9 An As layer having a thickness of 4nm, the third InGaAs channel layer 403 being In 0.15 Ga 0.85 An As layer having a thickness of 2nm, the fourth InGaAs channel layer 404 being In 0.2 Ga 0.8 An As layer having a thickness of 1.5nm, the fifth InGaAs channel layer 405 being In 0.5 Ga 0.5 As layer, its thickness is 1nm. Of course, the designs of the first GaAs channel layer 401, the second InGaAs channel layer 402, the third InGaAs channel layer 403, the fourth InGaAs channel layer 404, and the fifth InGaAs channel layer 405 are not limited thereto, and may be changed adaptively as needed.
In the embodiment of the present invention, as shown In fig. 4, the conduction band energy level of the InGaAs composite channel layer 40 of the epitaxial structure is shown In fig. 4, the design of increasing variation of In component In the InGaAs composite channel layer 40 makes the conduction band energy lowest at the interface between the InGaAs composite channel layer 40 and the AlGaAs isolation layer 50, so that electrons In the channel layer are more concentrated In the third InGaAs channel layer 403 with higher In component In the middle, and far away from the interface between the InGaAs composite channel layer 40 and the AlGaAs isolation layer 50, therefore, the influence of the scattering of electrons In the layer is less due to the interface, and the structural design of the first GaAs channel layer 401 and the sixth GaAs channel layer 406 with lower In component on both sides is adopted, so that the first GaAs channel layer 401 and the sixth GaAs channel layer 406 with lower In component on both sides can play a role of buffering, and the risk of crystal defects due to lattice mismatch In the middle InGaAs composite channel layer 40 is reduced.
By way of example, the pulse doped layer 60 includes a Si-doped GaAs pulse doped layer 601 and an AlAs pulse doped layer 602, wherein the Si doping concentration of the GaAs pulse doped layer 601 is 5 to 6E12cm -2 The thickness range is 0.5-2 nm, and the thickness range of the AlAs pulse doped layer 602 is 0.5-1 nm.
As shown in step S5 of fig. 5 and 7, a pulse doped layer 60 is grown on the AlGaAs spacer 50 by controlling a low growth rate, the pulse doped layer 60 including the Si doped GaAs pulse doped layer 601 adjacent to the AlGaAs spacer 50 and the one remote from the AlGaAs spacer 50The introduction of the AlAs pulse doped layer 602 and the change of the growth rate of the AlAs pulse doped layer 602 can effectively reduce the adsorption of impurities, thereby improving the doping efficiency of Si to further improve the two-dimensional electron gas concentration in the InGaAs composite channel layer 40. Specifically, in the present embodiment, the Si doping concentration of the GaAs pulse doped layer 601 is 5E12cm -2 And has a thickness of 2nm, and the AlAs pulse doped layer 602 has a thickness of 0.5nm. Of course, the design of the pulse doped layer 60 is not limited thereto, and may be adaptively changed as needed.
As an example, the first and second corrosion- cut layers 80 and 100 include AlAs corrosion-cut layers, and the thickness of the first and second corrosion- cut layers 80 and 100 ranges from 0.5 to 1.5nm, respectively, and may be 0.5nm, 1nm, or 1.5nm, for example.
As shown in step S7 and step S8 of fig. 1 and 7, a first etch stop layer 80 is grown on the second AlGaAs barrier layer 70 by a growth interruption method, wherein the growth interruption time of the first etch stop layer 80 is 2 to 3 seconds, and the first etch stop layer 80 is an AlAs etch stop layer and has a thickness of 1nm; a GaAs cap layer 90 and a second etch stop layer 100 were continued to be grown on the first etch stop layer 80, the second etch stop layer 100 also being AlAs etch stop layer and having a thickness of 1.5nm. By introducing the first etch stop layer 80 and the second etch stop layer 100, the source-drain resistance can be effectively reduced, effectively improving the gate-drain breakdown voltage of the PHEMT device. Of course, the designs of the first corrosion cut-off layer 80 and the second corrosion cut-off layer 100 are not limited thereto, and may be adaptively changed as needed.
As an example, the composite cap layer 110 includes a high Si doped composite GaAs cap layer 1101 and a composite In stacked In order from bottom to top m Ga 1-m An As cap layer 1102, wherein the Si doping concentration in the composite GaAs cap layer 1101 is 0.5-1.5E19 cm -2 And the thickness of the composite GaAs cap layer 1101 is In the range of 30-50 nm, and the composite In m Ga 1-m The As cap layer 1102 has a thickness In the range of 10 to 20nm and a value of In component m of 0.15 to 0.25, for example, 0.15. 0.2 or 0.25.
As shown In step S8 of fig. 6 and 7, a composite cap layer 110 is grown on the second etch stop layer 100, the composite cap layer 110 including the high Si doped composite GaAs cap layer 1101 adjacent to the second etch stop layer 100 and the high Si doped composite In remote from the second etch stop layer 100 0.2 Ga 0.8 An As cap layer 1102, wherein the silicon doping concentration in the composite cap layer 110 is 1.5E19cm -2 And the thickness of the composite GaAs cap layer 1101 is 40nm, the composite In 0.2 Ga 0.8 The As cap layer 1102 has a thickness in the range of 20nm. Of course, the design of the high silicon doped composite cap layer 110 is not limited thereto, and may be adapted as needed.
Based on the same conception, the embodiment of the invention also provides a preparation method of the epitaxial structure of the pseudo-matched high electron mobility transistor, and the method can be used for forming the epitaxial structure. Fig. 7 is a flow chart of a method for preparing an epitaxial structure of a pseudo-matching high electron mobility transistor according to an embodiment of the present invention, where the method in this embodiment includes the following steps:
1) Providing a substrate 10;
2) Forming an AlGaAs/GaAs composite buffer layer 20 on one side of the substrate 10 by a growth interruption method, and growing a first AlGaAs barrier layer 30 on the AlGaAs/GaAs composite buffer layer;
3) Growing an InGaAs composite channel layer 40 on the first AlGaAs barrier layer 30 by a growth interruption method, wherein the growth interruption time is 3-5 seconds;
4) Reducing the temperature of the Ga source furnace, and growing an AlGaAs isolation layer 50 on the InGaAs composite channel layer 40;
5) Growing a pulse doped layer 60 on the AlGaAs spacer layer 50;
6) Continuing to grow a second AlGaAs barrier layer 70 on the pulse doped layer 60;
7) Growing a first corrosion stop layer 80 on the second AlGaAs barrier layer 70 by a growth interruption method, wherein the growth interruption time of the first corrosion stop layer 80 is 2-3 seconds;
8) A GaAs cap layer 90, a second etch stop layer 100, and a composite cap layer 110 continue to be grown over the first etch stop layer 80.
Specifically, in step S1, a substrate 10 is provided, where the substrate 10 includes, but is not limited to, a sapphire substrate, a silicon carbide substrate, an aluminum nitride substrate, a gallium nitride substrate, and a composite substrate composed of silicon dioxide and sapphire, and in this embodiment, a semi-insulating GaAs substrate is used as the substrate 10 for the epitaxial structure growth.
Specifically, in step S2, an AlGaAs/GaAs composite buffer layer 20 and a first AlGaAs barrier layer 30 are formed on one side of the substrate 10; the AlGaAs/GaAs composite buffer layer 20 includes the first composite buffer layer 201, the second composite buffer layer 202, the third composite buffer layer 203 and the fourth composite buffer layer 204, and the first composite buffer layer 201, the second composite buffer layer 202, the third composite buffer layer 203 and the fourth composite buffer layer 204 are superlattice structures composed of an aiyga 1-yAs layer and a GaAs layer, wherein the value of the component y of Al is 0-0.3.
Specifically, in step S3, an InGaAs composite channel layer 40 is grown on the first AlGaAs barrier layer 30 by a growth interruption method, where the InGaAs composite channel layer 40 includes, from top to bottom, the first GaAs channel layer 401, the second InGaAs channel layer 402, the third InGaAs channel layer 403, the fourth InGaAs channel layer 404, the fifth InGaAs channel layer 405 and the sixth GaAs channel layer 406, which are grown layer by layer, in sequence, i.e., each layer in the InGaAs composite channel layer 40 is grown by a growth interruption method, where the interruption growth time is 3 to 5 seconds.
Specifically, in step S4, the temperature of the Ga source furnace is reduced, and an AlGaAs isolation layer 50 is grown on the InGaAs composite channel layer 40;
specifically, in step S5, a pulse doped layer 60 is grown on the AlGaAs isolation layer 50, the pulse doped layer 60 including the Si doped GaAs pulse doped layer 601 adjacent to the AlGaAs isolation layer 50 and the AlAs pulse doped layer 602 distant to the AlGaAs isolation layer 50;
specifically, in step S7, a first corrosion stop layer 80 is grown on the second AlGaAs barrier layer 70 by a growth interruption method, and the growth interruption time of the first corrosion stop layer is 2 to 3 seconds; the epitaxial structure is formed by Molecular Beam Epitaxy (MBE) or Metal Organic Chemical Vapor Deposition (MOCVD) between layers.
The embodiment of the invention also provides a pseudo-matching high electron mobility transistor, which comprises a transistor main body, wherein any epitaxial structure is arranged on the transistor main body.
In summary, the present invention provides a pseudo-high electron mobility transistor, an epitaxial structure and a method for manufacturing the same, wherein the epitaxial structure includes a substrate; the AlGaAs/GaAs composite buffer layer, the first AlGaAs barrier layer, the InGaAs composite channel layer, the AlGaAs isolation layer, the pulse doping layer, the second AlGaAs barrier layer, the first corrosion stop layer, the GaAs cap layer, the second corrosion stop layer and the composite cap layer are sequentially stacked on one side of the substrate from bottom to top; wherein the AlGaAs/GaAs composite buffer layer is made of Al y Ga 1-y The superlattice structure formed by the As layer and the GaAs layer, and the composition of Al is increased from bottom to top; the InGaAs composite channel layer is formed by In z Ga 1-z A superlattice structure composed of As, wherein the superlattice structure comprises a GaAs channel layer with z value of 0 at the upper end and the lower end, and In with increased variation and gradual thickness is presented from bottom to top between the GaAs channel layers z Ga 1-z An As channel layer. By introducing the AlGaAs/GaAs composite buffer layer, the defect of the substrate is fully prevented from extending to the channel in a shorter growth time, the quality of the barrier layer and the channel layer adjacent to the buffer layer is ensured, and the influence of the defect of the substrate on the performance of the device is further weakened; through the structure of the InGaAs composite channel layer with the In component and the gradual change of each layer thickness, the In content In the InGaAs channel is increased to the maximum extent under the condition of not introducing dislocation and big lattice mismatch, and good two-dimensional electron gas limitation is formed, so that the two-dimensional electron gas concentration and mobility are improved, and the performance of the device is further enhanced; by introducing the Si-doped GaAs pulse doping layer and the AlAs pulse doping layer into the pulse doping layer, the adsorption of impurities can be effectively reduced, and the growth rate of the GaAs pulse doping layer is changedThe doping efficiency of Si can be improved, and the two-dimensional electron gas concentration in the channel layer is further improved; by introducing the double corrosion stop layer and the high Si doped composite cap layer, the source-drain resistance is effectively reduced, and the gate leakage and gate-drain breakdown voltage of the PHEMT device are improved; the AlGaAs/GaAs composite buffer layer and the composite channel layer are grown by using a growth interruption method, so that high-quality growth of different materials is realized, smooth transition of band gaps among layers is realized, rough scattering of interfaces and disordered scattering of alloys are further reduced, and the two-dimensional electron gas concentration in the channel layer is further improved, thereby enhancing the performance of the device. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. An epitaxial structure of a pseudomorphic high electron mobility transistor, the epitaxial structure comprising:
a substrate; and
the AlGaAs/GaAs composite buffer layer, the first AlGaAs barrier layer, the InGaAs composite channel layer, the AlGaAs isolation layer, the pulse doping layer, the second AlGaAs barrier layer, the first corrosion stop layer, the GaAs cap layer, the second corrosion stop layer and the composite cap layer are sequentially stacked on one side of the substrate from bottom to top;
wherein the AlGaAs/GaAs composite buffer layer is made of Al y Ga 1-y The superlattice structure formed by the As layer and the GaAs layer, and the composition of Al is increased from bottom to top;
the InGaAs composite channel layer comprises a first GaAs channel layer, a second InGaAs channel layer, a third InGaAs channel layer, a fourth InGaAs channel layer, a fifth InGaAs channel layer and a third InGaAs channel layer from bottom to topA sixth GaAs channel layer, in between the first GaAs channel layer and the sixth GaAs channel layer, in having an increasing composition and a decreasing thickness, being present from bottom to top z Ga 1-z And an As channel layer, wherein the value of the component z of In is 0-0.5.
2. The epitaxial structure of claim 1, wherein: the AlGaAs/GaAs composite buffer layer comprises a first composite buffer layer, a second composite buffer layer, a third composite buffer layer and a fourth composite buffer layer which are sequentially overlapped from bottom to top, wherein the value of the component y of Al is 0-0.3.
3. The epitaxial structure of claim 2, wherein: the first composite buffer layer is a GaAs buffer layer with the thickness ranging from 200 nm to 500nm, and the second composite buffer layer is Al 0.1 Ga 0.9 An As/GaAs buffer layer, wherein the superlattice period of the second composite buffer layer is 5 and Al 0.1 Ga 0.9 The thickness range of the As layer is 8-10 nm, the thickness range of the GaAs layer is 2-3 nm, and the third composite buffer layer is Al 0.17 Ga 0.83 An As/GaAs buffer layer, wherein the superlattice period of the third composite buffer layer is 5 and Al 0.17 Ga 0.83 The thickness range of the As layer is 8-10 nm, the thickness range of the GaAs layer is 2-3 nm, and the fourth composite buffer layer is Al 0.24 Ga 0.76 An As/GaAs buffer layer, wherein the superlattice period of the fourth composite buffer layer is 5 and Al 0.24 Ga 0.76 The thickness of the As layer ranges from 8nm to 10nm, and the thickness of the GaAs layer ranges from 2nm to 3nm.
4. The epitaxial structure of claim 1, wherein: the first AlGaAs barrier layer and the second AlGaAs barrier layer are denoted as Al x Ga 1-x As, wherein the value of the component x of Al is 0.2-0.3, the thickness range of the first AlGaAs barrier layer is 20-50 nm, and the thickness range of the second AlGaAs barrier layer is 15-30 nm.
5. The epitaxial structure of claim 1, wherein: the thickness of the first GaAs channel layer and the sixth GaAs channel layer ranges from 1nm to 2nm, and the second InGaAs channel layer is In 0.1 Ga 0.9 An As layer with a thickness ranging from 3 to 4nm, the third InGaAs channel layer being In 0.15 Ga 0.85 An As layer with a thickness ranging from 1.5 to 2nm, the fourth InGaAs channel layer being In 0.2 Ga 0.8 An As layer with a thickness ranging from 1 to 1.5nm, the fifth InGaAs channel layer being In 0.5 Ga 0.5 As layer, its thickness range is 0.5-1 nm.
6. The epitaxial structure of claim 1, wherein: the pulse doping layer comprises a Si-doped GaAs pulse doping layer and an AlAs pulse doping layer, wherein the Si doping concentration of the GaAs pulse doping layer is 5-6E 12cm -2 The thickness range is 0.5-2 nm, and the thickness range of the AlAs pulse doped layer is 0.5-1 nm.
7. The epitaxial structure of claim 1, wherein: the first corrosion stop layer and the second corrosion stop layer comprise AlAs corrosion stop layers, and the thickness ranges of the first corrosion stop layer and the second corrosion stop layer are respectively 0.5-1.5 nm.
8. The epitaxial structure of claim 1, wherein: the composite cap layer comprises a high Si doped composite GaAs cap layer and a composite In which are sequentially overlapped from bottom to top m Ga 1-m The As cap layer, wherein the doping concentration of Si in the composite GaAs cap layer is 0.5-1.5E19 cm -2 The thickness of the composite GaAs cap layer ranges from 30nm to 50nm, and the composite In m Ga 1-m The thickness range of the As cap layer is 10-20 nm, and the value of the component m of In is 0.15-0.25.
9. A method for preparing an epitaxial structure of a pseudomorphic high electron mobility transistor, the method being used to prepare an epitaxial structure of a pseudomorphic high electron mobility transistor according to any one of claims 1-8, characterized by: the preparation method comprises the following steps:
s1: providing a substrate;
s2: forming an AlGaAs/GaAs composite buffer layer on one side of the substrate by a growth interruption method, and growing a first AlGaAs barrier layer on the AlGaAs/GaAs composite buffer layer;
s3: growing an InGaAs composite channel layer on the first AlGaAs barrier layer by a growth interruption method, wherein the growth interruption time is 3-5 seconds;
s4: reducing the temperature of a Ga source furnace, and growing an AlGaAs isolation layer on the InGaAs composite channel layer;
s5: growing a pulse doping layer on the AlGaAs isolating layer;
s6: continuously growing a second AlGaAs barrier layer on the pulse doping layer;
s7: growing a first corrosion stop layer on the second AlGaAs barrier layer by a growth interruption method, wherein the growth interruption time of the first corrosion stop layer is 2-3 seconds;
s8: and continuously growing a GaAs cap layer, a second corrosion stop layer and a composite cap layer on the first corrosion stop layer.
10. A pseudomorphic high electron mobility transistor comprising a transistor body characterized by: the transistor body is provided with an epitaxial structure as claimed in any one of claims 1 to 8.
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