CN206389376U

CN206389376U - One kind digitlization Tacan receiver

Info

Publication number: CN206389376U
Application number: CN201621447029.5U
Authority: CN
Inventors: 刘新强; 徐敬舟; 任宏伟; 潘国翠; 朱金芳
Original assignee: Tianjin 764 Communication and Navigation Technology Corp
Current assignee: Tianjin 764 Communication and Navigation Technology Corp
Priority date: 2016-12-27
Filing date: 2016-12-27
Publication date: 2017-08-08
Anticipated expiration: 2026-12-27

Abstract

The utility model is related to a kind of digitlization Tacan receiver, including ARM modules, A/D sampling modules, FPGA module, comparator, operational amplifier, FPGA module is connected with comparator and operational amplifier respectively by A/D sampling modules, the other end is bi-directionally connected with ARM modules, A/D sampling modules are bi-directionally connected beneficial effect with ARM modules, digitlization Tacan receiver possesses long echo suppression, short echo suppressing, face radio frequency channel suppression, launch the function of closing, it is the μ s of 50 μ s ~ 350 to realize long echo to suppress the time controllable, short echo suppressing realizes switchable setting, debugging work load is reduced to original 1/3, circuit form is simple, volume is about reduced to the half of original receiver, dependable performance, sensitivity improves 3dB.

Description

One kind digitlization Tacan receiver

Technical field

The utility model is related to a kind of Tacan receiver, more particularly to a kind of digitlization Tacan receiver.

Background technology

Existing Tacan receiver is analog receiver, circuit form is complicated, volume is big, easily by external interference, into This height.

The content of the invention

In view of the problem of prior art is present, the utility model provides a kind of digitlization Tacan receiver, particular technique side Case is that one kind digitizes Tacan receiver, including ARM modules, A/D sampling modules, FPGA module, comparator, operational amplifier, It is characterized in that：FPGA module is connected with comparator and operational amplifier respectively by A/D sampling modules and arm processor is double To connection, A/D sampling modules are bi-directionally connected with arm processor；Concrete signal flow direction is that vision signal is narrow-band ping, warp Enter A/D sampling modules after comparator, subsequently enter FPGA module, the letter that width is about 4.5 μ s pulses pair is produced after processing Numbers 11；After logarithmic signal amplifies through operation amplifier circuit, into A/D sampling modules, FPGA module is entered after being sampled through A/D, Square-wave pulse pair is formed after signal 1 is detected through half range after being delayed in FPGA module, the square-wave pulse pair is divided into 8,9 two-way again, Signal 8 is not processed, and signal 9 enters phase inverter after certain delay, is entered jointly with signal 8 after phase inverter is negated With gate circuit, square-wave pulse should be exported with gate circuit to signal 10, the signal realizes the work(of half range detection and short echo suppressing Energy；Signal 2 enters comparator, and square-wave pulse is exported after comparator to signal 5；Signal 3 enters long echo door process circuit, should Circuit is by decoding pulse-triggered, when having decoding pulse output and signal 3 enters long echo gate circuit jointly, will produce signal 4, Signal 4 is 50 ~ 350 μ s direct impulse signals.Signal 4 and signal 5 enter trigger jointly, trigger is exported 50 ~ 350 μ s' Reverse impulse signal, the signal realizes that long echo suppresses function；Signal 7 is transmitting enclosed signal, is the μ s of pulse signal width 10 Reverse impulse, the signal realize transmitting closing function；Signal 6,7,10,11 enters with door jointly, the pulse that should be exported with door Subsequent treatment is carried out to signal feeding decoding unit, transmitting closing, long echo suppression has been finally completed, short echo suppressing, has faced ripple Road suppresses, the function of half range detection.

The beneficial effects of the utility model are that possess long echo suppression, short echo suppressing, face radio frequency channel suppression, transmitting closing Function, it is the μ s of 50 μ s ~ 350 to realize long echo to suppress the time controllable, and short echo suppressing realizes switchable setting, debugging efforts Amount is reduced to original 1/3, and circuit form is simple, volume is about reduced to the half of original receiver, dependable performance, and sensitivity is carried High 3dB.

Brief description of the drawings

Fig. 1 is that circuit of the present utility model connects block diagram.

Embodiment

As shown in figure 1, a kind of digitlization Tacan receiver, including arm processor, A/D sampling modules, FPGA module, ratio Compared with device, operational amplifier, FPGA module is connected and ARM modules with comparator and operational amplifier respectively by A/D sampling modules It is bi-directionally connected, A/D sampling modules are bi-directionally connected with arm processor.

In Tacan receiver, logarithmic signal is broadband signal, and signal does not have distortion, during with accurate half range point with rising Between；The half range detection of signal, long echo suppression function are realized, near echo suppresses function realization, transmitting closing function realization is On the basis of logarithmic signal.

Vision signal enters A/D sampling modules after comparator, subsequently enters FPGA module, and width is produced about after processing For 4.5 μ s impulse pair signals 11, vision signal is narrow band signal, and signal distortion occurs, but is due to its narrow-band characteristic, energy It is enough to realize that facing radio frequency channel suppresses function.

After logarithmic signal amplifies through operation amplifier circuit, into A/D sampling modules, FPGA moulds are entered after being sampled through A/D It is divided into the part of signal 1,2,3 three after block, 2.7 μ s of delay, wherein the 2.7 μ s that are delayed are in order that logarithmic signal and signal 11 exist The two is synchronous on the time during FPGA processing；Signal 1 forms square-wave pulse pair after being detected through half range, the square-wave pulse pair is divided into 8 again, 9 two-way：Signal 8 is not processed, and signal 9 passes through certain delay（X mode 7 .4 μ s, the μ s of Y mode 31.5）Enter phase inverter afterwards, Enter jointly and gate circuit with signal 8 after phase inverter is negated, square-wave pulse should be exported with gate circuit to signal 10, the signal Realize the function of half range detection and short echo suppressing；Signal 2 enters comparator, and square-wave pulse is exported after comparator to signal 5；Signal 3 enters long echo door process circuit, and the circuit is by decoding pulse-triggered, and when having, decoding pulse output and signal 3 are common During into long echo gate circuit, signal 4 will be produced, signal 4 is 50 ~ 350 μ s direct impulse signals.Signal 4 and signal 5 enter jointly Enter trigger, trigger is exported 50 ~ 350 μ s reverse impulse signal, the signal realizes that long echo suppresses function；Signal 7 is Launch enclosed signal, be the μ s of pulse signal width 10 reverse impulse, the signal realizes transmitting closing function；Signal 6,7,10, 11 is common into door, and the impulse pair signals feeding decoding unit that should be exported with door carries out subsequent treatment, has been finally completed transmitting Closing, long echo suppression, short echo suppressing, face radio frequency channel suppress, half range detection function.

Claims

1. one kind digitlization Tacan receiver, including ARM modules, A/D sampling modules, FPGA module, comparator, operation amplifier Device, it is characterised in that：FPGA module is connected and arm processor with comparator and operational amplifier respectively by A/D sampling modules It is bi-directionally connected, A/D sampling modules are bi-directionally connected with arm processor；Concrete signal flow direction is that vision signal is narrow-band ping, Enter A/D sampling modules after comparator, subsequently enter FPGA module, it is about 4.5 μ s pulses pair that width is produced after processing Signal 11；After logarithmic signal amplifies through operation amplifier circuit, into A/D sampling modules, FPGA moulds are entered after being sampled through A/D Block, forms square-wave pulse pair after signal 1 is detected through half range after being delayed in FPGA module, the square-wave pulse pair is divided into 8 again, 9 liang Road, signal 8 is not processed, and signal 9 enters phase inverter after certain delay, common with signal 8 after phase inverter is negated Into with gate circuit, should with gate circuit export square-wave pulse to signal 10, the signal realize half range detection and short echo suppressing Function；Signal 2 enters comparator, and square-wave pulse is exported after comparator to signal 5；Signal 3 enters long echo door processing electricity Road, the circuit, when having decoding pulse output and signal 3 enters long echo gate circuit jointly, will be produced by decoding pulse-triggered Signal 4, signal 4 is 50 ~ 350 μ s direct impulse signals；

Signal 4 and signal 5 enter trigger jointly, trigger is exported 50 ~ 350 μ s reverse impulse signal, and the signal is realized Long echo suppresses function；Signal 7 is transmitting enclosed signal, is the μ s of pulse signal width 10 reverse impulse, and the signal realizes hair Penetrate closing function；Signal 6,7,10,11 is common into door, and the impulse pair signals that should be exported with door are sent into after decoding unit progress Continuous processing, be finally completed transmitting closing, long echo suppressions, short echo suppressing, face radio frequency channel suppression, the function that half range is detected.