CN205003282U - Digital UHF doppler radar device - Google Patents
Digital UHF doppler radar device Download PDFInfo
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- CN205003282U CN205003282U CN201520806406.9U CN201520806406U CN205003282U CN 205003282 U CN205003282 U CN 205003282U CN 201520806406 U CN201520806406 U CN 201520806406U CN 205003282 U CN205003282 U CN 205003282U
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Abstract
The utility model provides a digital UHF doppler radar device, including transmitting circuit, receiving circuit, the transmitting circuit includes emit antenna, RF power amplifier, fire switch, data signal source, clock source, receiving circuit includes receiving antenna, analog front end, adc, digital signal processor, digital synchronising controller, USB transmission control ware, the clock source is that adc, digital signal processor, data signal source provide synchronized clock, the data signal source is handled with data signal and is linked to each other. The utility model discloses the system architecture is clear, and hardware circuit is simple, and is small, with low costs, and the configuration is nimble.
Description
Technical field
The utility model belongs to Radar Technology field, relating to a kind of for detecting river surface wave parameter or offshore sea wave parameter radar, particularly relating to a kind of digital UHF Doppler radar device.
Background technology
The precision that radar can obtain finally depends on signal-to-noise ratio (SIR) or signal noise ratio (SNR), and the object of Radar Signal Processing is exactly to improve these indexs.Traditional receiver employing super heterodyne architectures employs analog multiplier and carries out demodulation to echo, because the non-linear signal that makes of semiconductor devices produces crosstalk, be apparent that most third order intermodulation, although echo signal to noise ratio (S/N ratio) can be significantly improved by pulse compression technique, but but cannot eliminate crosstalk, because analog multiplier produce distortion and nonwhite noise composition, pulse compression can think that it is a part for echoed signal itself by mistake.In order to eliminate the crosstalk that Analogue mixer is introduced, best solution is exactly in numeric field mixing, utilizes desirable digital multiplier to replace having the analog multiplier of nonlinear characteristic.This is also the method that the utility model patent uses, and utilizes high-speed AD to echoed signal direct RF sampling, then realizes mixing at numeric field and obtain low frequency signal, more down-sampled after be further analyzed.The method effectively prevent the distortion that analog multiplier is introduced, and echoed signal carry information is utilized effectively.
In recent years U.S. codar company is proposed ultrahigh frequency river noncontact detection system RiverSonde on the basis of its hydrospace detection radar system SeaSonde, RiverSonde frequency of operation is at 420 to 450MHz, transmitter emissive power is at 1W, maximum detectable range 300m, the highest measurable flow speed 4m/s, its receiver just have employed digital structure.Being called of Wuhan University's application: a kind of Full digital high-frequency radar installations, the patent No. are: in the patent of 201220632452.8, this device is operated in high-frequency band, the direct nyquist sampling of signal of coming is received to antenna, in digital signal processor, realizes down coversion; Because the sampling rate of analog to digital converter exists the upper limit, therefore the program is not suitable in ultra-wideband systems.
Utility model content
For background technology Problems existing, the utility model provides a kind of digital UHF Doppler radar device.
The technical solution of the utility model is as follows:
A kind of digital UHF Doppler radar device, comprise radiating circuit and receiving circuit, described radiating circuit comprises the emitting antenna, radio-frequency power amplifier, emission switch, derived digital signal, the clock source that connect successively; Receiving circuit comprises the receiving antenna, AFE (analog front end), analog to digital converter, digital signal processor, digital synchronous controller, digital synchronous controller, the USB transmission control unit (TCU) that connect successively; Clock source is analog to digital converter, digital signal processor, digital synchronous controller, derived digital signal provide synchronous clock; Derived digital signal is connected with digital signal processing.
Described digital signal processor and digital synchronous controller are all realized by programmable logic device (PLD) (FPGA), selected FPGA is the CYCLONEV series of ALTERA company, and generates the control core of NIOSII flush bonding processor as receiver therein.
Described emitting antenna is Yagi antenna; Described receiving antenna is Yagi antenna array, and array has 8 antennas, and 8 antennas linearly equidistantly arrange, and spacing is the half-wavelength that transmits; Emitting antenna is positioned at the left front end of receiving antenna array, apart more than 10 meters.
Described analog to digital converter simulating signal input channel bandwidth must be greater than radar working frequency range, but only need meet bandpass sample theory for sampling rate; What adopt here is the radio frequency sampling that the logical equivalent sampling of band completes to antenna echo.
Described AFE (analog front end) comprises the receiving key, radio frequency amplifier and the radio frequency band filter that connect successively; receiving key is for the protection of receiver; prevent direct wave from crossing strong jamming receiver; radio frequency amplifier adopts two-stage to amplify; full gain is at about 45dB; bandpass filter centre frequency 340Mhz, bandwidth 15MHz are used for anti-aliasing filter.
Described derived digital signal comprises the DDS chip, radio frequency amplifier and the radio frequency band filter that connect successively, can control it produce required linear frequency sweep interruption continuous-wave mode by digital signal processor.
The temperature compensating crystal oscillator that described clock source connects successively, digital phase-locked loop chip and clock buffer chip; Temperature compensating crystal oscillator provides the clock source of high stable, produces two-way clock through digital phase-locked loop chip, and a road is used for derived digital signal, one tunnel is as the input of clock buffer chip, clock buffer chip exports 9 road clocks, and wherein 8 tunnels are used for 8 passage modulus modules, and 1 tunnel is used for digital signal processor.
The utility model structure is simple, volume is little, cost is low; Owing to realizing down coversion in the digital domain, eliminating Analogue mixer part in AFE (analog front end), thus greatly simplified, and signal quality is greatly improved, do not need to consider the interference problems such as third order intermodulation; Whole receiver circuit debugging difficulty simplifies greatly, and compact conformation can realize Portable radar apparatus.Clock due to modules all in this device all derives from same high-quality clock source, and the phase place therefore between module is extremely synchronous, and the phase stability of system promotes greatly.Relative to traditional superhet UHF Doppler radar device, this digital UHF Doppler radar device has obvious advantage and economic worth.
Accompanying drawing explanation
Fig. 1 is structure diagram of the present utility model.
Embodiment
Describe in detail below in conjunction with drawings and Examples:
The utility model comprises radiating circuit and receiving circuit as shown in Figure 1, and described radiating circuit comprises emitting antenna, radio-frequency power amplifier, emission switch, derived digital signal, clock source; Receiving circuit comprises receiving antenna, AFE (analog front end), analog to digital converter, digital signal processor, digital synchronous controller, USB transmission control unit (TCU); Clock source is analog to digital converter, digital signal processor, digital synchronous controller, derived digital signal provide synchronous clock; Derived digital signal is connected with digital signal processing.
Digital processing unit and digital synchronous controller are all realized by programmable logic device (PLD) (FPGA), and selected FPGA is the CYCLONEV series of ALTERA company, and generates the control core of NIOSII flush bonding processor as receiver therein; Emitting antenna is Yagi antenna; Described receiving antenna is Yagi antenna array, and array has 8 antennas, and 8 antennas linearly equidistantly arrange, and spacing is the half-wavelength that transmits; Emitting antenna is positioned at the left front end of receiving antenna array, apart more than 10 meters; Analog to digital converter simulating signal input channel bandwidth must be greater than radar working frequency range, but only need meet bandpass sample theory for sampling rate; What adopt here is the radio frequency sampling that the logical equivalent sampling of band completes to antenna echo.
AFE (analog front end) comprises receiving key, radio frequency amplifier and radio frequency band filter; receiving key is for the protection of receiver; prevent direct wave from crossing strong jamming receiver; radio frequency amplifier adopts two-stage to amplify; full gain is at about 45dB; bandpass filter centre frequency 340Mhz, bandwidth 15MHz are used for anti-aliasing filter.Derived digital signal is made up of DDS chip, radio frequency amplifier and radio frequency band filter, can control it produce required linear frequency sweep interruption continuous-wave mode by digital signal processor; Clock source is made up of temperature compensating crystal oscillator, digital phase-locked loop chip and clock buffer chip; Temperature compensating crystal oscillator provides the clock source of high stable, produces two-way clock through digital phase-locked loop chip, and a road is used for derived digital signal, one tunnel is as the input of clock buffer chip, clock buffer chip exports 9 road clocks, and wherein 8 tunnels are used for 8 passage modulus modules, and 1 tunnel is used for digital signal processor.
In the present embodiment:
Clock source produces the work clock of 9 road 81.92Mhz clocks for analog to digital conversion sampling clock and processor, also has 1 road 983.04MHz clock in addition as the reference clock of derived digital signal, the phase place of these two clocks is consistent, ensure that the phase stability of system.
Derived digital signal produces centre frequency 340Mhz, swept bandwidth 15Mhz, the linear frequency sweep of output power-10dBm interrupts continuous wave, and sent out by Yagi antenna after power amplifier, the gain of power amplifier is 50dB, and therefore emissive power is 10W.
The echoed signal that receiving antenna receives enters the direct bandpass sampling of analog to digital converter after AFE (analog front end) amplification 45dB, the down coversion that is multiplied with the inner digital local oscillator signal produced of FPGA obtains low frequency signal, now sampling rate is still very high, be not suitable for subsequent treatment, therefore add after one-level cic filter extracts 3200 times and obtain low sampling rate digital signal, after the host computer uploaded by USB module, can follow-up process be carried out.
Low-frequency time-domain information after demodulation is uploaded to host computer by USB module by receiver, and host computer carries out twice Fourier transform and obtains Distance geometry velocity information respectively.
Claims (7)
1. a digital UHF Doppler radar device, comprises radiating circuit and receiving circuit, it is characterized in that:
Described radiating circuit comprises the emitting antenna, radio-frequency power amplifier, emission switch, derived digital signal, the clock source that connect successively; Described receiving circuit comprises the receiving antenna, AFE (analog front end), analog to digital converter, digital signal processor, digital synchronous controller, the USB transmission control unit (TCU) that connect successively; Clock source is analog to digital converter, digital signal processor, digital synchronous controller, derived digital signal provide synchronous clock; Derived digital signal is connected with digital signal processor.
2. the digital UHF Doppler radar device of one according to claim 1, it is characterized in that: described digital signal processor and digital synchronous controller are all realized by programmable logic device (PLD) FPGA, selected FPGA is the CYCLONEV series of ALTERA company, and generates the control core of NIOSII flush bonding processor as receiver therein.
3. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described emitting antenna is Yagi antenna; Described receiving antenna is Yagi antenna array, and array has 8 antennas, in the light of actual conditions can change array case.
4. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described analog to digital converter uses low sampling rate to echoed signal bandpass sampling, does not need in AFE (analog front end) echoed signal mixing.
5. the digital UHF Doppler radar device of one according to claim 1; it is characterized in that: described AFE (analog front end) comprises the receiving key, radio frequency amplifier and the radio frequency band filter that connect successively; receiving key is for the protection of receiver; prevent direct wave from crossing strong jamming receiver; radio frequency amplifier adopts two-stage to amplify; full gain is 45dB, and radio frequency band filter centre frequency 340Mhz, bandwidth 15MHz are used for anti-aliasing filter.
6. the digital UHF Doppler radar device of one according to claim 1, it is characterized in that: described derived digital signal comprises the DDS chip, radio frequency amplifier and the radio frequency band filter that connect successively, by DSP CONTROL, it produces required linear frequency sweep interruption continuous-wave mode.
7. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described clock source comprises the temperature compensating crystal oscillator, digital phase-locked loop chip and the clock buffer chip that connect successively; Temperature compensating crystal oscillator provides the clock source of high stable, produces two-way clock through digital phase-locked loop chip, and a road is used for derived digital signal, one tunnel is as the input of clock buffer chip, clock buffer chip exports 9 road clocks, and wherein 8 tunnels are used for 8 passage modulus modules, and 1 tunnel is used for digital signal processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520806406.9U CN205003282U (en) | 2015-10-19 | 2015-10-19 | Digital UHF doppler radar device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520806406.9U CN205003282U (en) | 2015-10-19 | 2015-10-19 | Digital UHF doppler radar device |
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| CN205003282U true CN205003282U (en) | 2016-01-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520806406.9U Expired - Fee Related CN205003282U (en) | 2015-10-19 | 2015-10-19 | Digital UHF doppler radar device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353370A (en) * | 2015-11-24 | 2016-02-24 | 武汉大学 | All-digital ultrahigh frequency radar system for offshore flow detection and data processing method thereof |
| CN106506018A (en) * | 2016-10-20 | 2017-03-15 | 武汉大学 | A kind of digital AIS receiver systems that is directly sampled based on radio frequency |
| CN109683132A (en) * | 2018-11-09 | 2019-04-26 | 天津师范大学 | A kind of acoustics and picture signal hybrid terminal and its processing method |
-
2015
- 2015-10-19 CN CN201520806406.9U patent/CN205003282U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105353370A (en) * | 2015-11-24 | 2016-02-24 | 武汉大学 | All-digital ultrahigh frequency radar system for offshore flow detection and data processing method thereof |
| CN106506018A (en) * | 2016-10-20 | 2017-03-15 | 武汉大学 | A kind of digital AIS receiver systems that is directly sampled based on radio frequency |
| CN109683132A (en) * | 2018-11-09 | 2019-04-26 | 天津师范大学 | A kind of acoustics and picture signal hybrid terminal and its processing method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160127 Termination date: 20171019 |