CN205003282U - Digital UHF doppler radar device - Google Patents

Abstract

The utility model provides a digital UHF doppler radar device, including transmitting circuit, receiving circuit, the transmitting circuit includes emit antenna, RF power amplifier, fire switch, data signal source, clock source, receiving circuit includes receiving antenna, analog front end, adc, digital signal processor, digital synchronising controller, USB transmission control ware, the clock source is that adc, digital signal processor, data signal source provide synchronized clock, the data signal source is handled with data signal and is linked to each other. The utility model discloses the system architecture is clear, and hardware circuit is simple, and is small, with low costs, and the configuration is nimble.

Description

An all-digital UHF radar device

technical field

The utility model belongs to the technical field of radars, and relates to a radar for detecting river surface wave parameters or near-coast sea surface wave parameters, in particular to an all-digital ultra-high frequency radar device.

Background technique

The accuracy that radar can obtain ultimately depends on the signal-to-interference ratio (SIR) or signal-to-noise ratio (SNR), and the purpose of radar signal processing is to improve these indicators. The traditional receiver adopts a superheterodyne structure and uses an analog multiplier to demodulate the echo. Due to the nonlinearity of the semiconductor device, the signal produces intermodulation distortion, the most obvious being the third-order intermodulation. Although the pulse compression technology can The echo signal-to-noise ratio is significantly improved, but the intermodulation distortion cannot be eliminated, because the distortion generated by the analog multiplier is not a white noise component, and the pulse compression will mistake it as part of the echo signal itself. In order to eliminate the intermodulation distortion introduced by the analog mixer, the best solution is to mix the frequency in the digital domain, and use an ideal digital multiplier instead of an analog multiplier with nonlinear characteristics. This is also the method used in this utility model patent. The echo signal is directly sampled by high-speed AD, and then mixed in the digital domain to obtain a low-frequency signal, and then further analyzed after down-sampling. This method effectively avoids the distortion introduced by the analog multiplier, and makes effective use of the information carried by the echo signal.

In recent years, the U.S. codar company has launched the ultra-high frequency river non-contact detection system RiverSonde based on its ocean detection radar system SeaSonde. 4m/s, its receiver adopts an all-digital structure. In the patent applied by Wuhan University named: a full-digital high-frequency radar device, the patent number is: 201220632452.8, the device works in the high-frequency band, directly Nyquist sampling the signal received by the antenna, in the digital signal Down-conversion is implemented in the processor; this approach is not suitable for use in UHF systems due to the upper sampling rate limit of the analog-to-digital converter.

Utility model content

Aiming at the problems existing in the background technology, the utility model provides an all-digital ultra-high frequency radar device.

The technical scheme of the utility model is as follows:

An all-digital UHF radar device, comprising a transmitting circuit and a receiving circuit, the transmitting circuit comprising a transmitting antenna connected in sequence, a radio frequency power amplifier, a transmitting switch, a digital signal source, and a clock source; the receiving circuit comprising a receiving antenna connected in sequence , analog front end, analog-to-digital converter, digital signal processor, digital synchronous controller, digital synchronous controller, USB transmission controller; the clock source is analog-to-digital converter, digital signal processor, digital synchronous controller, digital signal source A synchronous clock is provided; the digital signal source is connected to the digital signal processing.

The digital signal processor and the digital synchronous controller are all realized by a programmable logic device (FPGA), and the selected FPGA is the CYCLONEV series of ALTERA Company, and a NIOSII embedded processor is generated inside it as the control core of the receiver .

The transmitting antenna is a Yagi antenna; the receiving antenna is a Yagi antenna array, and the array has 8 antennas, and the 8 antennas are arranged in a straight line at equal intervals, and the spacing is half the wavelength of the transmitting signal; the transmitting antenna is located at the left front end of the receiving antenna array, with a distance of more than 10 m.

The analog signal input channel bandwidth of the analog-to-digital converter must be greater than the radar operating frequency band, but the sampling rate only needs to satisfy the band-pass sampling theorem; here, the band-pass equivalent sampling is used to complete the radio frequency sampling of the antenna echo.

The analog front end includes a receiving switch, a radio frequency amplifier and a radio frequency band-pass filter connected in sequence, the receiving switch is used to protect the receiver and prevent the direct wave from being too strong to block the receiver, the radio frequency amplifier adopts two-stage amplification, and the total gain is about 45dB. The center frequency of the bandpass filter is 340Mhz, and the bandwidth is 15MHz for anti-aliasing filtering.

The digital signal source includes a sequentially connected DDS chip, a radio frequency amplifier and a radio frequency bandpass filter, which can be controlled by a digital signal processor to generate the required linear frequency sweep interrupted continuous wave pattern.

The temperature-compensated crystal oscillator, digital phase-locked loop chip and clock buffer chip connected in sequence to the clock source; the temperature-compensated crystal oscillator provides a highly stable clock source, and two clocks are generated through the digital phase-locked loop chip, one for the digital signal source and one for the digital signal source As the input of the clock buffer chip, the clock buffer chip outputs 9 clocks, 8 of which are used for the 8-channel analog-to-digital module, and 1 is used for the digital signal processor.

The utility model has the advantages of simple structure, small size and low cost; since the down-conversion is realized in the digital domain, the analog mixer part is removed in the analog front end, thereby greatly simplifying, and the signal quality is greatly improved, and there is no need to consider Interference problems such as third-order intermodulation; the difficulty of debugging the entire receiver circuit is greatly simplified, and the structure is compact, which can realize a portable radar device. Since the clocks of all modules in this device come from the same high-quality clock source, the phases between the modules are extremely synchronized, and the phase stability of the system is greatly improved. Compared with the traditional superheterodyne UHF radar device, the all-digital UHF radar device has obvious advantages and economic value.

Description of drawings

Fig. 1 is a structural diagram of the utility model.

detailed description

Below in conjunction with accompanying drawing and embodiment describe in detail:

As shown in Figure 1, the utility model includes a transmitting circuit and a receiving circuit, and the transmitting circuit includes a transmitting antenna, a radio frequency power amplifier, a transmitting switch, a digital signal source, and a clock source; the receiving circuit includes a receiving antenna, an analog front end, and an analog-to-digital converter , digital signal processor, digital synchronous controller, USB transmission controller; clock source provides synchronous clock for analog-to-digital converter, digital signal processor, digital synchronous controller, digital signal source; digital signal source is connected with digital signal processing.

The digital processor and digital synchronous controller are all implemented by programmable logic devices (FPGA). The selected FPGA is the CYCLONEV series of ALTERA Company, and a NIOSII embedded processor is generated inside it as the control core of the receiver; the transmitting antenna It is a Yagi antenna; the receiving antenna is a Yagi antenna array, the array has 8 antennas, and the 8 antennas are arranged in a straight line at equal intervals, and the spacing is half the wavelength of the transmitting signal; the transmitting antenna is located at the left front end of the receiving antenna array, and the distance is more than 10 meters; The analog signal input channel bandwidth of the digital converter must be greater than the radar operating frequency band, but the sampling rate only needs to satisfy the band-pass sampling theorem; here, the band-pass equivalent sampling is used to complete the radio frequency sampling of the antenna echo.

The analog front end includes a receiving switch, a radio frequency amplifier and a radio frequency band-pass filter. The receiving switch is used to protect the receiver and prevent the direct wave from blocking the receiver. The radio frequency amplifier adopts two-stage amplification with a total gain of about 45dB. The frequency is 340Mhz, and the bandwidth is 15MHz for anti-aliasing filtering. The digital signal source is composed of DDS chip, RF amplifier and RF bandpass filter, which can be controlled by the digital signal processor to generate the required linear frequency sweep interrupt continuous wave pattern; the clock source is composed of temperature-compensated crystal oscillator, digital phase-locked loop chip and clock The buffer chip is composed of; the temperature-compensated crystal oscillator provides a highly stable clock source, and two clocks are generated through the digital phase-locked loop chip, one is used for the digital signal source, and the other is used as the input of the clock buffer chip, and the clock buffer chip outputs 9 clocks, of which 8 One way is used for 8-channel analog-to-digital module, and one way is used for digital signal processor.

In this example:

The clock source generates 9 channels of 81.92Mhz clocks for the analog-to-digital conversion sampling clock and the working clock of the processor. There is also a channel of 983.04MHz clocks as the reference clock of the digital signal source. The phases of these two clocks are consistent, ensuring The phase stability of the system.

The digital signal source generates a linear sweep interrupted continuous wave with a center frequency of 340Mhz, a sweep bandwidth of 15Mhz, and an output power of -10dBm. After passing through the power amplifier, it is sent out through the Yagi antenna. The gain of the power amplifier is 50dB, so the transmit power is 10W.

The echo signal received by the receiving antenna is amplified by the analog front end by 45dB and then enters the analog-to-digital converter for direct band-pass sampling. It is multiplied by the digital local oscillator signal generated inside the FPGA and down-converted to obtain a low-frequency signal. At this time, the sampling rate is still high, which is not suitable for Subsequent processing, so a first-level CIC filter is added to extract 3200 times to obtain a low sampling rate digital signal, and subsequent processing can be performed after uploading to the host computer through the USB module.

The receiver uploads the demodulated low-frequency time-domain information to the host computer through the USB module, and the host computer performs two Fourier transforms to obtain distance and speed information respectively.

Claims (7)

1. a digital UHF Doppler radar device, comprises radiating circuit and receiving circuit, it is characterized in that:

Described radiating circuit comprises the emitting antenna, radio-frequency power amplifier, emission switch, derived digital signal, the clock source that connect successively; Described receiving circuit comprises the receiving antenna, AFE (analog front end), analog to digital converter, digital signal processor, digital synchronous controller, the USB transmission control unit (TCU) that connect successively; Clock source is analog to digital converter, digital signal processor, digital synchronous controller, derived digital signal provide synchronous clock; Derived digital signal is connected with digital signal processor.

2. the digital UHF Doppler radar device of one according to claim 1, it is characterized in that: described digital signal processor and digital synchronous controller are all realized by programmable logic device (PLD) FPGA, selected FPGA is the CYCLONEV series of ALTERA company, and generates the control core of NIOSII flush bonding processor as receiver therein.

3. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described emitting antenna is Yagi antenna; Described receiving antenna is Yagi antenna array, and array has 8 antennas, in the light of actual conditions can change array case.

4. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described analog to digital converter uses low sampling rate to echoed signal bandpass sampling, does not need in AFE (analog front end) echoed signal mixing.

5. the digital UHF Doppler radar device of one according to claim 1; it is characterized in that: described AFE (analog front end) comprises the receiving key, radio frequency amplifier and the radio frequency band filter that connect successively; receiving key is for the protection of receiver; prevent direct wave from crossing strong jamming receiver; radio frequency amplifier adopts two-stage to amplify; full gain is 45dB, and radio frequency band filter centre frequency 340Mhz, bandwidth 15MHz are used for anti-aliasing filter.

6. the digital UHF Doppler radar device of one according to claim 1, it is characterized in that: described derived digital signal comprises the DDS chip, radio frequency amplifier and the radio frequency band filter that connect successively, by DSP CONTROL, it produces required linear frequency sweep interruption continuous-wave mode.

7. the digital UHF Doppler radar device of one according to claim 1, is characterized in that: described clock source comprises the temperature compensating crystal oscillator, digital phase-locked loop chip and the clock buffer chip that connect successively; Temperature compensating crystal oscillator provides the clock source of high stable, produces two-way clock through digital phase-locked loop chip, and a road is used for derived digital signal, one tunnel is as the input of clock buffer chip, clock buffer chip exports 9 road clocks, and wherein 8 tunnels are used for 8 passage modulus modules, and 1 tunnel is used for digital signal processor.