CN206364914U - A kind of timing sequencer for binary channels CCD imaging systems - Google Patents
A kind of timing sequencer for binary channels CCD imaging systems Download PDFInfo
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Abstract
The utility model is related to a kind of timing sequencer for binary channels CCD imaging systems, and the timing sequencer includes external clock, host state machine, sub-state machine and counter；External clock is connected with host state machine；Sub-state machine turns state of a control machine, row including spectrum assignment state machine, frame and turns state of a control machine, pixel reading state of a control machine；Spectrum assignment state machine one end is connected with host state machine, and the other end and the frame of spectrum assignment state machine turn state of a control machine and be connected；Frame turns state of a control machine and is connected with pixel reading state of a control machine；Pixel reading state of a control machine turns state of a control machine with row respectively and host state machine is connected；Counter turns counter, row including exposure counter corresponding with each sub-state machine respectively, frame and turns counter and pixel read-out counter.The utility model is applied to the high frame frequency scientific grade CCD imaging system of binary channels, can meet the complex logic clock signal driving with certain phase relation, improve the reliability of CCD imaging systems.
Description
Technical field
The utility model is related to a kind of timing sequencer for binary channels CCD imaging systems.
Background technology
High-quality image plays very important in field of scientific studies such as astrosurveillance, remote measurement remote sensing, Aero-Space
Effect, therefore, in order to obtain high quality image, CCD camera has served as vital role.Current CCD camera in order to
Reduction reads noise, improves overall performance, and read-out speed is generally relatively low, and frame frequency is often no more than 1fps, some far from meeting
The demand of high frame frequency application.CCD output frequencies can be improved to a certain extent by the way of binary channels is exported, but accordingly
CCD imaging systems control sequential it is also more complicated, existing CCD sequential control methods are difficult to meet demand mostly.
The content of the invention
The technology for meeting high frame rate CCD imaging system demand for control to solve existing CCD sequential control methods to be difficult to
Problem, the utility model provides a kind of timing sequencer for binary channels CCD imaging systems.
Technical solution of the present utility model is：A kind of timing sequencer for binary channels CCD imaging systems, it is special
Different part is：Including external clock, host state machine, sub-state machine and counter；
The external clock is connected with host state machine；
The sub-state machine turns state of a control machine, row including spectrum assignment state machine, frame and turns state of a control machine, pixel reading
State of a control machine；Described spectrum assignment state machine one end is connected with host state machine, and the other end and the frame of spectrum assignment state machine turn
State of a control machine is connected；The frame turns state of a control machine and is connected with pixel reading state of a control machine；The pixel reads control shape
State machine turns state of a control machine with row respectively and host state machine is connected；
The counter includes exposure counter corresponding with each sub-state machine respectively, frame and turns counter, row turn counting
Device and pixel read-out counter.
The utility model also provides a kind of Timing driver method for binary channels CCD imaging systems, and its special character exists
In：Comprise the following steps：
1) system electrification, reset signal triggering host state machine is in holding state；
2) external clock produces synchronization pulse, is sent by host state machine to spectrum assignment state machine；
3) synchronization pulse trigger exposure state of a control machine, opens electronic shutter and starts exposure, while exposure counter
Start counting up；After the count value of exposure counter reaches time for exposure setting value, spectrum assignment state machine produces end exposure
Id signal simultaneously sends to frame and turns state of a control machine；Spectrum assignment state machine recovers holding state；
4) end exposure id signal trigger frame turns state of a control machine, carries out frame and turns operation, turns counter with time frame and start
Count；After the count value that frame turns counter reaches that frame turns setting value, frame turns state of a control machine and produces frame turn completion id signal
And send to pixel reading state of a control machine；Frame turns state of a control machine and recovers holding state；
5) frame turns to complete id signal triggering pixel reading state of a control machine, empty read operation is carried out, while pixel reads meter
Number device is started counting up；After the count value of pixel read-out counter reaches that pixel reads setting value, pixel reads state of a control machine
Produce sky and run through id signal and send to row and turn state of a control machine；Pixel reads state of a control machine and recovers holding state；
6) sky runs through id signal triggering row and turns state of a control machine, enters every trade and turns operation, while row turns counter and started
Count；After the count value that row turns counter reaches that row turns time setting value, row turns state of a control machine generation row and turns to complete mark
Signal is simultaneously sent to pixel reading state of a control machine；Row turns state of a control machine and recovers holding state；
7) row turns to complete id signal triggering pixel reading state of a control machine, pixel read operation is carried out, while pixel is read
Go out counter to start counting up；After the count value of pixel read-out counter reaches that pixel reads setting value, complete pixel and read, as
Member reads state of a control machine and recovers holding state；
8) step 3-7 is repeated), until completing the output of whole analog images.
Preferably, the synchronization pulse that external clock is produced is the 20Hz synchronization pulses that width is 1ms.
Step 4) in the frame that carries out to turn operation be that to produce the fixed cycle be 720KHz, the clock of overlapping 2/3 trace by image
The image in area goes to memory block.
Step 4) in frame turn setting value for 1030.
Step 5) in pixel read setting value be 256.
Step 6) in row turn time setting value for 105Tp.
The beneficial effects of the utility model are：The timing sequencer and sequential driving method that the utility model is provided are applicable
In the high frame frequency scientific grade CCD imaging system of binary channels, the complex logic clock signal with certain phase relation can be met and driven
It is dynamic, improve the reliability of CCD imaging systems.
Brief description of the drawings
Fig. 1 is the specific time diagram that the utility model timing sequencer is produced.
Fig. 2 is the driving circuit structure block diagram of the utility model timing sequencer.
Fig. 3 is the sequential flow chart of the utility model Timing driver method.
Fig. 4 is the Timing driver signal simulation waveform that the utility model Timing driver method is produced.
Embodiment
From FTT1010-M as ccd imaging sensor in the present embodiment, FTT1010-M belongs to frame transfer type area array CCD,
Referring to Fig. 1, the Timing driver signal that its normal work needs includes：4 tunnel frame transfer signal A1, A2, A3, A4,4 road row transfer letters
Number B1, B2, B3, B4,3 road pixel read output signal C1, C2, C3 and reset signal RG and pixel merge signal SG.The CCD is imaged
Working sensor is in left and right doubleway output pattern, in order to prevent left and right road signal from interfering with each other, by readout clock signal in design
C1 signals be divided into C1X and C1W, C2 signals are divided into C2X and C2W, go respectively driving CCD read, so, driver' s timing signal is total
Have 15 tunnels.
Specific sequential needed for FTT1010-M work is as shown in Fig. 2 its course of work can be broadly divided into 4 stages：(1)
Exposure stage, electronic shutter is opened, and CCD carries out light integration, converts optical signals into the charge packet signal of spatial distribution；(2) it is electric
Pocket signal is shifted, and charge packet signal is transferred to memory block from image district successively；(3) charge packet signal output, charge packet signal
Exported successively from memory block through amplifier；(4) it is idle, the next frame image to be captured such as CCD is completed after picture signal output.This
Outside, CCD peripheries have also needed to substantial amounts of voltage bias to coordinate this 4 steps just to can guarantee that its normal work.
CCD sequential is produced by FPGA it can be seen from Fig. 2, and the clock that outside is provided is divided, and according to hand
Volume produces corresponding exposure, frame transfer, row transfer and readout sequence signal, and these clock signals pass through vertical, horizontal drive circuit
CCD is given, its work is driven；Meanwhile, FPGA will also produce corresponding bias voltage control signal as needed, switch through bias
Circuit gives CCD, the need for meeting it to various voltages.
In whole timing diagram, the design of CCD sequential is the most complicated, and in order to simplify design, the utility model employs one
Individual host state machine is controlled, as shown in Figure 3.Then again different subfunctions is designed next stage state machine to realize, it is final complete
Into all functions.
Specific timing Design is as follows：After electricity is stable on FPGA, systematic reset signal Reset triggering host state machines are in
Idle condition, because the frame frequency of camera is fixed 20f/s, first, a width is produced in FPGA using clock division function
For 1us 20Hz synchronization pulses, for synchronous whole imaging process.It is fixed respectively in order to be precisely controlled in each process, system
Justice exposure counter Inter_cnt, frame turn counter F_cnt, row and turn counter L_cnt and pixel read-out counter P_cnt.
When first 20Hz pulse arrives, trigger exposure state of a control opens electronic shutter, and the duration of electronic shutter is set as
15us, while Inter_cnt is started counting up, when Inter_cnt value is equal to the time for exposure of setting, shows that exposure is completed,
State machine can produce an end exposure id signal, and state of a control is turned for trigger frame, while spectrum assignment state may proceed to
The arrival of next 20Hz synchronizing signals is waited, above procedure is repeated according still further to the new time for exposure.
Frame turns state of a control and received to proceed by frame after trigger signal and turn operation, and F_cnt starts counting up.It is main that frame turns operation
It is the generation fixed cycle image of image district to be gone into memory block for 720KHz, overlapping 2/3 trace clock, often shifts a line F_
Cnt numerical value adds 1, when F_cnt is equal to 1030, represents to finish all images transfer of image district, at this moment state machine can be produced
One frame turns to complete mark to trigger pixel reading state of a control, meanwhile, frame turns state of a control can be idle, and until next time, frame turns
The arrival of triggering.
In order to reduce influence of the interference signal to this two field picture as far as possible, after the completion of frame turns, the utility model is not direct
Row is gone to turn, but first 2 rows of empty reading, after pixel, which reads state, receives trigger signal, P_cnt is started counting up, and often reads a pixel
P_cnt numerical value adds 1, because CCD imaging systems of the present utility model are operated in two-way Binning patterns, when P_cnt is equal to 256
When illustrate that pixel has been read totally, at this moment if sky is run through trigger row turns state, otherwise into IDLE state, treat 105Tp
It is empty again after time to read once.
Row turns state and received after triggering, and L_cnt is started counting up, and the time that row turns is 105Tp, and L_cnt is in 70MHz clock zones
Numerical value is cumulative when its value is equal to 105Tp, and triggering pixel reads state and goes to read pixel.
Above procedure is repeated, CCD just can continually export analog image, during which can be passed through according to imaging needs
RS422 changes the time for exposure of camera, to adapt to changeable imaging circumstances.The time stimulatiom waveform of system is as shown in figure 4, control
CCD handbooks understand that the timing sequencer and sequential driving method that the utility model is provided fully meet requirement.
Claims (1)
1. a kind of timing sequencer for binary channels CCD imaging systems, it is characterised in that：Including external clock, host state machine,
Sub-state machine and counter；
The external clock is connected with host state machine；
The sub-state machine turns state of a control machine, row including spectrum assignment state machine, frame and turns state of a control machine, pixel reading control
State machine；Described spectrum assignment state machine one end is connected with host state machine, and the other end and the frame of spectrum assignment state machine turn control
State machine is connected；The frame turns state of a control machine and is connected with pixel reading state of a control machine；The pixel reads state of a control machine
Turn state of a control machine with row respectively and host state machine is connected；
The counter include the exposure counter corresponding with each sub-state machine, frame respectively turn counter, row turn counter and
Pixel read-out counter.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106791505A (en) * | 2016-12-29 | 2017-05-31 | 中国科学院西安光学精密机械研究所 | A kind of timing sequencer and sequential driving method for binary channels CCD imaging systems |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106791505A (en) * | 2016-12-29 | 2017-05-31 | 中国科学院西安光学精密机械研究所 | A kind of timing sequencer and sequential driving method for binary channels CCD imaging systems |
| CN106791505B (en) * | 2016-12-29 | 2023-09-05 | 中国科学院西安光学精密机械研究所 | Time sequence generator and time sequence driving method for double-channel CCD imaging system |
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