CN206349984U - A kind of broadband signal sampling playback system that compensation is divided based on frequency range - Google Patents
A kind of broadband signal sampling playback system that compensation is divided based on frequency range Download PDFInfo
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- CN206349984U CN206349984U CN201621377811.4U CN201621377811U CN206349984U CN 206349984 U CN206349984 U CN 206349984U CN 201621377811 U CN201621377811 U CN 201621377811U CN 206349984 U CN206349984 U CN 206349984U
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Abstract
The utility model provides a kind of broadband signal sampling playback system that compensation is divided based on frequency range, including：Input analog signal conditioner circuit, AD, digital signal processing module, DA, output analog signal conditioner circuit；Frequency measurement, the compensation operation for carrying out correlation using the mode of software on general-purpose processing device are different from, all numeric fields work and completed in FPGA, belong to a kind of hardware-accelerated work, process performance is better than the former.
Description
Technical field
The utility model belongs to field of signal processing, more particularly to a kind of broadband signal for dividing compensation based on frequency range is adopted
Sample playback system.
Background technology
In digital processing field, according to practical application scene, signal frequency to be processed needed for system often compared with
For fixation：Such as voice signal (300Hz-3.4KHz), underwater sound signal (KHz-100KHz grades), radar intermediate frequency signal (100MHz grades)
Deng.In real work, for each scene, respective ripe signal conditioning circuit and back-end processing method have been developed, and
Achieve good application effect.
At the same time, when application scenarios need analog signal band coverage broadening to be processed to hundred hertz of levels to 100,000,000
During hertz level, no matter how the signal conditioning circuit of analog end designs, and its amplitude-frequency response characteristic necessarily occurs more in passband
Obvious fluctuation.
Utility model content
In view of this, in order to overcome the deficiencies in the prior art, the utility model offer is a kind of to divide compensation based on frequency range
Broadband signal sampling playback system, can realize wideband of the pending signal frequency in hundred hertz of levels to hundred megahertzs of level scopes
Band signal, realizes the signal sampling storage playback function of low distortion, also, the signal that need to be handled is in the main signal frequency of synchronization
Rate is relatively fixed.
A kind of broadband signal sampling playback system that compensation is divided based on frequency range, including：
Input analog signal conditioner circuit：The first broadband analog signal is received, and the first broadband analog signal is entered
The preliminary conditioning of row；
AD：The first broadband analog signal after the input analog signal conditioner circuit tentatively conditioning is received, and will just
The first broadband analog signal after step reason is converted into the first digital quantity signal；
Digital signal processing module：The first digital quantity signal that the AD is exported is received, and the first digital quantity signal is carried out
Sampling, storage and playback；
DA：The first digital quantity signal after the digital signal processing module is sampled, stored and played back is received, and will be adopted
The first digital quantity signal after sample, storage and playback is converted into the second broadband analog signal；
Export analog signal conditioner circuit：The second broadband analog signal that the DA is exported is received, to the second wideband
Band analog signal is nursed one's health, and by the second broadband analog signal output after conditioning.
Further, the digital signal processing module includes FPGA and DDR3 SDRAM, and the FPGA mounts the DDR3
SDRAM, the FPGA carry out Frequency Estimation to first digital quantity signal and corrected；The DDR3 SDRAM are to described first
Digital quantity signal is stored.
Further, the first broadband analog signal is hundred hertz to hundred megahertzs.
Further, the digital signal processing module segmentation carries out continuous sampling to first digital quantity signal.
The beneficial effects of the utility model are：1) it is different from general-purpose processing device (such as central processor CPU, numeral letter
Number processor DSP etc.) on carry out frequency measurement, the compensation operation of correlation using the mode of software, all numeric field work (including is adopted
Sample, Frequency Estimation and compensation data playback) completed in FPGA, belong to a kind of hardware-accelerated work, process performance is excellent
In the former；
2), it is necessary to be divided according to frequency range, if designing main line AD/DA passages on hardware circuit with respectively in traditional design
Handle one section of frequency band of relative narrower；The technical program completes the broadband signal collection of the level from hundred hertz to hundred megahertzs, and
Preferably sampling playback effect can be obtained.
Brief description of the drawings
Fig. 1 is a kind of basic structure schematic diagram for the broadband signal sampling playback system that compensation is divided based on frequency range；
Fig. 2 is the workflow schematic diagram for carrying out Frequency Estimation and compensation playback inside FPGA to sampled signal；
Fig. 3 is the workflow schematic diagram of the algorithm structure of frequency estimation unit in Fig. 2；
Wherein, 101, input analog signal conditioner circuit；102nd, analog signal conditioner circuit is exported；20、AD；40、DA；
50、FPGA；60、DDR3 SDRAM；70th, the first FIFO is buffered；80th, the 2nd FIFO is buffered.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with the accompanying drawings and implement
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only to explain this
Utility model, is not used to limit the utility model.
The playback system as shown in figure 1, a kind of broadband signal for dividing compensation based on frequency range is sampled, including：
Input analog signal conditioner circuit 101：The first broadband analog signal is received, and to the first broadband analog signal
Tentatively nursed one's health；
Input analog signal conditioner circuit 101 refers to by the outer of the operational amplifier A DA4937-1 of ADI companies and correlation
Enclose discrete device (resistance, inductance, electric capacity) and take out related circuit.
AD20：The first broadband analog signal after the tentatively conditioning of input analog signal conditioner circuit 101 is received, and will just
The first broadband analog signal after step reason is converted into the first digital quantity signal；
AD20 analog-digital converters, are converted into digital quantity by analog electrical signal input, are output in digital display circuit and are handled,
A kind of available model is the ISLA214P50 chips of Intersil companies, and chip sampling bit wide 14bit (passes through in digital display circuit
Bit wide is expanded to 16bit by minimum two zero paddings), maximum slew rate 500MHz.
Digital signal processing module：The first digital quantity signal that AD20 is exported is received, and the first digital quantity signal is adopted
Sample, storage and playback；
DA40：Receive digital signal processing module sampled, stored and play back after the first digital quantity signal, and will sample,
The first digital quantity signal after storage and playback is converted into the second broadband analog signal；
DA40：Digital analog converter, by the digital quantity that digital display circuit is sent be converted to corresponding analog electrical signal and to
Outer output.A kind of available model is the AD9783 chips of ADI companies, and the chip data bit wide is 16bit, maximum data turnover rate
For 500MHz.
Export analog signal conditioner circuit 102：The second broadband analog signal that DA40 is exported is received, to the second wideband
Band analog signal is nursed one's health, and by the second broadband analog signal output after conditioning.
Digital signal processing module includes FPGA50 and DDR3 SDRAM60, FPGA50 mounting DDR3 SDRAM60, FPGA50 couples
First digital quantity signal carries out Frequency Estimation and corrected；DDR3 SDRAM60 are stored to the first digital quantity signal.
FPGA50：FPGA, a kind of chip of internal hardware structure programmable, by hard to its inside
The digital circuitry functions that the programming realization of part logic is specified.A kind of XC7K160T- of available model Xilinx companies
3fbg676。
DDR3 SDRAM60：Third generation Double Data Rate SDRAM.A kind of available model
MT41K256M16HA-125IT。
First broadband analog signal is hundred hertz to hundred megahertzs.
Have been converted into the analog signal of electric signal, the frequency of electric analoging signal can include from hundred hertz (100Hz) to
The frequency component of hundred megahertzs of (100MHz) levels.
Digital signal processing module segmentation carries out continuous sampling to the first digital quantity signal.
A kind of method that use divides the broadband signal sampling playback system of compensation based on frequency range, comprises the following steps：
1) digital signal processing module buffers 70 the first digital quantity signals for continuously reading AD20 samplings by the first FIFO；
2) the DDR3 SDRAM60 mounted using FPGA50 periodically cache a collection of continuous first digital quantity signal；
3) FPGA50 divides multiple frequency ranges according to the frequency range of the first pending digital quantity signal, for each frequency range
Data are extracted from DDR3 SDRAM60；
4) data to extraction carry out FFT computings respectively, and FFT result feeding cordic units are extracted into corresponding data
Amplitude response value, by comparing, the main signal frequency of current demand signal is judged, while frequency information also is notified into main process task
Device；
5) signal for treating playback according to main signal frequency and the compensating parameter that obtains in advance carries out digital compensation, and according to
Primary control program order transfers data to DA40 externally to play back by the 2nd FIFO bufferings 80.
If pending signal frequency range is 50Hz-200MHz；
From 16 DA20 chips of 16 AD20 chips of 500MHz sample rates and 500MHz data updating rates, AD20/
DA40 chips are articulated on a piece of high-performance FPGA50 respectively.Wherein, a piece of DDR3 particles of high-performance FPGA50 carries.System
The signal of collection is stored in DDR3 by basic working modes to carry out the signal acquisition of a period of time, using FPGA50 to collection
Signal carry out Frequency Estimation, finally need playback when output is modified to sampled value.
The burned test logic first into FPGA50, straight-through be connected on DA40 of AD20 sampled signals is exported, measured respectively
The virtual value proportionate relationship of input signal and output signal under some frequencies.
As shown in Fig. 2 test logic refers to：Frequency estimation unit, corrected parameter list are removed, by two FIFO data
Carry out direct-connected logic.The corrected parameter list of actual circuit is obtained for early stage, without using the logic during real work.
Straight-through be connected on DA40 of AD sampled signals is exported purpose and be：In order to obtain circuit in real work in each frequency
The actual signal pad values of Duan Shangcong foremost produced by simulation input to rearmost end analog signal output.Measure the simulation of input
Signal energy (AD20 inputs), then measure the signal energy of the analog signal (DA40 outputs) exported under test logic control.Obtain
The two energy differences is taken, the ratio of signal amplitude is obtained by conversion.
Value of frequency point to be measured：200MHz、190MHz、180MHz、……10MHz、1MHz；
900KHz、800KHz、……100KHz、50KHz、20KHz、10KHz、5KHz、1KHz；
900Hz、800Hz、……100Hz、50Hz。
By the proportionate relationship measured and (or main control chip) in each self-corresponding frequency band deposit FPGA ram.
The proportionate relationship under some frequencies in the virtual value proportionate relationship of input signal and output signal is measured respectively to refer to：
The proportionate relationship obtained by the energy differential conversion measured.
One conversion example is as follows：
Measured at 150MHz, the difference power of output signal and input signal is about 1dB.Then input signal and output signal
Amplitude ratio Al/AOIt is as follows：
The corrected parameter of 160-140MHz frequency ranges can be then set in reference to other frequency measurement results near 1.122.
Each self-corresponding frequency band refers to：According to frequency, 200-180MHz, 180-160MHz, 160- can be divided into
140MHz、……40-20MHz、20-1MHz；
1000-800KHz、800-600KHz、……200-100KHz、100-5KHz；
5000Hz-1KHz、1KHz-500Hz、500Hz-50Hz。
As shown in figure 3, signal frequency range is divided into three sections：50Hz-5KHz, 5KHz-1MHz, 1MHz-200MHz, are used to respectively
Under type extracts sampled value from DDR：
50Hz-5KHz sections：40000 times are taken out value, equivalent 12.5KHz sample rates.One complete cycle sampled point of 50Hz signals
For 250 points；One complete cycle sampled point number of 5KHz signals is 2.5 points.
5KHz-1MHz sections：200 times are taken out value, equivalent 2.5MHz sample rates.One complete cycle sampled point of 5KHz signals is
500 points；1MHz signal integrity sampling periods sampling number is 2.5 points.
1MHz-200MHz sections：Do not take out value, original 500MHz sample rates.One complete cycle sampled point of 1MHz signals is 500
Point；200MHz signal integrity sampling periods sampling number is 2.5 points.
During above-mentioned frequency range is divided, in each frequency range highest frequency equivalent sampling rate less than half, meet how
Qwest's bandwidth；Meanwhile, each section after 2048 point FFT computings respective minimum frequency resolution ratio be respectively
6.103515625Hz, 1.220703125KHz and 0.244140625MHz, can preferably tell the minimum of each frequency range
Frequency.In order to prevent obscuring.Signal 3 big frequency ranges have been divided into example.Assuming that carrying out Frequency Estimation to 50-5KHz frequency ranges
Shi Buneng tells minimum 50Hz frequencies, then very likely by the Frequency Estimation of sampled signal be 0Hz so as to obtain mistake repair
On the occasion of, and cause digital system operation abnormal.
Each frequency range extracts 200 sampled points, and 2048 point FFT computings (all mending 0 in not enough part) are carried out respectively.Will meter
Calculate result and be sequentially sent to cordic units, extract the corresponding frequency of amplitude response highest point；By the frequency of extraction and each frequency range
Interior minimum frequency resolution ratio is multiplied, and obtains actual frequency estimation.
cordic：Coordinate Rotation Digital computational methods.A stone resource in FPGA is referred in text, the unit is used
The amplitude and phase information of signal are extracted after input signal FFT.
To ensure the accuracy of Frequency Estimation, each frequency range sampling number at least needs at 200 points, then once complete frequency
Estimation at least needs 8000000 sampled points, and required memory space is about 15.3M bytes, and the required sampling time is about
16ms。
Frequency estimation algorithm is about 30us from extracting algorithm of the sampled value to needed for extracting bigness scale frequency values and being delayed.
According to the signal frequency estimate in this period, with reference to the numeral that playback is treated when carrying out signal playback measured
Signal is compensated, it is ensured that inband signaling amplitude response substantially flat.
Above example only expresses embodiment of the present utility model, and it describes more specific and detailed, but can not
Therefore it is interpreted as the limitation to the utility model the scope of the claims.It should be pointed out that for one of ordinary skill in the art
For, without departing from the concept of the premise utility, various modifications and improvements can be made, these belong to this practicality
New protection domain.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (4)
- The playback system 1. a kind of broadband signal for dividing compensation based on frequency range is sampled, it is characterised in that including：Input analog signal conditioner circuit (101)：The first broadband analog signal is received, and the first broadband analog signal is entered The preliminary conditioning of row；AD(20)：The first broadband analog signal after the input analog signal conditioner circuit (101) tentatively conditioning is received, and The first broadband analog signal after preliminary conditioning is converted into the first digital quantity signal；Digital signal processing module：The first digital quantity signal that the AD (20) is exported is received, and the first digital quantity signal is carried out Sampling, storage and playback；DA(40)：The first digital quantity signal after the digital signal processing module is sampled, stored and played back is received, and will be adopted The first digital quantity signal after sample, storage and playback is converted into the second broadband analog signal；Export analog signal conditioner circuit (102)：The second broadband analog signal that the DA (40) is exported is received, to second Broadband analog signal is nursed one's health, and by the second broadband analog signal output after conditioning.
- Playback system, its feature 2. a kind of broadband signal for dividing compensation based on frequency range according to claim 1 is sampled It is：The digital signal processing module includes FPGA (50) and DDR3 SDRAM (60), and the FPGA (50) mounts the DDR3 SDRAM (60), the FPGA (50) carries out Frequency Estimation to first digital quantity signal and corrected；The DDR3 SDRAM (60) first digital quantity signal is stored.
- Playback system, its feature 3. a kind of broadband signal for dividing compensation based on frequency range according to claim 1 is sampled It is：The first broadband analog signal is hundred hertz to hundred megahertzs.
- Playback system, its feature 4. a kind of broadband signal for dividing compensation based on frequency range according to claim 1 is sampled It is：The digital signal processing module segmentation carries out continuous sampling to first digital quantity signal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108616277A (en) * | 2018-05-22 | 2018-10-02 | 电子科技大学 | A kind of method for quickly correcting of multichannel frequency domain compensation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108616277A (en) * | 2018-05-22 | 2018-10-02 | 电子科技大学 | A kind of method for quickly correcting of multichannel frequency domain compensation |
| CN108616277B (en) * | 2018-05-22 | 2021-07-13 | 电子科技大学 | Rapid correction method for multi-channel frequency domain compensation |
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Granted publication date: 20170721 Termination date: 20211215 |