CN106788430A - A kind of broadband signal sampling playback system that compensation is divided based on frequency range - Google Patents
A kind of broadband signal sampling playback system that compensation is divided based on frequency range Download PDFInfo
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- CN106788430A CN106788430A CN201611161285.2A CN201611161285A CN106788430A CN 106788430 A CN106788430 A CN 106788430A CN 201611161285 A CN201611161285 A CN 201611161285A CN 106788430 A CN106788430 A CN 106788430A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Abstract
The invention provides a kind of broadband signal sampling playback system that compensation is divided based on frequency range, including：Input analog signal conditioner circuit, AD, digital signal processing module, DA, output analog signal conditioner circuit；Being different from general-purpose processing device carries out frequency measurement, the compensation operation of correlation using the mode of software, and all of numeric field work is completed in FPGA, belongs to a kind of hardware-accelerated work, and process performance is better than the former.
Description
Technical field
Sampled back the invention belongs to field of signal processing, more particularly to a kind of broadband signal for dividing compensation based on frequency range
Place system.
Background technology
In digital processing field, according to practical application scene, signal frequency to be processed needed for system often compared with
It is fixation：Such as voice signal (300Hz-3.4KHz), underwater sound signal (KHz-100KHz grades), radar intermediate frequency signal (100MHz grades)
Deng.In real work, for each scene, the signal conditioning circuit and back-end processing method of respective maturation are developed, and
Achieve good application effect.
At the same time, when application scenarios need analog signal band coverage broadening to be processed to hundred hertz of levels to 100,000,000
During hertz level, no matter how the signal conditioning circuit of analog end designs, and its amplitude-frequency response characteristic necessarily occurs more in passband
Obvious fluctuation.
The content of the invention
In view of this, in order to overcome the deficiencies in the prior art, the present invention to provide a kind of wideband that compensation is divided based on frequency range
Band signal sampling playback system, can realize that pending signal frequency is taken a message in hundred hertz of levels to the wideband of hundred megahertzs of level scopes
Number, the signal sampling storage playback function of low distortion is realized, also, the signal that need to be processed is in the main signal frequency phase of synchronization
To fixation.
A kind of broadband signal sampling playback system that compensation is divided based on frequency range, including：
Input analog signal conditioner circuit：The first broadband analog signal is received, and the first broadband analog signal is entered
The preliminary conditioning of row；
AD：The first broadband analog signal after the input analog signal conditioner circuit tentatively conditioning is received, and will just
The first broadband analog signal after step reason is converted into the first digital quantity signal；
Digital signal processing module：The first digital quantity signal that the AD is exported is received, and the first digital quantity signal is carried out
Sampling, storage and playback；
DA：The first digital quantity signal after the digital signal processing module is sampled, stored and played back is received, and will be adopted
The first digital quantity signal after sample, storage and playback is converted into the second broadband analog signal；
Output analog signal conditioner circuit：The second broadband analog signal that the DA is exported is received, to the second wideband
Band analog signal nursed one's health, and by conditioning after the second broadband analog signal output.
Further, the digital signal processing module includes that FPGA and DDR3 SDRAM, the FPGA mount the DDR3
SDRAM, the FPGA carry out Frequency Estimation and correct to first digital quantity signal；The DDR3 SDRAM are to described first
Digital quantity signal is stored.
Further, the first broadband analog signal is hundred hertz to hundred megahertzs.
Further, the digital signal processing module segmentation carries out continuous sampling to first digital quantity signal.
The present invention also provides a kind of method of playback system of being sampled using the broadband signal based on frequency range division compensation, bag
Include following steps：
1) digital signal processing module buffers continuous the first digital quantity signal for reading AD samplings by a FIFO；
2) the DDR3 SDRAM mounted using FPGA periodically cache a collection of continuous first digital quantity signal；
3) FPGA divides multiple frequency ranges according to the frequency range of the first pending digital quantity signal, for each frequency range from
Extracted data in DDR3 SDRAM；
4) FFT computings are carried out respectively to the data for extracting, the result feeding cordic units of FFT is extracted into corresponding data
Amplitude response value, by comparing, the main signal frequency of current demand signal is judged, while frequency information also is notified into main process task
Device；
5) signal for treating playback according to main signal frequency and the compensating parameter that obtains in advance carries out digital compensation, and according to
Primary control program order is buffered by the 2nd FIFO and transfers data to DA externally to play back.
Beneficial effects of the present invention are：1) it is different from general-purpose processing device (such as at central processor CPU, data signal
Reason device DSP etc.) on carry out frequency measurement, the compensation operation of correlation using the mode of software, all of numeric field work (including sampling,
Frequency Estimation and compensation data are played back) completed in FPGA, belong to a kind of hardware-accelerated work, before process performance is better than
Person；
2) in traditional design, it is necessary to according to frequency range divide, if designed on hardware circuit main line AD/DA passages with respectively
Process one section of frequency band of relative narrower；The technical program completes the broadband signal collection of the level from hundred hertz to hundred megahertzs, and
Preferably sampling playback effect can be obtained.
Brief description of the drawings
Fig. 1 is a kind of basic structure schematic diagram of the broadband signal sampling playback system that compensation is divided based on frequency range；
Fig. 2 is the workflow schematic diagram for carrying out Frequency Estimation and compensation playback inside FPGA to sampled signal；
Fig. 3 is the workflow schematic diagram of the algorithm structure of frequency estimation unit in Fig. 2；
Wherein, 101, input analog signal conditioner circuit；102nd, analog signal conditioner circuit is exported；20、AD；40、DA；
50、FPGA；60、DDR3 SDRAM；70th, FIFO bufferings；80th, the 2nd FIFO bufferings.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with the accompanying drawings and embodiment, it is right
The present invention is further elaborated.It should be appreciated that specific embodiment described herein is only used to explain the present invention, not
For limiting the present invention.
The playback system as shown in figure 1, a kind of broadband signal for dividing compensation based on frequency range is sampled, including：
Input analog signal conditioner circuit 101：The first broadband analog signal is received, and to the first broadband analog signal
Tentatively nursed one's health；
Input analog signal conditioner circuit 101 refers to by the outer of the operational amplifier A DA4937-1 of ADI companies and correlation
Enclose discrete device (resistance, inductance, electric capacity) and take out related circuit.
AD20：The first broadband analog signal after the preliminary conditioning of input analog signal conditioner circuit 101 is received, and will just
The first broadband analog signal after step reason is converted into the first digital quantity signal；
AD20 analog-digital converters, digital quantity is converted into by analog electrical signal input, is processed in output to digital display circuit,
A kind of available model is the ISLA214P50 chips of Intersil companies, and chip sampling bit wide 14bit (passes through in digital display circuit
Bit wide is expanded to 16bit by minimum two zero paddings), maximum slew rate 500MHz.
Digital signal processing module：The first digital quantity signal that AD20 is exported is received, and the first digital quantity signal is adopted
Sample, storage and playback；
DA40：Receive digital signal processing module sampled, stored and play back after the first digital quantity signal, and will sample,
The first digital quantity signal after storage and playback is converted into the second broadband analog signal；
DA40：Digital analog converter, by the digital quantity that digital display circuit sends be converted to corresponding analog electrical signal and to
Outer output.A kind of available model is the AD9783 chips of ADI companies, and the chip data bit wide is 16bit, maximum data turnover rate
It is 500MHz.
Output analog signal conditioner circuit 102：The second broadband analog signal that DA40 is exported is received, to the second wideband
Band analog signal nursed one's health, and by conditioning after the second broadband analog signal output.
Digital signal processing module includes FPGA50 and DDR3 SDRAM60, FPGA50 mounting DDR3 SDRAM60, FPGA50 couples
First digital quantity signal carries out Frequency Estimation and corrects；DDR3 SDRAM60 are stored to the first digital quantity signal.
FPGA50：FPGA, a kind of chip of internal hardware structure programmable, by hard to its inside
The digital circuitry functions that the programming realization of part logic is specified.A kind of XC7K160T- of available model Xilinx companies
3fbg676。
DDR3 SDRAM60：Third generation Double Data Rate SDRAM.A kind of available model
MT41K256M16HA-125IT。
First broadband analog signal is hundred hertz to hundred megahertzs.
Have been converted into the analog signal of electric signal, the frequency of electric analoging signal can include from hundred hertz (100Hz) to
Hundred megahertzs of frequency components of (100MHz) level.
Digital signal processing module segmentation carries out continuous sampling to the first digital quantity signal.
A kind of method of playback system of being sampled using the broadband signal based on frequency range division compensation, is comprised the following steps：
1) digital signal processing module buffers 70 continuous the first digital quantity signals for reading AD20 samplings by a FIFO；
2) the DDR3 SDRAM60 mounted using FPGA50 periodically cache a collection of continuous first digital quantity signal；
3) FPGA50 divides multiple frequency ranges according to the frequency range of the first pending digital quantity signal, for each frequency range
The extracted data from DDR3 SDRAM60；
4) FFT computings are carried out respectively to the data for extracting, the result feeding cordic units of FFT is extracted into corresponding data
Amplitude response value, by comparing, the main signal frequency of current demand signal is judged, while frequency information also is notified into main process task
Device；
5) signal for treating playback according to main signal frequency and the compensating parameter that obtains in advance carries out digital compensation, and according to
Primary control program order buffers 80 and transfers data to DA40 externally to play back by the 2nd FIFO.
If pending signal frequency range is 50Hz-200MHz；
From 16 DA20 chips of 16 AD20 chips of 500MHz sample rates and 500MHz data updating rates, AD20/
DA40 chips are articulated on a piece of high-performance FPGA50 respectively.Wherein, a piece of DDR3 particles of high-performance FPGA50 carries.System
Basic working modes are the signal acquisition for carrying out a period of time, and the signal of collection is stored in DDR3, using FPGA50 to collection
Signal carry out Frequency Estimation, finally need playback when output is modified to sampled value.
First to burned test logic in FPGA50, straight-through being connected on DA40 of AD20 sampled signals is exported, measured respectively
The virtual value proportionate relationship of input signal and output signal under some frequencies.
As shown in Fig. 2 test logic refers to：Removal frequency estimation unit, corrected parameter list, by two data of FIFO
Carry out direct-connected logic.The corrected parameter list of side circuit is obtained for early stage, the logic is not used during real work.
Straight-through being connected on DA40 of AD sampled signals is exported purpose and be：In order to obtain circuit in real work at each frequently
Duan Shangcong actual signal pad values foremost produced by simulation input to rearmost end analog signal output.Measure the simulation of input
Signal energy (AD20 inputs), then measure the signal energy of the analog signal (DA40 outputs) exported under test logic control.Obtain
The two energy differences is taken, the ratio of signal amplitude is obtained by conversion.
Value of frequency point to be measured：200MHz、190MHz、180MHz、……10MHz、1MHz；
900KHz、800KHz、……100KHz、50KHz、20KHz、10KHz、5KHz、1KHz；
900Hz、800Hz、……100Hz、50Hz。
The proportionate relationship that will be measured and each self-corresponding frequency band are stored in the ram of FPGA (or main control chip).
Input signal refers to the proportionate relationship in the virtual value proportionate relationship of output signal under measuring some frequencies respectively：
The proportionate relationship for being obtained by the energy differential conversion for measuring.
One conversion example is as follows：
Measured at 150MHz, output signal is about 1dB with the difference power of input signal.Then input signal and output signal
Amplitude ratio AI/AOIt is as follows：
The corrected parameter of 160-140MHz frequency ranges can be then set near 1.122 with reference to other frequency measurement results.
Each self-corresponding frequency band refers to：According to frequency, 200-180MHz, 180-160MHz, 160- can be divided into
140MHz、……40-20MHz、20-1MHz；
1000-800KHz、800-600KHz、……200-100KHz、100-5KHz；
5000Hz-1KHz、1KHz-500Hz、500Hz-50Hz。
As shown in figure 3, signal frequency range is divided into three sections：50Hz-5KHz, 5KHz-1MHz, 1MHz-200MHz, are used to respectively
Under type extracts sampled value from DDR：
50Hz-5KHz sections：40000 times are taken out value, equivalent 12.5KHz sample rates.One complete cycle sampled point of 50Hz signals
It is 250 points；One complete cycle sampled point number of 5KHz signals is 2.5 points.
5KHz-1MHz sections：200 times are taken out value, equivalent 2.5MHz sample rates.One complete cycle sampled point of 5KHz signals is
500 points；1MHz signal integrity sampling periods sampling number is 2.5 points.
1MHz-200MHz sections：Do not take out value, original 500MHz sample rates.One complete cycle sampled point of 1MHz signals is 500
Point；200MHz signal integrity sampling periods sampling number is 2.5 points.
During above-mentioned frequency range is divided, in each frequency range highest frequency equivalent sampling rate less than half, meet how
Qwest's bandwidth；Meanwhile, each section after 2048 point FFT computings respective minimum frequency resolution ratio be respectively
6.103515625Hz, 1.220703125KHz and 0.244140625MHz, can preferably tell the minimum of each frequency range
Frequency.In order to prevent obscuring.Signal 3 big frequency ranges have been divided into example.Assuming that carrying out Frequency Estimation to 50-5KHz frequency ranges
Shi Buneng tells minimum 50Hz frequencies, then very likely by the Frequency Estimation of sampled signal be 0Hz so as to obtain mistake repair
On the occasion of, and cause digital system operation exception.
Each frequency range extracts 200 sampled points, and 2048 point FFT computings (all mending 0 in not enough part) are carried out respectively.Will meter
Calculate result and be sequentially sent to cordic units, extract the corresponding frequency of amplitude response highest point；By the frequency for extracting and each frequency range
Interior minimum frequency resolution ratio is multiplied, and obtains actual frequency estimation.
cordic：Coordinate Rotation Digital computational methods.A stone resource in FPGA is referred in text, the unit is used
The amplitude and phase information of signal are extracted after input signal FFT.
To ensure the accuracy of Frequency Estimation, each frequency range sampling number at least needs at 200 points, then once complete frequency
Estimate at least to need 8000000 sampled points, required memory space to be about 15.3M bytes, the required sampling time is about
16ms。
Algorithm time delay about 30us of the frequency estimation algorithm from extraction sampled value to needed for extracting bigness scale frequency values.
According to the signal frequency estimate in this period, with reference to the numeral that playback is treated when signal playback is carried out for measuring
Signal is compensated, it is ensured that inband signaling amplitude response substantially flat.
Above example only expresses embodiments of the present invention, therefore its description is more specific and detailed, but can not be
And it is interpreted as the limitation to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, not
On the premise of departing from present inventive concept, various modifications and improvements can be made, these belong to protection scope of the present invention.Cause
This, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (5)
1. it is a kind of that the broadband signal sampling playback system for compensating is divided based on frequency range, it is characterised in that including：
Input analog signal conditioner circuit (101)：The first broadband analog signal is received, and the first broadband analog signal is entered
The preliminary conditioning of row；
AD(20)：The first broadband analog signal after input analog signal conditioner circuit (101) tentatively conditioning is received, and
The first broadband analog signal after preliminary conditioning is converted into the first digital quantity signal；
Digital signal processing module：The first digital quantity signal that the AD (20) is exported is received, and the first digital quantity signal is carried out
Sampling, storage and playback；
DA(40)：The first digital quantity signal after the digital signal processing module is sampled, stored and played back is received, and will be adopted
The first digital quantity signal after sample, storage and playback is converted into the second broadband analog signal；
Output analog signal conditioner circuit (102)：The second broadband analog signal that the DA (40) is exported is received, to second
Broadband analog signal is nursed one's health, and by conditioning after the second broadband analog signal output.
2. it is according to claim 1 it is a kind of based on frequency range divide compensation broadband signal sample playback system, its feature
It is：The digital signal processing module includes FPGA (50) and DDR3SDRAM (60), and FPGA (50) mounting is described
DDR3SDRAM (60), the FPGA (50) carries out Frequency Estimation and corrects to first digital quantity signal；It is described
DDR3SDRAM (60) is stored to first digital quantity signal.
3. it is according to claim 1 it is a kind of based on frequency range divide compensation broadband signal sample playback system, its feature
It is：The first broadband analog signal is hundred hertz to hundred megahertzs.
4. it is according to claim 1 it is a kind of based on frequency range divide compensation broadband signal sample playback system, its feature
It is：The digital signal processing module segmentation carries out continuous sampling to first digital quantity signal.
5. it is a kind of to use the method that the broadband signal sampling playback system for compensating is divided based on frequency range, it is characterised in that including
Following steps：
1) digital signal processing module buffers (70) and continuously reads the first digital quantity signal that AD (20) samples by a FIFO；
2) DDR3SDRAM (60) mounted using FPGA (50) periodically caches a collection of continuous first digital quantity signal；
3) FPGA (50) divides multiple frequency ranges according to the frequency range of the first pending digital quantity signal, for each frequency range from
Extracted data in DDR3SDRAM (60)；
4) FFT computings are carried out respectively to the data for extracting, the result feeding cordic units of FFT is extracted into the width of corresponding data
Degree response, by comparing, judges the main signal frequency of current demand signal, while frequency information also is notified into primary processor；
5) signal for treating playback with the compensating parameter for obtaining in advance according to main signal frequency carries out digital compensation, and according to master control
Program command buffers (80) and transfers data to DA (40) externally to play back by the 2nd FIFO.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108445366A (en) * | 2018-05-09 | 2018-08-24 | 国网浙江省电力有限公司电力科学研究院 | Local discharge signal playback reproducer and its application method |
| CN108536759A (en) * | 2018-03-20 | 2018-09-14 | 阿里巴巴集团控股有限公司 | A kind of sample playback data access method and device |
| CN112532244A (en) * | 2020-12-14 | 2021-03-19 | 天津光电通信技术有限公司 | High-speed collection system of intermediate frequency based on PXIE |
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| CN104155630A (en) * | 2014-08-08 | 2014-11-19 | 浙江大学 | High-speed data record storage and playback system |
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| CN2791746Y (en) * | 2005-04-04 | 2006-06-28 | 苏州鹞鹰数据技术有限公司 | High-speed high-precision analogue sigual collection playback card |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108536759A (en) * | 2018-03-20 | 2018-09-14 | 阿里巴巴集团控股有限公司 | A kind of sample playback data access method and device |
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| CN108536759B (en) * | 2018-03-20 | 2020-08-04 | 阿里巴巴集团控股有限公司 | Sample playback data access method and device |
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| CN108445366A (en) * | 2018-05-09 | 2018-08-24 | 国网浙江省电力有限公司电力科学研究院 | Local discharge signal playback reproducer and its application method |
| CN112532244A (en) * | 2020-12-14 | 2021-03-19 | 天津光电通信技术有限公司 | High-speed collection system of intermediate frequency based on PXIE |
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