CN206301654U - laminated chip inductor - Google Patents
laminated chip inductor Download PDFInfo
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- CN206301654U CN206301654U CN201621180199.1U CN201621180199U CN206301654U CN 206301654 U CN206301654 U CN 206301654U CN 201621180199 U CN201621180199 U CN 201621180199U CN 206301654 U CN206301654 U CN 206301654U
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- Prior art keywords
- layer
- electrode coil
- lid
- chip inductor
- laminated chip
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- 238000007639 printing Methods 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 140
- 229910000859 α-Fe Inorganic materials 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000003475 lamination Methods 0.000 claims description 8
- 239000002002 slurry Substances 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 239000004332 silver Substances 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 3
- 208000037656 Respiratory Sounds Diseases 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000005266 casting Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
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Abstract
A kind of laminated chip inductor, it includes the first lid, intermediate layer and the second lid that stack gradually, intermediate layer includes trace layer and dielectric layer, trace layer is set near the first lid or the second lid, electrode coil and packed layer are printed with dielectric layer, packed layer printing is filled in electrode coil surrounding.Laminated chip inductor of the present utility model can effectively improve product rated current using filling technique around repeat print internal electrode coil and internal electrode coil, reduce D.C. resistance；Meanwhile, also help and solve pin hole around the internal electrode coil that internal electrode coil height increase causes, crack problem, so as to reduce interiors of products design defect, improve product reliability.The utility model also provides a kind of manufacture method of the laminated chip inductor.
Description
Technical field
The utility model is related to field of electrical components, more particularly to a kind of laminated chip inductor.
Background technology
To meet people to the higher and higher requirement of electronic product, though it is foreseeable that laminated inductive application forward direction is small
The directions such as size, high band, high-power and low energy consumption are developed.Lamination sheet type high power inductors are to solve electromagnetic compatibility problem most
One of effective element, it can both ensure preferably to absorb power supply noise in the case where larger DC current is loaded, and can meet new again
The slice structure requirement that electronic equipment volume is small, lightweight surface is installed, the electromagnetism for being particularly suited for eliminating power circuit is done
Disturb, in the field extensive use such as automobile and mobile phone electronic.
However, common chip inductor is that the planarization single of inductance coil is printed in multi-layer ferrite film strips, then
By multi-layer ferrite film strips by laminate shaping after it is low temperature co-fired form, the electrode coil thickness that it has the disadvantage product is small, product
D.C. resistance is high, and rated current is low, and DC superposition characteristic is poor, and inductance value is very big with the increase reduction amplitude of electric current, and product is resistance to
Current capability is poor, strictly limits it on probation under high current environment.
Utility model content
Based on this, it is necessary to provide a kind of rated current higher and having larger DC current by lower product inductance simultaneously
The amount less laminated chip inductor of reduction amplitude.
A kind of laminated chip inductor, it includes the first lid, intermediate layer and the second lid that stack gradually, it is described in
Interbed includes the trace layer and two-layer above dielectric layer of parallel lamination, and the trace layer is near first lid or described second
Lid is set, and electrode coil and packed layer are printed with the dielectric layer, and the packed layer printing is filled in the electrode coil
Surrounding.
Wherein in one embodiment, the electrode coil is superimposition printing at least two-layer on the dielectric layer.
Wherein in one embodiment, the dielectric layer includes first medium layer and second dielectric layer, the first medium
Layer superimposed layer is printed with least two-layer first electrode coil, and the second dielectric layer superimposed layer is printed with least two-layer second electrode
Coil, the first electrode coil and the second electrode coil are connected up by the way of parallel connection.
Wherein in one embodiment, the first electrode coil and the second electrode coil are printed using plasticity silver paste
Scopiform into.
Wherein in one embodiment, the packed layer first electrode coil and second electricity for single is printed on
High viscosity ferrite slurry around polar curve circle.
Wherein in one embodiment, the trace layer includes the first trace layer and the second trace layer, first lead
Layer is printed with first near second lid near first lid, second trace layer in first trace layer
Lead, the second lead is printed with second trace layer.
Wherein in one embodiment, the laminated chip inductor includes that nonmagnetic ceramic separates interlayer, the non-magnetic
Property ceramics cut-off interlayer be located at any a layer between first lid and second lid.
Wherein in one embodiment, on the trace layer, the dielectric layer and the nonmagnetic ceramic cut-off interlayer all
Connecting hole is provided with, the connecting hole is contained within the metallic conductor for connecting the electrode coil on the adjacent dielectric layer.
Laminated chip inductor of the present utility model is used around repeat print internal electrode coil and internal electrode coil
Filling technique, can effectively improve product rated current, reduce D.C. resistance；Meanwhile, also help solution internal electrode line
Circle highly increases pin hole around the internal electrode coil for causing, crack problem, so as to reduce interiors of products design defect, improves and produces
Product reliability.Additionally, technology of the present utility model is applied to the development and production of all of laminated chip inductor, do not changing
In the case of existing production equipment, the slightly improvement of technology is only needed, can just meet laminated chip inductor development and life
Produce, promote the marketing of the technology.
Brief description of the drawings
Fig. 1 is the structure chart of laminated chip inductor in the utility model preferred embodiment；
Fig. 2 is the sectional view of laminated chip inductor dielectric layer shown in Fig. 1；
Fig. 3 is the manufacture method flow chart of laminated chip inductor shown in Fig. 1.
Specific embodiment
For the ease of understanding the utility model, the utility model is more fully retouched below with reference to relevant drawings
State.Preferred embodiment of the present utility model is given in accompanying drawing.But, the utility model can come real in many different forms
It is existing, however it is not limited to embodiment described herein.On the contrary, the purpose for providing these embodiments is made to public affairs of the present utility model
The understanding for opening content is more thorough comprehensive.
It should be noted that when element is referred to as " being fixed on " another element, it can directly on another element
Or can also there is element placed in the middle.When an element is considered as " connection " another element, it can be directly connected to
To another element or may be simultaneously present centering elements.
Unless otherwise defined, all of technologies and scientific terms used here by the article is led with technology of the present utility model is belonged to
The implication that the technical staff in domain is generally understood that is identical.It is herein to be in term used in the description of the present utility model
The purpose of description specific embodiment, it is not intended that in limitation the utility model.Term as used herein " and/or " include
The arbitrary and all of combination of one or more related Listed Items.
Fig. 1 is refer to, in the utility model preferred embodiment, laminated chip inductor includes the first lid for stacking gradually
100th, intermediate layer and the second lid 300.First lid 100 and the second lid 300 are the Ferrite Material diaphragm not punched,
Intermediate layer includes more than the trace layer and two-layer of parallel lamination being printed on the dielectric layer of electrode coil.Electrode wires in adjacent dielectric
Circle is connected up by the way of parallel connection, and trace layer is set near the first lid 100 or the second lid 300.Wherein, the first lid
The lid 300 of body 100 and second is constituted by more than one layer of Ferrite Material diaphragm, i.e. the first lid 100 and the second lid 300
Thickness be all higher than or be printed on equal to each layer electrode coil dielectric layer thickness.
Specifically, trace layer includes the first trace layer 210 and the second trace layer 250, and dielectric layer includes first medium layer 220
With second dielectric layer 230.
, near the first lid 100, the second trace layer 250 is near the second lid 300 for first trace layer 210.First trace layer
The first lead (not shown) is printed with 210, the second lead (not shown) is printed with the second trace layer 250.In lamination
The first lead can be directly printed on the first lid 100 for making or the is directly printed on the second lid 300 for making
Two leads.
First electrode coil 222 and second electrode coil are printed with respectively in first medium layer 220 and second dielectric layer 230
232.Wherein, the structure of first electrode coil 222 and second electrode coil 232 is essentially identical, and both are using parallel connection
Mode is connected up.
Specifically, first electrode coil 222 is superimposition printing at least two-layer on first medium layer 220, similarly, the
Two electrode coils 232 are also superimposition printing at least two-layer in second dielectric layer 230.In this specific embodiment, using can
Plasticity silver paste is printed in first medium layer 220 and the surface of second dielectric layer 230 to form first electrode coil 222 and second electrode
Coil 232, the viscosity ratio of wherein plasticity silver paste is higher, and certain height can be retained after printing without collapsing modification, and
One electrode coil 222 and the thickness of second electrode coil 232 are up to 50 μm.
In addition, the first electrode coil 222 being printed in first medium layer 220 and second dielectric layer 230 and second electrode
Coil 232 is the two-layer repeated print, and so by the way of electrode coil of repeating print, can effectively improve laminated sheet
More than 2 times of formula inductor rated current, reduces by 3 times or so of D.C. resistance.
Fig. 2 is refer to, further, packed layer 224 is printed with first medium layer 220 and second dielectric layer 230, filled
The printing of layer 224 is filled in the surrounding of first electrode coil 222 and second electrode coil 232 and covers whole first medium layer 220
With the surface of second dielectric layer 230.In this specific embodiment, packed layer 224 is printed on first electrode coil 222 and for single
High viscosity ferrite slurry around two electrode coils 232, and the thickness of packed layer 224 is equal to the thickness of 1/2 first electrode coil 222
Degree, about 25 μm, width is about 80 μm.Wherein, high-viscosity ferrite slurry material is identical with large power ferrite slurry, area
It is not that its viscosity is higher.
Can effectively solve first electrode coil 222 and the height of second electrode coil 232 using filling technique increases what is caused
First electrode coil 222 and the surrounding pin hole of second electrode coil 232, crack problem, so as to reduce the interior of laminated chip inductor
Portion's design defect, improves the reliability of laminated chip inductor.
It is to be appreciated that in other embodiments, it is same between first medium layer 220 and the first trace layer 210 can be with
Have more than the one layer dielectric layer for being printed on electrode coil, can also have between the trace layer 250 of second dielectric layer 230 and second one layer with
On be printed on the dielectric layer of electrode coil, but to ensure that the electrode coil in adjacent dielectric is connected up by the way of parallel connection.
In other embodiments, intermediate layer also includes that nonmagnetic ceramic separates interlayer 240, nonmagnetic ceramic cut-off interlayer
240 are located at any a layer between the first lid 100 and the second lid 300, and it can reduce product magnetic saturation intensity, effectively improve
Laminated chip inductor DC superposition characteristic, is allowed to rated current and is improved, and reduces its D.C. resistance.
Further, the first trace layer 210, first medium layer 220, second dielectric layer 230, nonmagnetic ceramic cut-off interlayer
240 and second are designed with connecting hole in trace layer 250, and connecting hole is contained within for connecting adjacent dielectric (such as this specific implementation
First medium layer 220 and second dielectric layer 230 in example) Top electrode coil (first electrode coil 222 and second electrode coil 232)
Metallic conductor.
Fig. 3 is refer to, the utility model also provides a kind of manufacture method of laminated chip inductor, and it includes following step
Suddenly：
S10：Prepare ferrite slurry.
S20:Above-mentioned ferrite slurry is cast with casting machine is fabricated to film strips.
S30：Above-mentioned film strips are cut into medium diaphragm of the same size on guillotine, and with puncher in the medium
Punched on diaphragm, the medium diaphragm not punched is made into the first lid 100 and the second lid 300.
S40：According to setting pattern printing lead on the medium diaphragm for having punched, it is allowed to form trace layer.It is specific at this
In embodiment, according to setting pattern printing lead on the medium diaphragm for having punched, it is allowed to form the He of the first trace layer 210 respectively
Second trace layer 250.
S50：According to electrode in setting pattern printing on the medium diaphragm for having punched, it is allowed to be formed and is printed with electrode coil
Dielectric layer.In this specific embodiment, printing to be formed respectively on the medium diaphragm for having punched has first electrode coil 222
First medium the layer 220 and second dielectric layer 230 with second electrode coil 232.Wherein, first electrode coil 222 and
Two electrode coils 232 are at least two-layer being printed on correspondence medium diaphragm, to improve the specified electricity of laminated chip inductor
Stream.
S60：Filling packed layer is printed around electrode coil.Specifically, in first electrode coil 222 and second electrode line
232 surroundings printing filling packed layer 224 is enclosed, with by the first electrode coil 222 of packed layer 224 and second electrode coil 232 weeks
Pin hole and crackle are enclosed, so as to improve the reliability of laminated chip inductor.
S70：The first trace layer 210, the first medium layer 220, trace layer of second dielectric layer 230 and second that will be completed for printing
250 form intermediate layer 200 by parallel lamination, and by the first trace layer 210 near the first lid 100, the second trace layer 250 is leaned on
The principle of nearly second lid 300, by the first lid 100, the lid 300 of intermediate layer 200 and second, lamination forms lamination in order
Chip inductor.
In addition, the electrode coil being printed in the dielectric layer of electrode coil at least two-layer, and adjacent dielectric is using parallel
Mode in parallel is connected up.And also include manufacture nonmagnetic ceramic cut-off interlayer 240 in the present embodiment and be stacked in the first lid
The step of between the lid 300 of body 100 and second.
S80：Laminated chip inductor is cut, dumping, sintering, chamfering are separated into single laminated chip inductor.
S90：By each laminated chip inductor carry out termination treatment and sorting braid, obtain laminated chip inductor into
Product.
Laminated chip inductor of the present utility model is using the internal electrode coil (He of first electrode coil 222 of repeating print
Second electrode coil 232) and internal electrode coil around filling technique, can effectively improve product rated current, reduce straight
Leakage resistance；Meanwhile, also helping and solve pin hole around the internal electrode coil that internal electrode coil height increase causes, crackle is asked
Topic, so as to reduce interiors of products design defect, improves product reliability.Additionally, technology of the present utility model is suitable for all of
The development of laminated chip inductor and production, in the case where existing production equipment is not changed, only need technology slightly
Improve, can just meet laminated chip inductor development and production, promote the marketing of the technology.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more specific and detailed,
But therefore can not be interpreted as the limitation to the utility model the scope of the claims.It should be pointed out that common for this area
For technical staff, without departing from the concept of the premise utility, various modifications and improvements can be made, these all belong to
In protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (8)
1. a kind of laminated chip inductor, it is characterised in that：Including the first lid, intermediate layer and the second lid that stack gradually
Body, the intermediate layer includes the trace layer and two-layer above dielectric layer of parallel lamination, and the trace layer is near first lid
Or second lid is set, electrode coil and packed layer are printed with the dielectric layer, the packed layer printing is filled in institute
State electrode coil surrounding.
2. laminated chip inductor as claimed in claim 1, it is characterised in that：The electrode coil is superimposition printing in described
At least two-layer on dielectric layer.
3. laminated chip inductor as claimed in claim 1, it is characterised in that：The dielectric layer includes first medium layer and the
Second medium layer, the first medium layer superimposed layer is printed with least two-layer first electrode coil, the second dielectric layer superimposed layer
At least two-layer second electrode coil is printed with, the first electrode coil and the second electrode coil use the side of parallel connection
Formula is connected up.
4. laminated chip inductor as claimed in claim 3, it is characterised in that：The first electrode coil and second electricity
Polar curve circle prints to be formed using plasticity silver paste.
5. laminated chip inductor as claimed in claim 4, it is characterised in that：The packed layer is described for single is printed on
High viscosity ferrite slurry around one electrode coil and the second electrode coil.
6. laminated chip inductor as claimed in claim 1, it is characterised in that：The trace layer includes the first trace layer and the
Two trace layers, first trace layer near first lid, second trace layer near second lid, described the
The first lead is printed with one trace layer, the second lead is printed with second trace layer.
7. laminated chip inductor as claimed in claim 1, it is characterised in that：The laminated chip inductor includes non magnetic
Ceramics cut-off interlayer, the nonmagnetic ceramic cut-off interlayer is located at any between first lid and second lid
Layer.
8. the laminated chip inductor that such as claim 7 is stated, it is characterised in that：The trace layer, the dielectric layer and described non-
Connecting hole is designed with magnetic ceramics cut-off interlayer, the connecting hole is contained within for connecting the electricity on the adjacent dielectric layer
The metallic conductor of polar curve circle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621180199.1U CN206301654U (en) | 2016-10-27 | 2016-10-27 | laminated chip inductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621180199.1U CN206301654U (en) | 2016-10-27 | 2016-10-27 | laminated chip inductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206301654U true CN206301654U (en) | 2017-07-04 |
Family
ID=59202745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621180199.1U Expired - Fee Related CN206301654U (en) | 2016-10-27 | 2016-10-27 | laminated chip inductor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206301654U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106373712A (en) * | 2016-10-27 | 2017-02-01 | 深圳振华富电子有限公司 | Laminated chip inductor and manufacturing method thereof |
-
2016
- 2016-10-27 CN CN201621180199.1U patent/CN206301654U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106373712A (en) * | 2016-10-27 | 2017-02-01 | 深圳振华富电子有限公司 | Laminated chip inductor and manufacturing method thereof |
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| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170704 |
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| CF01 | Termination of patent right due to non-payment of annual fee |