CN206271702U - 一种连接led芯片电极与支架电极的金线线弧 - Google Patents

一种连接led芯片电极与支架电极的金线线弧 Download PDF

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CN206271702U
CN206271702U CN201621336876.4U CN201621336876U CN206271702U CN 206271702 U CN206271702 U CN 206271702U CN 201621336876 U CN201621336876 U CN 201621336876U CN 206271702 U CN206271702 U CN 206271702U
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千晓敏
杜汉伟
易瑞吕
王跃飞
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Hongli Zhihui Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

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Abstract

一种连接LED芯片电极与支架电极的金线线弧，包括第一线弧段、第二线弧段、第三线弧段和第四线弧段；所述第一线弧段的起始端与LED芯片的第一电极连接，第一线弧段的末端与第二线弧段的起始端连接，第二线弧段的末端与第三线弧段的起始端连接，第三线弧段的末端与第四线弧段的起始端连接，第四线弧段的末端与支架的第一电极连接；所述第一线弧段为直线段且竖直于LED芯片表面，所述第二线弧段为弧形弯曲段且向LED芯片的第二电极方向凸出；所述第四线弧段贴于支架的第一电极的表面。当线弧整体出现拉扯，第二线弧段和第四线弧段给线弧一定的缓冲，在冷热冲击过程中避免直接拉扯断线的问题。

Description

一种连接LED芯片电极与支架电极的金线线弧
技术领域
本实用新型涉及LED领域，尤其是一种连接LED芯片电极与支架电极的金线线弧。
背景技术
正装LED芯片的电极通过打金线与支架的电极连接，现有金线线型为QA线弧。如图1所示，其打线方式先从LED芯片正极向上拉伸后，向支架正极方向弯曲并直接引到支架的正极，金线的端部与支架正极之间的夹角为锐角。线弧的向上拉伸段与弯曲段的过渡点为B点，线弧的末端靠近与支架电极连接的位置为D点，由于现有的线弧拉的比较直，在冷热冲击过程中易出现死灯，即线弧中的B、D点断开。
发明内容
本实用新型所要解决的技术问题是提供一种连接LED芯片电极与支架电极的金线线弧，金线线弧不容易断。
为解决上述技术问题，本实用新型的技术方案是：一种连接LED芯片电极与支架电极的金线线弧，包括第一线弧段、第二线弧段、第三线弧段和第四线弧段；所述第一线弧段的起始端与LED芯片的第一电极连接，第一线弧段的末端与第二线弧段的起始端连接，第二线弧段的末端与第三线弧段的起始端连接，第三线弧段的末端与第四线弧段的起始端连接，第四线弧段的末端与支架的第一电极连接；所述第一线弧段为直线段且竖直于LED芯片表面，所述第二线弧段为弧形弯曲段且向LED芯片的第二电极方向凸出；所述第四线弧段贴于支架的第一电极的表面。本实用新型在第二线弧段处形成向前凸出的弯曲弧线段，使其在向后拉扯是具有一定的缓冲，第四线弧段弯折并贴地式，使其在向前拉扯时具有一定的缓冲；当线弧整体出现拉扯，第二线弧段和第四线弧段给线弧一定的缓冲，在冷热冲击过程中避免直接拉扯断线的问题。
作为改进，所述LED芯片的第一电极为LED芯片的正极；所述支架的第一电极为支架的正极。
作为改进，所述第一线弧段、第二线弧段、第三线弧段和第四线弧段处于同一平面。
作为改进，所述LED芯片为正装芯片。
本实用新型与现有技术相比所带来的有益效果是：
本实用新型在第二线弧段处形成向前凸出的弯曲弧线段，使其在向后拉扯是具有一定的缓冲，第四线弧段弯折并贴地式，使其在向前拉扯时具有一定的缓冲；当线弧整体出现整体向上拉扯时，作用在拉扯点的力为F，金线上B点的受力为F1，D点的受力为F2，金线被拉直后，拉扯点两侧的线弧与拉扯力F之间夹角分别为a1和a2，F＝F1cosa1+F2cos a2；由于本实用新型设置了第二线弧段和第四线弧段，使得金线比传统金线更长，当金线被拉直后，a1和a2变小，则在拉扯点两侧的线弧承受的力相应的减小，且第二线弧段和第四线弧段给线弧一定的缓冲，在冷热冲击过程中避免直接拉扯断线的问题。
附图说明
图1为现有技术LED线弧打线方式。
图2为本实用新型LED线弧打线方式。
图3为B点与D点之间线弧受力分析示意图。
具体实施方式
下面结合说明书附图对本实用新型作进一步说明。
一种连接LED芯片电极与支架电极的金线线弧，所述的LED芯片1为正装芯片，LED芯片1的顶部设有正极2和负极，LED芯片的正、负极通过打线与支架的正、负极连接。如图2所示，LED芯片的正极2与支架的正极7之间的金线线弧包括第一线弧段3、第二线弧段4、第三线弧段5和第四线弧段6；所述第一线弧段3、第二线弧段4、第三线弧段5和第四线弧段6处于同一平面。所述第一线弧段3的起始端与LED芯片的正极连接，第一线弧段3的末端与第二线弧段4的起始端连接且二者之间的连接点为B点，第二线弧段4的末端与第三线弧段5的起始端连接，第三线弧段5的末端与第四线弧段6的起始端连接且二者之间的连接点为D点，第四线弧段6的末端与支架的正极连接。所述第一线弧段3为直线段且竖直于LED芯片表面，所述第二线弧段4为弧形弯曲段且向LED芯片的第二电极方向凸出；第三线弧段5从第二线弧段4的末端向下倾斜拉伸至第四线弧段6；所述第四线弧段6贴于支架的第一电极的表面。
所述第一线弧段3、第二线弧段4、第三线弧段5和第四线弧段6由LED打线机依次打线形成，可通过调整打线头的运动轨迹坐标来改变线弧的形状；本实用新型线弧的打线方式：从LED芯片的正极引出，然后向上拉伸形成第一线弧段3；然后打线头继续向上且偏向LED芯片的负极方向呈弧形轨迹移动形成第二线弧段4；打线头向支架的正极方向向下倾斜移动形成第三线弧段5；最后打线头水平贴地移动形成第四线弧段6。
本实用新型在第二线弧段处形成向前凸出的弯曲弧线段，使其在向后拉扯是具有一定的缓冲，第四线弧段弯折并贴地式，使其在向前拉扯时具有一定的缓冲；如图3所示，当线弧整体出现整体向上拉扯时，作用在拉扯点的力为F，金线上B点的受力为F1，D点的受力为F2，金线被拉直后，拉扯点两侧的线弧与拉扯力F之间夹角分别为a1和a2，F＝F1cos a1+F2cos a2；由于本实用新型设置了第二线弧段和第四线弧段，使得金线比传统金线更长，当金线被拉直后，a1和a2变小，则在拉扯点两侧的线弧承受的力相应的减小，且第二线弧段和第四线弧段给线弧一定的缓冲，在冷热冲击过程中避免直接拉扯断线的问题。

Claims (4)

1.一种连接LED芯片电极与支架电极的金线线弧，其特征在于：包括第一线弧段、第二线弧段、第三线弧段和第四线弧段；所述第一线弧段的起始端与LED芯片的第一电极连接，第一线弧段的末端与第二线弧段的起始端连接，第二线弧段的末端与第三线弧段的起始端连接，第三线弧段的末端与第四线弧段的起始端连接，第四线弧段的末端与支架的第一电极连接；所述第一线弧段为直线段且竖直于LED芯片表面，所述第二线弧段为弧形弯曲段且向LED芯片的第二电极方向凸出；所述第四线弧段贴于支架的第一电极的表面。
2.根据权利要求1所述的一种连接LED芯片电极与支架电极的金线线弧，其特征在于：所述LED芯片的第一电极为LED芯片的正极；所述支架的第一电极为支架的正极。
3.根据权利要求1所述的一种连接LED芯片电极与支架电极的金线线弧，其特征在于：所述第一线弧段、第二线弧段、第三线弧段和第四线弧段处于同一平面。
4.根据权利要求1所述的一种连接LED芯片电极与支架电极的金线线弧，其特征在于：所述LED芯片为正装芯片。
CN201621336876.4U 2016-12-07 2016-12-07 一种连接led芯片电极与支架电极的金线线弧 Expired - Fee Related CN206271702U (zh)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978668A (zh) * 2017-11-28 2018-05-01 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件的导电线的方法
WO2019105075A1 (zh) * 2017-11-28 2019-06-06 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件的导电线的方法
CN109962148A (zh) * 2019-03-27 2019-07-02 旭宇光电（深圳）股份有限公司 Led封装结构

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107978668A (zh) * 2017-11-28 2018-05-01 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件的导电线的方法
WO2019105075A1 (zh) * 2017-11-28 2019-06-06 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件的导电线的方法
CN107978668B (zh) * 2017-11-28 2019-06-21 佛山市国星光电股份有限公司 Led器件、led灯及加工led器件的导电线的方法
US11502231B2 (en) 2017-11-28 2022-11-15 Foshan Nationstar Optoelectronics Co., Ltd Light-emitting diode device, LED lamp and method for machining conductive wire of LED device
CN109962148A (zh) * 2019-03-27 2019-07-02 旭宇光电（深圳）股份有限公司 Led封装结构

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