CN206210617U - Chip is combined component - Google Patents
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- CN206210617U CN206210617U CN201621105493.6U CN201621105493U CN206210617U CN 206210617 U CN206210617 U CN 206210617U CN 201621105493 U CN201621105493 U CN 201621105493U CN 206210617 U CN206210617 U CN 206210617U
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Abstract
Component is combined the utility model discloses a kind of chip.A kind of compound component of chip includes：Ceramic body, ceramic body includes：First medium layer, first electrode layer, the second electrode lay, second dielectric layer, 3rd electrode layer, 3rd dielectric layer and the 4th electrode layer, the first gap is formed between first electrode layer and first side, the second gap is formed between first electrode layer and second side, third space is formed between 4th electrode layer and heptalateral side, the 4th gap is formed between 4th electrode layer and the 8th side, width of the width of third space more than the first gap, width lateral electrode of the width in the 4th gap less than the second gap, it is attached to the side of ceramic body, and electrically connected with least one of the second electrode lay and the 3rd electrode layer；Resistance, is completely covered lateral electrode and extends to first surface and the 4th surface, and resistance is electrically connected with first electrode layer and the 4th electrode layer.The compound component structure of this chip is compact.
Description
Technical field
The utility model is related to field of electrical components, and component is combined more particularly, to a kind of chip.
Background technology
With the development of science and technology, electronic product makes rapid progress, the major requirement to component is miniaturization and multifunction.
In many circuit applications, it is necessary to using resistance and capacitances in series structure circuit when, generally use discrete component, i.e., single electricity
Resistance and single electric capacity, so take more circuit space, are unfavorable for the miniaturization of whole machine, and mount less efficient.
Utility model content
Based on this, it is necessary to provide a kind of compact conformation, prepare the compound component of chip of convenient resistance capacitance series connection.
A kind of chip is combined component, including：
Ceramic body, the ceramic body is cuboid, and the ceramic body includes：
First medium layer, the first medium layer has relative first surface and second surface, the first surface tool
There is relative first side and second side, the second surface has relative the 3rd side and four side；
First electrode layer, is formed at the first surface of the first medium layer, the first electrode layer and first side
The first gap is formed between side, the second gap is formed between the first electrode layer and the second side；
The second electrode lay, is formed at the second surface of the first medium layer, the second electrode lay and the 3rd side
While and at least one of the four side at least partly it is concordant formed draw while；
Second dielectric layer, is laminated in the surface of the second electrode lay and the second surface is completely covered, and described second
Dielectric layer has the 3rd surface, and the 3rd surface is a side surface of the second dielectric layer away from first medium layer,
3rd surface has relative the 5th side and the 6th side；
3rd electrode layer, is formed at the 3rd surface, and the 3rd electrode layer and the 5th side and described
At least partly concordant formation draws side at least one of six sides；
3rd dielectric layer, is laminated in the surface of the 3rd electrode layer and the 3rd surface is completely covered, and the described 3rd
Dielectric layer has the 4th surface, and the 4th surface is a side surface of the 3rd dielectric layer away from the second dielectric layer,
4th surface has a relative heptalateral side and the 8th side, the heptalateral side the first surface orthographic projection with
The first side overlaps；
4th electrode layer, is formed at the 4th surface, is formed between the 4th electrode layer and the heptalateral side
Third space, is formed with the 4th gap between the 4th electrode layer and the 8th side, the width of the third space is big
In the width in first gap, the width of the width less than second gap in the 4th gap；
Lateral electrode, is attached to the side of the ceramic body, and with the second electrode lay and the 3rd electrode layer at least
One electrical connection；
Resistance, is completely covered the lateral electrode and extends to the first surface and the 4th surface, the resistance with it is described
An electrical connection in first electrode layer and the 4th electrode layer.
Wherein in one embodiment, orthographic projection and described first electricity of the second electrode lay in the first electrode layer
Pole layer is least partially overlapped；Orthographic projection and fourth electrode layer at least portion of 3rd electrode layer in the 4th electrode layer
Divide and overlap.
Wherein in one embodiment, orthographic projection and the second electrode of the 3rd electrode layer in the second surface
Layer overlaps.
Wherein in one embodiment, the second electrode lay extends to the four side from the 3rd side；And/
Or, the 3rd electrode layer extends to the 6th side from the 5th side.
Wherein in one embodiment, orthographic projection and threeth electrode of the second electrode lay on the 3rd surface
Layer is overlapped.
Wherein in one embodiment, the width 0.2mm~0.5mm bigger than the width in the first gap of the third space；
And/or, the width big 0.2mm~0.5mm of the width than the 4th gap in second gap.
Wherein in one embodiment, the second electrode lay extend to the four side from the 3rd side and with it is described
Be formed with gap between four side, the 3rd electrode layer extend to the 5th side from the 6th side and with it is described
Gap is formed between 5th side, the 3rd side and the 5th side are located at same one end of the second dielectric layer.
Wherein in one embodiment, the lateral electrode includes the first lateral electrode and the second lateral electrode, and the resistance includes
First resistor and second resistance, the first lateral electrode be attached to the one side of the ceramic body and with the second electrode lay and the 3rd electricity
Pole layer in one electrical connection, second lateral electrode be attached to the another side of the ceramic body and with the second electrode lay
And the 3rd another electrical connection in electrode layer, the first resistor be completely covered first lateral electrode and with the described first electricity
Pole layer and the 4th electrode layer in one electrical connection, the second resistance be completely covered second lateral electrode and with it is described
Another electrical connection in first electrode layer and the 4th electrode layer.
Wherein in one embodiment, the first surface, second surface, the 3rd surface and the 4th surface are pros
Shape, the second electrode lay is completely covered the second surface, and the 3rd electrode layer is completely covered the 3rd surface, described
It is each formed with gap between first electrode layer and four sides of the first surface, the 4th electrode layer and the 4th surface
Gap is each formed between four sides.
Above-mentioned chip is combined component, is formed with outside line by first electrode layer and the 4th electrode layer and electrically connected, when
When lateral electrode and resistance are attached to the first side of ceramic body, first electrode layer, first medium layer and the second electrode lay form electricity
Hold, the part resistance positioned at the 4th electrode layer or between first electrode layer and lateral electrode 130 constitutes tandem junction with capacitances in series
Structure, so as to resistance and electric capacity are integrated into discrete component, structure is more compact；By adjusting first electrode layer and second electrode
The dielectric constant of the facing area, the thickness of first medium layer and first medium layer of layer can easily obtain different electric capacity
Amount, can easily be obtained by the resistivity and first electrode layer or the 4th electrode layer that adjust resistance with the gap of lateral electrode
Different resistance values, the compound component of chip can be conveniently adjusted by the thickness for adjusting first medium layer and second dielectric layer
Thickness, it is with strong applicability；In the preparation, due to the width of the width more than the first gap of third space, the width in the 4th gap
One end of ceramic body is prepared resistance by degree less than the width in the second gap using infusion process, by adjusting the depth of immersion, can be made
Resistance is electrically connected with first electrode layer and the 4th electrode layer.
Brief description of the drawings
Fig. 1 is the three-dimensional assembling structure schematic diagram of the compound component of chip of an implementation method；
Fig. 2 is profile of the compound component of chip in Fig. 1 along II-II lines；
Fig. 3 is the decomposing schematic representation of the ceramic body of the compound component of chip in Fig. 1；
Fig. 4 is the three-dimensional assembling structure schematic diagram of the compound component of chip of another implementation method；
Fig. 5 is profile of the compound component of chip in Fig. 4 along V-V lines；
Fig. 6 is the decomposing schematic representation of the ceramic body of the compound component of chip in Fig. 4；
Fig. 7 is the three-dimensional assembling structure schematic diagram of the compound component of chip of another implementation method；
Fig. 8 is profile of the compound component of chip in Fig. 4 along VIII-VIII lines；
Fig. 9 is the decomposing schematic representation of the ceramic body of the compound component of chip in Fig. 7.
Specific embodiment
The compound component of chip is described in further detail mainly in combination with accompanying drawing below.
Please refer to Fig. 1, Fig. 2 and Fig. 3, the compound component 100 of chip of an implementation method includes ceramic body 110, shape
Into in the lateral electrode 130 and resistance 150 of the side of ceramic body 110.
Ceramic body 110 is cuboid, in the illustrated embodiment, the substantially cuboid of ceramic body 110, certainly, at it
In his embodiment, ceramic body 110 can also be square.Ceramic body 110 includes the first electrode layer 112, first for stacking gradually
Dielectric layer 111, the second electrode lay 113, second dielectric layer 114, the 3rd electrode layer 115, the 3rd dielectric layer 116 and the 4th electrode layer
117。
In the illustrated embodiment, first medium layer 111 is rectangular patch, with relative first surface (figure is not marked)
And second surface 1112.Certainly, in other embodiments, first medium layer 111 can also be square sheet or other shapes
Shape.
First surface has relative first side and second side.In the illustrated embodiment, first surface is square
Shape, first side and second side are the short side of rectangle.
Second surface 1112 has the 3rd relative side and four side.In the illustrated embodiment, second surface
1112 is rectangle, and the 3rd side and four side are the short side of rectangle.
First electrode layer 112 is laminated in first surface.In the illustrated embodiment, the substantially square of first electrode layer 112
Shape, the length of first electrode layer 112 is more slightly shorter than the length of first surface.It is formed between first electrode layer 112 and first side
First gap.The width in the first gap is 0.2mm~0.5mm.It is formed between second between first electrode layer 112 and second side
Gap, the width 0.2mm~0.5mm bigger than the width in the first gap in the second gap.In the illustrated embodiment, first electrode layer
112 width is equal with the width of first surface, i.e., first electrode layer 112 is put down with the two other lateral section of first surface
Together.
The second electrode lay 113 is laminated in second surface 1112.The second electrode lay 113 prolongs from four side to the 3rd side
Stretch.3rd side is located at same one end of first medium layer 111 with first side.In the illustrated embodiment, the second electrode lay
113 is rectangle, and the length of the second electrode lay 113 is identical with the length of second surface 1112, and the second electrode lay 113 is from four side
The 3rd side is extended to, certainly, being formed with width in other embodiments, between the side of the second electrode lay 113 and the 3rd is
The gap of 0.2mm~0.5mm.
The width of the second electrode lay 113 is less than the width of second surface 1112, the second electrode lay 113 and second surface 1112
Two other side between to be formed with width be the gap more than 0.2mm.In the illustrated embodiment, gap has certain
Width, certainly in other embodiments, the width in gap can be 0, that is, the second electrode lay 113 width and second surface
1112 width are identical.In the illustrated embodiment, the side concordant with the 3rd side and four side of the second electrode lay 113 is to draw
Go out side.
In the illustrated embodiment, orthographic projection and the second electrode lay 113 of the first electrode layer 112 in second surface 1112
Partly overlap.The second electrode lay 113 is not covered with the entire area of second surface 1112, such that it is able to increase second dielectric layer
Bonding force between 114 and first medium layer 111.
Second dielectric layer 114 is laminated in the surface of the second electrode lay 113.Second dielectric layer 114 is rectangular patch, in diagram
Implementation method in, second dielectric layer 114 is completely covered the surface of the second electrode lay 113 and second surface 1112.Second medium
Layer 114 is the 3rd surface 1141 away from a side surface of first medium layer 111.3rd surface 1141 is substantially rectangular, with phase
To the 5th side and the 6th side, the 5th side and the 6th side are short side.In the illustrated embodiment, first side,
3rd side and the 5th side are located at the first end of ceramic body 110, and second side, four side and the 6th side are located at ceramic body
110 the second end.
3rd electrode layer 115 is formed at a side surface of the second dielectric layer 114 away from first medium layer 111.In diagram
In implementation method, the 3rd electrode layer 115 is rectangle, and the 3rd electrode layer 115 is from the 6th side on the 3rd surface 1141 to the 5th side
Side extends, and the length of the 3rd electrode layer 115 is identical with the length on the 3rd surface 1141, certainly, in other embodiments, the 3rd
The gap that width is 0.2mm~0.5mm is formed between the side of electrode layer 115 and the 5th.
The width of the 3rd electrode layer 115 is less than the width on the 3rd surface 1141, the 3rd electrode layer 115 and the 3rd surface 1141
Two other side between to be formed with width be the gap more than 0.2mm, in the illustrated embodiment, gap has certain
Width, certainly in other embodiments, the width in gap can be 0, that is, the 3rd electrode layer 115 width and the 3rd surface
1141 width are identical.3rd electrode layer 115 it is concordant with the 5th side and the 6th side while for draw while.In the embodiment party of diagram
In formula, the 3rd electrode layer 115 is completely overlapped with the second electrode lay 113 in the orthographic projection of second surface 1141, certainly, in other realities
Apply in mode, the 3rd electrode layer 115 can also partly overlap in the orthographic projection of second surface 1141 with the second electrode lay 113.
3rd dielectric layer 116 is laminated in the surface of the 3rd electrode layer 115.3rd dielectric layer 116 is rectangular patch, in diagram
Implementation method in, the 3rd dielectric layer 116 is completely covered the surface on the 3rd electrode layer 115 and the 3rd surface 1141.3rd medium
Layer 116 is the 4th surface 1161 away from a side surface of second dielectric layer 114.4th surface 1161 is substantially rectangular, with phase
To heptalateral side and the 8th side, heptalateral side and the 8th side are short side.In the illustrated embodiment, first side,
3rd side, the 5th side and heptalateral side be located at ceramic body 110 first end, second side, four side, the 6th side and
8th side is located at the second end of ceramic body 110.Heptalateral side is Chong Die with first side in the orthographic projection of first surface.
4th electrode layer 117 is laminated in the 4th surface 1161.In the illustrated embodiment, the 4th electrode layer 117 is square
Shape, the length of the 4th electrode layer 117 is more slightly shorter than the length on the 4th surface 1161.Shape between 4th electrode layer 117 and heptalateral side
Into there is third space, the 4th gap is formed between the 4th electrode layer 117 and the 8th side.The width in the 4th gap is 0.2mm
~0.5mm.The width of third space is than the first gap and the big 0.2mm~0.5mm of width in the 4th gap.In the embodiment party of diagram
In formula, the width of the 4th electrode layer 117 is equal with the width on the 4th surface 1161, i.e. the 4th electrode layer 117 and the 4th surface
1161 two other lateral section is concordant.Orthographic projection and first electrode layer 112 of 4th electrode layer 117 in first surface 1112
Partly overlap.
First electrode layer 112, first medium layer 111, the second electrode lay 113, second dielectric layer 114, the 3rd electrode layer
115th, the 3rd dielectric layer 116 and the 4th electrode layer 117 stack gradually the ceramic body 110 to form cuboid.Preferably, ceramic body
110 big more than the 0.2mm of length: width and thickness.Side where first side, the 3rd side, the 5th side and heptalateral side
Face is the first side of ceramic body 110, and the side where second side, four side, the 6th side and the 8th side is ceramics
The second side of body 110.
In the illustrated embodiment, the thickness of first medium layer 111 and second dielectric layer 114 is identical, certainly, at other
In implementation method, the thickness of second dielectric layer 114 can also be different from first medium layer 111.The thickness pair of second dielectric layer 114
The capacitance of the compound component 100 of chip does not produce influence, therefore can go adjustment by adjusting the thickness of second dielectric layer 114
The thickness of the compound component 100 of chip.When requiring that the compound component 100 of chip has larger capacitance, the can be reduced
The thickness of one dielectric layer 111, while increase the thickness of second dielectric layer 114, to ensure that it is enough that the compound component 100 of chip has
Thickness avoid fracture；When requiring that the compound component 100 of chip has less capacitance, first medium layer can be increased
111 thickness, while reducing the thickness of second dielectric layer 114.
Lateral electrode 130 is attached to the side of ceramic body 110.In the illustrated embodiment, lateral electrode 130 is attached to ceramics
The second side of body 110, and second side is completely covered, so that lateral electrode 130 and the electrode layer of the second electrode lay 113 and the 3rd
115 electrical connections.Further, lateral electrode 130 extends to four surfaces abutted with second side, side electricity from second side bending
The distance of the edge of pole 130 and the four edges of second side is 0.1mm~0.4mm, and lateral electrode 130 and first electrode layer 112
And the 4th be formed with gap between electrode layer 117.
Resistance 150 is completely covered the surface of lateral electrode 130, and extends to the 4th electrode layer 117 and cover the 4th electrode layer
117 near one end of the 8th side, so as to be electrically connected with the 4th electrode layer 117, and between resistance 150 and first electrode layer 112
It is formed with gap and insulate.
Certainly, in other implementations, lateral electrode 130 also can adhere to first side, and now resistance 150 covers completely
The surface of lid lateral electrode 130, and extend to first electrode layer 112 and cover the one end of first electrode layer 112 near first side,
And electrically connected with first electrode layer 112, it is formed with gap between the 4th electrode layer 117 and insulate.
Due to the width of the width less than third space in the first gap, so that when lateral electrode 130 is attached to first side,
Resistance 150 can easily be prepared by infusion process, same immersion depth can ensure that resistance 150 covers first electrode layer
112 one end and it is formed with gap between the 4th electrode layer 117；Likewise, because the width in the second gap is more than between the 4th
The width of gap, when lateral electrode 130 is attached to second side, resistance 150, same leaching can be easily prepared by infusion process
Entering depth can ensure that resistance 150 covers one end of the 4th electrode layer 117 and is formed with gap between first electrode layer 112.
In the illustrated embodiment, the facing area of first electrode layer 112 and the second electrode lay 113 and the 3rd electrode layer
115 is identical with the facing area of the 4th electrode layer 117, the thickness and the thickness phase of the 3rd dielectric layer 116 of first medium layer 111
Together, the width in the first gap is equal with the width in the 4th gap, and the width in the second gap is equal with the width of third space, and second
The length of the electrode layer 115 of electrode layer 113 and the 3rd with the equal length on the surface 1141 of second surface 1112 and the 3rd, and second
Orthographic projection of the electrode layer 113 on the 3rd surface 1141 is completely overlapped with the 3rd electrode layer 115.So as to the structure tool of ceramic body 110
Have symmetry, no matter therefore which in first side and second side lateral electrode 130 and resistance 150 are attached to, chip is multiple
The resistance value and capacitance for closing component 100 will not produce difference.
Above-mentioned chip is combined component 100, is formed with outside line by the electrode layer 117 of first electrode layer 112 and the 4th
Electrical connection, when lateral electrode 130 and resistance 150 are attached to the second side of ceramic body 110, first electrode layer 112, first medium
Layer 111 and the second electrode lay 113 form electric capacity, part resistance and electricity between the 4th electrode layer 117 and lateral electrode 130
Appearance is composed in series cascaded structure, so as to resistance and electric capacity are integrated into discrete component, structure is more compact；Lateral electrode is set
130, the part resistance between the 4th electrode layer 117 and lateral electrode 130 is not required to the edges and corners by ceramic body 110 (by ceramics
One end of body 110 directly prepares resistance 150 using infusion process, and the edges and corners slurry thickness of ceramic body 110 is smaller, can answer chip
The resistance accuracy for closing component 100 deteriorates), the resistance accuracy of the compound component 100 of chip, and lateral electrode 130 can be improved
Covered by resistance 150, lateral electrode 130 and resistance 150 electrically connect more reliable.By adjusting the electricity of first electrode layer 112 and second
The dielectric constant of the facing area, the thickness of first medium layer 111 and first medium layer 111 of pole layer 113 can be obtained easily
Different capacitances are obtained, by the resistivity and the electrode layer 117 of first electrode layer 112 or the 4th and side electricity that adjust resistance 150
The gap of pole 130 can easily obtain different resistance values, by adjusting first medium layer 111 and second dielectric layer 114
Thickness can be conveniently adjusted the thickness of the compound component 100 of chip, with strong applicability；In the preparation, it is thus only necessary to by side electricity
Pole 130 is attached to any one in two sides of ceramic body 110, without identification, Simplified flowsheet；In the preparation, by
In the width of the width more than the first gap of third space, the width of the width less than the second gap in the 4th gap, by ceramic body
110 one end prepares resistance 150 using infusion process, by adjusting the depth of immersion, can make resistance 150 and first electrode layer 112
And the 4th electrical connection in electrode layer 117.
The preparation method of the compound component of above-mentioned chip, comprises the following steps：
Step S210, prepare starch film.
In the present embodiment, starch, first adhesive and the first solvent are well mixed and obtain starch size, with starch
Slurry prepares starch film for raw material.
Preferably, starch, first adhesive and the first solvent are well mixed by the way of ball milling and obtain starch size.
Further, the time of ball milling is 3 hours~4 hours.
Preferably, the mass ratio of starch, first adhesive and the first solvent is 10：2.5~3：10~15.
Preferably, starch is cornstarch.
Preferably, first adhesive is selected from least one in acrylic resin and polyvinyl butyral resin.
Preferably, the first solvent is that mass ratio is 1：1~1.25：1 toluene and the mixed solvent of absolute ethyl alcohol.
Preferably, starch size also includes plasticizer, and in one embodiment, plasticizer is dioctyl phthalate
(DOP).Further, plasticizer and the mass ratio of starch are 1：20~1：10.
Preferably, starch size is cast to form starch film using the tape casting.
Preferably, the thickness of starch film is 90 μm~130 μm.
Step S220, prepare ceramic membrane.
In the present embodiment, ceramic size is obtained after ceramic powder, second adhesive, the second solvent being well mixed, with
Ceramic size prepares ceramic membrane for raw material.
Preferably, ceramic powder, second adhesive, the second solvent are well mixed by the way of ball milling and obtain ceramic slurry
Material.Further, the time of ball milling is 12 hours~16 hours.
Preferably, ceramic powder, second adhesive, the mass ratio of the second solvent are 10：3~5：4~6.
Preferably, ceramic powder is barium titanate ceramic powder, and certainly, other ceramic powders commonly used in the trade can also.Barium titanate is made pottery
Porcelain powder has dielectric constant higher so that the capacitance swing of the compound component of the chip of preparation is wider.
Preferably, second adhesive is polyvinyl butyral resin, and the second solvent is that mass ratio is 1:1~1.5:1 toluene
With the mixed solvent of absolute ethyl alcohol.
Preferably, ceramic size is cast to form ceramic membrane using the tape casting.
Preferably, the thickness of ceramic membrane is 20 μm~60 μm.
Step S230, multiple ceramic membranes are laminated in substrate surface, are secured to the protective layer on substrate.
Preferably, substrate is stainless steel plate, and certainly, other intensity and toughness suitable material can serve as the material of substrate
Material.
Preferably, the thickness of protective layer is 0.2mm~0.3mm.
Step S240, at least one starch film is laminated on the protection layer.
Step S250, the surface preparation first electrode layer in starch film.
In present embodiment, first electrode layer is prepared on starch film surface by the way of silk-screen printing.Further, adopt
With silk screen in starch film print electrode on surface slurry, the first electrode layer being layered on starch film is obtained after drying.
The material of first electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, substrate is positioned using the method for three-point fix when starch film surface prepares first electrode layer.
Preferably, the thickness of first electrode layer is 1 μm~3 μm.
Step S260, a few ceramic membrane is laminated on first electrode layer surface, obtains being layered in first electrode layer surface
First medium layer.
In this step, the design thickness according to first medium layer determines the quantity of ceramic membrane, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of first medium layer is 25 μm~200 μm.
Step S270, first medium layer surface prepare the second electrode lay.
In present embodiment, the second electrode lay is prepared in first medium layer surface by the way of silk-screen printing.Further
, printed electrode slurry in first medium layer surface using silk screen, the second electricity being layered on first medium layer is obtained after drying
Pole layer.
The material of the second electrode lay can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the second electrode lay is 1 μm~3 μm.
Step S280, a few ceramic membrane is laminated on the surface of the second electrode lay, obtains being layered in the second electrode lay table
The second dielectric layer in face.
In this step, the design thickness according to second dielectric layer determines the quantity of ceramic membrane, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of second dielectric layer is 20 μm~350 μm.
Step S290, the 3rd electrode layer of surface preparation in second dielectric layer.
In present embodiment, the 3rd electrode layer is prepared in second medium layer surface by the way of silk-screen printing.Further
, using silk screen in second dielectric layer print electrode on surface slurry, the 3rd electricity being layered in second dielectric layer is obtained after drying
Pole layer.The silk screen used in the silk screen and step S270 that are used in the step can be the same or different, when in two steps
When the silk screen for using is identical, without re-registrating again in the step.
The material of the 3rd electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the 3rd electrode layer is 1 μm~3 μm.
Step S300, the 3rd electrode layer surface be laminated at least one ceramic membrane, obtain being layered in the 3rd electrode layer surface
The 3rd dielectric layer.
In this step, the design thickness according to the 3rd dielectric layer determines the quantity of ceramic membrane, such that it is able to needed for reaching
The thickness wanted.
Preferably, the thickness of the 3rd dielectric layer is 25 μm~200 μm.
Step S310, the 4th electrode layer of surface preparation in the 3rd dielectric layer.
In present embodiment, the 4th electrode layer is prepared in the 3rd dielectric layer surface by the way of silk-screen printing.Further
, printed electrode slurry in the 3rd dielectric layer surface using silk screen, the 4th electricity being layered on the 3rd dielectric layer is obtained after drying
Pole layer.
The material of the 4th electrode layer can be silver, palladium or silver palladium alloy.Further, palladium and silver-colored quality in palladium-silver
Than there is no particular restriction.
Preferably, electrode slurry can be silver paste, palladium slurry or silver palladium alloy slurry.
Preferably, the thickness of the 4th electrode layer is 1 μm~3 μm.
Step S320, multilayer board press to obtain layered product.
In the present embodiment, pressing makes in multilayer board each film layer tight bond to avoid using isostatic pressing method pressing
Layering.
In the present embodiment, cut according to required size after multilayer board is pressed, afterwards with substrate point
From obtaining layered product.Being separated with substrate can be shoveled layered product using blade, and in this step, protective layer can guarantee that first
Electrode layer is not scratched in operating herein by blade.
Step S330, carry out that row is viscous and sintering obtains ceramic body to layered product.
Wherein in one embodiment, the viscous concrete operations of row are：Layered product is heated to 350 DEG C~450 DEG C and insulation 1
~3 hours.Further, arrange to glue is carried out in air atmosphere.
One embodiment wherein, the concrete operations of sintering are：The layered product that will be arranged after gluing is heated to 900 DEG C~1320 DEG C
And insulation is sintered for 2 hours~3 hours.Further, sintering is carried out in air atmosphere.
In the step, during sintering, starch film ashing so that protective layer departs from.
The ceramic body obtained after sintering includes the first electrode layer, first medium layer, the second electrode lay, second that stack gradually
Dielectric layer, the 3rd electrode layer, the 3rd dielectric layer and the 4th electrode layer.
Step S340, the side formation lateral electrode in ceramic body.
In the illustrated embodiment, by way of dipping, first side is immersed in silver paste, side is formed after drying
Electrode.
Immersion depth is controlled during dipping, it is to avoid lateral electrode 130 covers the electrode layer 117 of first electrode layer 112 and the 4th.
Certainly, in other embodiments, second side can be also immersed in silver paste.
Step S350, prepare resistance on the surface of lateral electrode and obtain the compound component of chip.
In the illustrated embodiment, by way of dipping, lateral electrode is immersed in resistance slurry, electricity is formed after drying
Resistance.
Immersion depth is controlled during dipping so that in the covering electrode layer 117 of first electrode layer 112 and the 4th of resistance 150 one
Individual one end, it is to avoid resistance 150 covers the electrode layer 117 of first electrode layer 112 and the 4th simultaneously.
Preferably, ceramic body is fixed using suitable fixture such as end-blocking plate, by resistance slurry by way of dipping
Four sides of lateral electrode and ceramic body and first side adjoining are sticked to, sintering obtains resistance after drying.Further, sinter
Temperature be 840 DEG C~850 DEG C.Further, resistance slurry is ruthenium system resistance slurry.Further, it is sintered in air atmosphere
Under carry out.Further, the temperature of drying is 140 DEG C~150 DEG C.
The length of ceramic body 110 0.2mm more than bigger than the thickness of width and ceramic body 110 of ceramic body 110, Ke Yibao
Card being properly positioned in fixture of ceramic body 110, that is, ensure that resistance slurry will not by mistake be adhered to the other surfaces of ceramic body 110
On.
The preparation method of the compound component of above-mentioned chip, process is simple.
It should be noted that the order of step S210 and step S220 can be exchanged, it is also possible to synchronous to perform, certainly,
In other embodiment, starch film and ceramic membrane can also outsourcing, then step S210 and step S220 can be omitted.Step S230
Can omit, layered product is separated from substrate using other modes now.Step S240 can be omitted, now by other
Technique directly prepares first electrode layer on starch film.
Refer to Fig. 4, Fig. 5 and Fig. 6, structure and the compound unit of chip of the compound component 500 of chip of another implementation method
The structure of device 100 is roughly the same, and its difference is：The compound component 500 of chip includes two lateral electrodes：First lateral electrode
534 and second lateral electrode 538；Including two resistance：First resistor 554 and second resistance 558；The second electrode lay 513 and second
3rd side on surface 5112 is at least partly concordantly formed and draws side, and width is formed between the second electrode lay 513 and four side
Gap more than 0.2mm；3rd electrode layer 515 draws side with the 6th side at least partly concordant formation on the 3rd surface 5141,
Gap of the width more than 0.2mm is formed between 3rd electrode layer 515 and the 5th side.
First lateral electrode 534 be attached to first side where first side, the first lateral electrode 534 extends to and the first side
Face adjoining other four sides and form gap, the first lateral electrode between the electrode layer 517 of first electrode layer 512 and the 4th
534 electrically connect with the second electrode lay 513.First resistor 554 covers the surface of the first lateral electrode 534 and extends to and first side
Other adjacent four sides, first resistor 554 extend to first electrode layer 512 near one end of first side and with the 4th electricity
Pole layer 517 forms gap near the one end on heptalateral side.
Second lateral electrode 538 be attached to second side where second side, the second lateral electrode 538 extends to and the second side
Face adjoining other four sides and form gap, the second lateral electrode between the electrode layer 517 of first electrode layer 512 and the 4th
538 electrically connect with the 3rd electrode layer 515.Second resistance 558 covers the surface of the second lateral electrode 538 and extends to and second side
Other adjacent four sides, second resistance 558 extend to the 4th electrode layer 517 near one end of the 8th side and with the first electricity
Pole layer 512 forms gap near one end of second side.
It should be noted that in other embodiments, first surface, second surface 5112, the 3rd surface 5141 and
Four surfaces 5161 or square.
Above-mentioned chip is combined component 500, is formed with outside line by the electrode layer 517 of first electrode layer 512 and the 4th
Electrical connection.The second electrode lay 513, the 3rd electrode layer 515 and second dielectric layer 514 form electric capacity, positioned at first electrode layer 512 and
Part first resistor 554 between first lateral electrode 534, that between the 4th electrode layer 517 and the second lateral electrode 538
The cascaded structure of resistance-capacitance-resistance is formed between part second resistance 558 and electric capacity.
Refer to Fig. 7, Fig. 8 and Fig. 9, structure and the compound unit of chip of the compound component 700 of chip of another implementation method
The structure of device 100 is roughly the same, and its difference is：First surface, second surface 7112, the 3rd surface 7141 and the 4th surface
7161 are square, and the second electrode lay 713 is completely covered second surface 7112, and the 3rd electrode layer 715 is completely covered the 3rd table
Gap, the 4th electrode layer 717 and the 4th are each formed between four sides of face 7141, first electrode layer 712 and first surface
Gap is each formed between four sides on surface 7161.
Further, in the illustrated embodiment, first surface has first side and intersect with first side
Dual side-edge, the 4th surface 7161 has the 8th side that heptalateral intersects while heptalateral.First side and second side
Orthographic projection and heptalateral side and the 8th side composition square on the 4th surface 7161.First electrode layer 712 and first side
And the two other that width is the gap of 0.2mm~0.5mm, first electrode layer 712 and first surface is formed between second side
Gap-ratio first electrode layer 712 between side and the big 0.2mm~0.5mm in the gap between first side and second side.The
The gap that width is 0.2mm~0.5mm, the 4th electrode layer are formed between four electrode layers 717 and heptalateral side and the 8th side
717 and the 4th surface 7161 two other side between the electrode layer 717 of gap-ratio the 4th and heptalateral side and the 8th side
Between the big 0.2mm~0.5mm in gap.
Lateral electrode 730 be attached to one of side of ceramic body 710 and extend to the flank abutment other four
Individual side and gap is formed between the electrode layer 717 of first electrode layer 712 and the 4th, resistance 750 covers the surface of lateral electrode 730
And extend to four sides adjacent with the side where lateral electrode 730.Resistance 750 cover the 4th electrode layer 717 one end from
And electrically connected with the 4th electrode layer 717, between resistance 750 and first electrode layer 712 formed gap so as to first electrode layer 712
Insulation.
In the illustrated embodiment, length (or width) 0.2mm bigger than the thickness of ceramic body 710 of ceramic body 710 with
On.
The structure of the compound component 700 of above-mentioned chip has symmetry, so as to lateral electrode 730 and resistance 750 are attached to
On any one side of ceramic body 710 can, and the resistance value and capacitance of chip compound component 700 will not be caused
Difference, simplifies preparation technology.
Embodiment described above only expresses several embodiments of the present utility model, and its description is more specific and detailed,
But therefore can not be interpreted as the limitation to the utility model the scope of the claims.It should be pointed out that common for this area
For technical staff, without departing from the concept of the premise utility, various modifications and improvements can be made, these all belong to
In protection domain of the present utility model.Therefore, the protection domain of the utility model patent should be determined by the appended claims.
Claims (9)
1. a kind of chip is combined component, it is characterised in that including：
Ceramic body, the ceramic body includes：
First medium layer, the first medium layer has relative first surface and second surface, and the first surface has phase
To first side and second side, the second surface has relative the 3rd side and four side；
First electrode layer, is formed at the first surface of first medium layer, the first electrode layer and the first side it
Between be formed with the first gap, the second gap is formed between the first electrode layer and the second side；
The second electrode lay, is formed at the second surface of first medium layer, the second electrode lay and the 3rd side and
At least one of described four side at least partly concordant formation draws side；
Second dielectric layer, is laminated in the surface of the second electrode lay and the second surface is completely covered, the second medium
Layer has the 3rd surface, and the 3rd surface is a side surface of the second dielectric layer away from first medium layer, described
3rd surface has relative the 5th side and the 6th side；
3rd electrode layer, is formed at the 3rd surface, and the 3rd electrode layer and the 5th side and the 6th side
While at least one of at least partly it is concordant formed draw while；
3rd dielectric layer, is laminated in the surface of the 3rd electrode layer and the 3rd surface is completely covered, the 3rd medium
Layer has the 4th surface, and the 4th surface is a side surface of the 3rd dielectric layer away from the second dielectric layer, described
4th surface has a relative heptalateral side and the 8th side, the heptalateral side the first surface orthographic projection with it is described
First side overlaps；
4th electrode layer, is formed at the 4th surface, and the 3rd is formed between the 4th electrode layer and the heptalateral side
Gap, is formed with the 4th gap between the 4th electrode layer and the 8th side, the width of the third space is more than institute
State the width in the first gap, the width of the width less than second gap in the 4th gap；
Lateral electrode, is attached to the side of the ceramic body, and with least one of the second electrode lay and the 3rd electrode layer
Electrical connection；
Resistance, is completely covered the lateral electrode and extends to the first surface and the 4th surface, the resistance and described first
An electrical connection in electrode layer and the 4th electrode layer.
2. chip as claimed in claim 1 is combined component, it is characterised in that the second electrode lay is in the first electrode
The orthographic projection of layer is least partially overlapped with the first electrode layer；Orthographic projection of 3rd electrode layer in the 4th electrode layer
It is least partially overlapped with the 4th electrode layer.
3. chip as claimed in claim 1 is combined component, it is characterised in that the 3rd electrode layer is in the second surface
Orthographic projection overlapped with the second electrode lay.
4. the compound component of chip as claimed in claim 1, it is characterised in that the second electrode lay is from the 3rd side
Extend to the four side；And/or, the 3rd electrode layer extends to the 6th side from the 5th side.
5. chip as claimed in claim 4 is combined component, it is characterised in that the second electrode lay is on the 3rd surface
Orthographic projection it is Chong Die with the 3rd electrode layer.
6. chip as claimed in claim 1 is combined component, it is characterised in that the width of the third space is than the first gap
The big 0.2mm~0.5mm of width；And/or, the width big 0.2mm~0.5mm of the width than the 4th gap in second gap.
7. the compound component of chip as claimed in claim 1, it is characterised in that the second electrode lay is from the 3rd side
Extend to the four side and be formed between the four side gap, the 3rd electrode layer is from the 6th side
Gap, the 3rd side and the 5th side position are formed with to the 5th side extension and between the 5th side
In same one end of the second dielectric layer.
8. the compound component of chip as claimed in claim 7, it is characterised in that the lateral electrode includes the first lateral electrode and the
Two lateral electrodes, the resistance include first resistor and second resistance, the first lateral electrode be attached to the one side of the ceramic body and with
An electrical connection in the second electrode lay and the 3rd electrode layer, second lateral electrode is attached to the another of the ceramic body
Side and electrically connected with another in the second electrode lay and the 3rd electrode layer, the first resistor is completely covered described
One lateral electrode and electrically connected with the first electrode layer and the 4th electrode layer, the second resistance is completely covered
Second lateral electrode and electrically connected with another in the first electrode layer and the 4th electrode layer.
9. chip as claimed in claim 1 is combined component, it is characterised in that the first surface, second surface, the 3rd table
Face and the 4th surface are square, and the second electrode lay is completely covered the second surface, and the 3rd electrode layer is complete
The 3rd surface is covered, gap is each formed between the first electrode layer and four sides of the first surface, it is described
Gap is each formed between four articles of sides on the 4th electrode layer and the 4th surface.
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| CN201621105493.6U CN206210617U (en) | 2016-09-30 | 2016-09-30 | Chip is combined component |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340387A (en) * | 2016-09-30 | 2017-01-18 | 广东风华高新科技股份有限公司 | Chip type composite component and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106340387A (en) * | 2016-09-30 | 2017-01-18 | 广东风华高新科技股份有限公司 | Chip type composite component and preparation method thereof |
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