CN206164483U

CN206164483U - High -speed differential amplification circuit

Info

Publication number: CN206164483U
Application number: CN201621123250.5U
Authority: CN
Inventors: 刘雄
Original assignee: Guangzhou Chang Yuhang Mdt Infotech Ltd
Current assignee: Guangzhou Chang Yuhang Mdt Infotech Ltd
Priority date: 2016-10-14
Filing date: 2016-10-14
Publication date: 2017-05-10
Anticipated expiration: 2026-10-14

Abstract

The utility model discloses a high -speed differential amplification circuit, including a NMOS pipe, the 2nd NMOS pipe, the 3rd NMOS pipe, fourth NMOS pipe, first electric capacity, second electric capacity, first electric current source and second electric current source. The utility model relates to a high -speed differential amplification circuit combines first electric capacity and second electric capacity to realize that the differential signal amplifies through the difference output load of differential input geminate transistors, the 3rd NMOS pipe and the fourth NMOS nest of tubes one -tenth of NMOS pipe and the 2nd NMOS nest of tubes one -tenth, and not only circuit structure is simple, and is enlarged functional in addition, is applicable to the high -speed circuit, and the practicality is strong, and application scope is wide. The utility model relates to a high -speed differential amplification circuit, but wide application in amplifier circuit field.

Description

High Speed Differential Amplifier

Technical field

This utility model is related to amplifying circuit field, especially a kind of High Speed Differential Amplifier.

Background technology

CMOS devices：Refer to using CMOS technology (Complementary Metal Oxide Semiconductor) the plane type field three terminal device that manufactures, can be used to switch or amplify.Including p-type Metal-oxide-semiconductor and N-type metal-oxide-semiconductor, so being referred to as CMOS technology.Also there is single p-type metal-oxide half Semiconductor process and N-type metal oxide semiconductor processing, present is fewer.Generally include grid (Gate), source electrode (Source) and drain electrode (Drain) three ports.Grid typically plays control action.

Amplifying circuit, referring to carries out voltage either electric current or the circuit of power amplification to input signal, and the amplification Gain can be adjusted within the specific limits.The comparison of general chip internal voltage amplification is more, under certain characteristic frequency, the letter of output The ratio of number scope and input signal is referred to as gain.With the increase of input signal, the amplifying power of general amplifier is posted Drop under the influence of raw electric capacity etc..When input signal gain reduction to low-frequency gain 0.707 or reduce 3dB when, the frequency The referred to as bandwidth of the amplifier.Bandwidth is higher, and the frequency range that the amplifier can amplify signal is higher.Difference channel refers to input letter Number it is differential signal, one side signal becomes big, and in addition one side signal diminishes, and vice versa.The output of difference channel can be single-ended It can also be both-end difference.

General adjustable gain section amplifying circuit is as shown in figure 1, a variable resistance Rs is connected on two NMOS tubes M1 and M2 Source electrode in the middle of, play degenerative effect；So that gain can be approximately the ratio of the resistance between metal-oxide-semiconductor drain electrode and source electrode；This The linearity for planting circuit is relatively good, and gain is the ratio of two resistance, more stable, does not change with process corner, and output loading is determined Determine the bandwidth of the amplifying circuit, therefore the amplifying circuit is not suitable for being applied to high speed circuit, practicality is low, narrow application range.

The content of the invention

In order to solve above-mentioned technical problem, the purpose of this utility model is to provide a kind of stable high-speed-differential of amplification performance Amplifying circuit.

The technical scheme that this utility model is adopted is：A kind of High Speed Differential Amplifier, including the first NMOS tube, second NMOS tube, the 3rd NMOS tube, the 4th NMOS tube, the first electric capacity, the second electric capacity, the first current source and the second current source, described The first differential input end and the second difference that the grid of one NMOS tube and the second NMOS tube is respectively High Speed Differential Amplifier is defeated Enter end, the source electrode of first NMOS tube, the source electrode of the second NMOS tube are grounded respectively by the first current source, the second current source, The drain electrode of first NMOS tube, the drain electrode of the second NMOS tube source electrode, the source electrode of the 4th NMOS tube respectively with the 3rd NMOS tube Connection, the grid of the 3rd NMOS tube, the grid of the 4th NMOS tube connect power supply by first resistor, second resistance respectively, The drain electrode of the 3rd NMOS tube, the drain electrode of the 4th NMOS tube connect respectively power supply, and first capacitance connection is in the 3rd NMOS Between the grid and source electrode of pipe, second capacitance connection between the grid and source electrode of the 4th NMOS tube, a NMOS The first difference output end and the second difference that the drain electrode of pipe and the drain electrode of the second NMOS tube are respectively High Speed Differential Amplifier is defeated Go out end.

Further, the High Speed Differential Amplifier also includes 3rd resistor, the source electrode of first NMOS tube and the One end connection of three resistance, the other end of the 3rd resistor is connected with the source electrode of the second NMOS tube.

Further, the High Speed Differential Amplifier also includes the 3rd electric capacity, and the 3rd electric capacity is with 3rd resistor simultaneously Connection.

The beneficial effects of the utility model are：This utility model High Speed Differential Amplifier passes through the first NMOS tube and second Difference output load of the Differential Input of NMOS tube composition to pipe, the 3rd NMOS tube and the 4th NMOS tube composition, it is electric with reference to first Hold and the second electric capacity realizes that differential signal amplifies, not only circuit structure is simple, and amplification performance is good, it is adaptable to high speed electricity Road, it is practical, it is applied widely.

Description of the drawings

Specific embodiment of the present utility model is described further below in conjunction with the accompanying drawings：

Fig. 1 is the circuit diagram of prior art；

Fig. 2 is the circuit diagram of this utility model High Speed Differential Amplifier embodiment one；

Fig. 3 is circuit diagram when this utility model High Speed Differential Amplifier is actually used；

Fig. 4 is the circuit diagram of this utility model High Speed Differential Amplifier embodiment two；

Fig. 5 is the circuit diagram of this utility model High Speed Differential Amplifier embodiment three.

Specific embodiment

It should be noted that in the case where not conflicting, the feature in embodiment and embodiment in the application can phase Mutually combination.

Embodiment one

A kind of High Speed Differential Amplifier, with reference to Fig. 2, Fig. 2 is that a kind of High Speed Differential Amplifier of this utility model is implemented The circuit diagram of example one, specifically, High Speed Differential Amplifier includes the first NMOS tube M1, the second NMOS tube M2, the 3rd NMOS tube M3, the 4th NMOS tube M4, the first electric capacity C1, the second electric capacity C2, the first current source IW1 and the second current source IW2, the first NMOS tube The grid of M1 and the second NMOS tube M2 is respectively the first differential input end INP and the second Differential Input of High Speed Differential Amplifier End INN, the source electrode of the first NMOS tube M1, the source electrode of the second NMOS tube M2 pass through respectively the first current source IW1, the second current source IW2 is grounded, the drain electrode of the first NMOS tube M1, the drain electrode source electrode respectively with the 3rd NMOS tube M3 of the second NMOS tube M2, the 4th The source electrode connection of NMOS tube M4, the grid of the 3rd NMOS tube M3, the 4th NMOS tube M4 grid respectively by first resistor R1, the Two resistance R2 connect power supply VAA, and the drain electrode of the 3rd NMOS tube M3, the drain electrode of the 4th NMOS tube M4 connect respectively power supply VAA, and first Electric capacity C1 is connected between the grid of the 3rd NMOS tube M3 and source electrode, the second electric capacity C2 be connected to the 4th NMOS tube M4 grid and Between source electrode, the drain electrode of the first NMOS tube M1 is poor with the first of the drain electrode of the second NMOS tube M2 respectively High Speed Differential Amplifier Divide outfan OUTN and the second difference output end OUTP.

First NMOS tube M1 and the second NMOS tube M2 are Differential Inputs to pipe, and it is poor that the differential voltage signal of input is converted into Divide electric current, the 3rd NMOS tube M3 and the 4th NMOS tube M4 are difference output loads, and current signal is converted into into voltage signal.This reality It is not only simple in structure with new High Speed Differential Amplifier, cost of implementation is low, and suitable for high speed circuit, specifically, such as Lower explanation：

With reference to Fig. 3, Fig. 3 is circuit diagram when a kind of High Speed Differential Amplifier of this utility model is actually used, high speed difference When dividing amplifying circuit connection load, as shown in figure 3, load capacitance Cload1 and Cload2 are connected to the first difference output end Between OUTN and ground, between the second difference output end OUTP and ground.When low frequency, the impedance of the first electric capacity C1 is very big, the The voltage of three NMOS tubes M3 is connected on power supply VAA by first resistor R1, therefore the 3rd NMOS tube M3 forms a diode connection Metal-oxide-semiconductor, the voltage of its grid and drain electrode by the 3rd NMOS tube M3 pipe sizing and flow through its electric current and determine.Due to the 3rd The direct grid current voltage of NMOS tube M3 is supply voltage, therefore the drain electrode DC voltage or the direct current of output of the 3rd NMOS tube M3 Voltage is automatically determined, therefore the output of High Speed Differential Amplifier does not need extra common mode feedback circuit to provide stable common mode Voltage, circuit structure is simple and cost is relatively low.Low-frequency gain is gm1/gm3, wherein, gm1, gm3 are respectively the first NMOS tube M1 With the mutual conductance of the 3rd NMOS tube M3.When high frequency, the impedance of the first electric capacity C1 diminishes, and it feeds back a part of output signal To the grid of the 3rd NMOS tube M3, it is ensured that ensure certain fixed pressure drop between the grid and source electrode of the 3rd NMOS tube M3 so that The output current kept stable of the 3rd NMOS tube M3, the signal code of the first NMOS tube M1 is most of to flow into load, so as to Signal gain when high frequency is ensure that, high-frequency gain is gm1/Cload1, wherein, gm1 is the mutual conductance of the first NMOS tube M1, Cload1 is the capacitance of load capacitance Cload1, therefore, differential amplifier circuit of the present utility model can apply to electricity at a high speed Road, not only amplification performance is stablized, and practicality is good.

Embodiment two

Used as the further improvement of the technical scheme of embodiment one, with reference to Fig. 4, Fig. 4 is this utility model one to embodiment two The circuit diagram of High Speed Differential Amplifier embodiment two is planted, High Speed Differential Amplifier also includes 3rd resistor R3, a NMOS The source electrode of pipe M1 is connected with one end of 3rd resistor R3, and the other end of 3rd resistor R3 is connected with the source electrode of the second NMOS tube M2. Input signal becomes comparison linearly after the negative feedback of 3rd resistor R3, flows from the first NMOS tube M1 and the second NMOS tube M2 The signal code for going out is mainly the electric current after negative-feedback process, in the first NMOS tube M1 and the second NMOS tube M2 bias current In the case of big, signal code is substantially equal to resistance value of the input voltage divided by 3rd resistor R3.It is identical with embodiment one, at a high speed During differential amplifier circuit connection load, as shown in figure 3, load capacitance Cload1 and Cload2 are connected to the first difference output Between end OUTN and ground, between the second difference output end OUTP and ground.

Embodiment three

Used as the further improvement of the technical scheme of embodiment two, with reference to Fig. 5, Fig. 5 is this utility model one to embodiment three The circuit diagram of High Speed Differential Amplifier embodiment three is planted, High Speed Differential Amplifier also includes the 3rd electric capacity C3, the 3rd electric capacity C3 is in parallel with 3rd resistor R3.Input signal becomes to compare after the negative feedback of 3rd resistor R3 the 3rd electric capacity C3 of parallel connection Linearly, the signal code for flowing out from the first NMOS tube M1 and the second NMOS tube M2 is mainly the electric current after negative-feedback process, In the case where the first NMOS tube M1 and the second NMOS tube M2 bias current are big, signal code is substantially equal to input voltage divided by Resistance value after three resistance R3 the 3rd electric capacity C3 of parallel connection.So negative feedback dies down when high frequency, and signal gain becomes big, beneficial Gain when promotion signal is in high frequency.It is identical with embodiment one, during High Speed Differential Amplifier connection load, such as Fig. 3 institutes Show, load capacitance Cload1 and Cload2 are connected between the first difference output end OUTN and ground, the second difference output end Between OUTP and ground.

The difference that a kind of High Speed Differential Amplifier of this utility model is consisted of the first NMOS tube M1 and the second NMOS tube M2 Divide difference output load of the input to pipe, the 3rd NMOS tube M3 and the 4th NMOS tube M4 composition, with reference to the first electric capacity C1 and second Electric capacity C2 realizes that differential signal amplifies, and not only circuit structure is simple, and amplification performance is good, it is adaptable to high speed circuit, practical Property it is strong, it is applied widely.

It is more than that preferable enforcement of the present utility model is illustrated, but this utility model is created and is not limited to institute Embodiment is stated, those of ordinary skill in the art can also make a variety of equivalents on the premise of without prejudice to this utility model spirit Deformation is replaced, and the deformation or replacement of these equivalents are all contained in the application claim limited range.

Claims

1. a kind of High Speed Differential Amplifier, it is characterised in that including the first NMOS tube, the second NMOS tube, the 3rd NMOS tube, Four NMOS tubes, the first electric capacity, the second electric capacity, the first current source and the second current source, first NMOS tube and the second NMOS tube Grid be respectively first differential input end and the second differential input end of High Speed Differential Amplifier, first NMOS tube Source electrode, the source electrode of the second NMOS tube are grounded respectively by the first current source, the second current source, the drain electrode of first NMOS tube, The source electrode for draining respectively with the 3rd NMOS tube of the second NMOS tube, the source electrode of the 4th NMOS tube are connected, the 3rd NMOS tube Grid, the 4th NMOS tube grid respectively by first resistor, second resistance connect power supply, the drain electrode of the 3rd NMOS tube, The drain electrode of the 4th NMOS tube connects respectively power supply, first capacitance connection between the grid and source electrode of the 3rd NMOS tube, institute The second capacitance connection is stated between the grid and source electrode of the 4th NMOS tube, the drain electrode of first NMOS tube and the second NMOS tube Drain electrode is respectively first difference output end and the second difference output end of High Speed Differential Amplifier.

2. High Speed Differential Amplifier according to claim 1, it is characterised in that also including 3rd resistor, described first The source electrode of NMOS tube is connected with one end of 3rd resistor, and the other end of the 3rd resistor is connected with the source electrode of the second NMOS tube.

3. High Speed Differential Amplifier according to claim 2, it is characterised in that also including the 3rd electric capacity, the described 3rd Electric capacity is in parallel with 3rd resistor.