CN206099773U - Three sectional drive ware and drive circuit - Google Patents
Three sectional drive ware and drive circuit Download PDFInfo
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- CN206099773U CN206099773U CN201621087815.9U CN201621087815U CN206099773U CN 206099773 U CN206099773 U CN 206099773U CN 201621087815 U CN201621087815 U CN 201621087815U CN 206099773 U CN206099773 U CN 206099773U
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- segment drivers
- phase inverter
- outfan
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- mos pipe
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Abstract
The utility model relates to an electronic circuit technique field discloses a three sectional drive ware and drive circuit. The utility model discloses well drive circuit includes: non - overlap unit is used for producing the blind spot, the one or three sectional drive ware is used for driving the high -voltage switch pipe, the two or three sectional drive ware is used for driving high -pressure afterflow pipe, between the cut in voltage VTH that the mains voltage of the one or three sectional drive ware managed to high -voltage switch, adopt to drive by force drive high -voltage switch pipe from linear zone on -state entering saturation region on -state, at VTH to inferior threshold voltage VTH between, adopt weak drive, slow down the slewing rate of high -voltage switch pipe intermediate -current, at VTH to adopting strong drive high -voltage switch pipe to end totally between the minimum current potential of the one or three sectional drive ware, the working method of the two or three sectional drive ware and the one or three sectional drive ware is similar. Can improve the switching speed and reduce the blind spot time when take into account overvoltage and EMC index like this, showing the efficiency that promotes switching power supply.
Description
Technical field
This utility model is related to electronic circuit technology field, more particularly to a kind of three segment drivers and drive circuit.
Background technology
Increase with the function of electronic product and the higher pursuit to performance, the power of power supply are increasing, work
Voltage range is more and more wider, forms higher challenge to the endurance of power supply and encapsulation, therefore to the conversion efficiency of power supply just
There is higher requirement, and affect conduction impedance of the factor of power-efficient except switching tube and continued flow tube, the DCR (direct currents of inductance
Resistance) and electric capacity ESR (equivalent series resistance) outward, the factor such as switching speed, Dead Time is also very crucial, and these mainly take
Certainly in the design of drive circuit.Existing driving (DRIVER) circuit adopts strong pipe to drive to improve the switch speed of switch, subtracts
Little Dead Time, but the switch speed for switching is too fast, it is meant that and the current change rate flow through in wiring parasitic inductance increases, both
The problem in terms of electromagnetic compatibility (EMC) using in is brought, while power tube drain-source end there is also serious overvoltage phenomenon,
There is the breakdown risk of power tube, the particularly occasion of high current application.
By taking buck DC-DC (BUCK) power supply as an example, a kind of typical high pressure DC-DC voltage dropping power supplies structure such as Fig. 1, MH are height
Compress switch pipe (specially HVNMOS), and ML is high pressure continued flow tube (specially HVNMOS), injectron and high pressure continued flow tube
Cut-in voltage is VTH, the CH and CL respectively parasitic gate-drain capacitances of MH and ML, LH and LL are respectively the parasitism electricity of MH and ML leads
Sense, MH pipes drive end are HDRV, and ML pipes drive end is LDRV, and SW is switching signal, and VDD is stabilized power source, and output voltage values are
Vdd, VIN are external power source, and PWM is pulse width modulating signal, and D is diode, and DRIVE is driver, and BOOT is from lifting
Voltage source, VOUTFor switched power output.For the power supply of ML tube drive circuits only needs to internal low-voltage LDO power vds D i.e.
Can, and for MH is managed, in order to reduce linear zone conduction impedance when MH pipes are turned on, MH pipes gate source voltage difference in conducting is needed all the time
Be maintained at steady state value, be typically also set at Vdd, as MH pipe sources are connected with SW ends, and switching signal be 0 with VIN it
Between convert, this is accomplished by the grid to MH pipes increases bootstrap circuit boost (Bootstrap Circuit), and this circuit is by periphery
Bootstrap capacitor CBOOT, isolation charging diode D and power vd D constitute.
One more universal high-voltage driving circuit structure as shown in Fig. 2 PWM for input pulse-width signal, by anti-
Phase device I28, phase inverter I29, MPB (P-channel metal-oxide-semiconductor B), the switch of MNB (N-channel MOS pipe B) control ML pipes, by NAND gate
I24, L-HLSHIFT3 (the 3rd low-high level translator), phase inverter I25, I26, MPA, MNA control the switch of MH pipes, anti-phase
Device I27, H-LLSHIFT3 (the three-hypers-low transition device), nor gate I28 and phase inverter I30, NAND gate I24 constitute non-friendship
Folded (non-overlap) structure, produces dead band.
The inverter drive that the switch of MH pipes and ML pipes is made up of MPA, MNA and MPB, MNB, in order to improve the speed of switch
Degree, the method for unique feasible are to increase the driving force of phase inverter, but while also make to increase by the current change rate of power tube
Plus, cause power tube drain-source end to produce very strong overvoltage, when serious, even puncture power tube.Therefore power tube is opened
Close speed to effectively improve.
Utility model content
The purpose of this utility model embodiment is to provide a kind of three segment drivers and drive circuit, can taken into account
While overvoltage and EMC indexs, improve switching speed and reduce Dead Time, be obviously improved the efficiency of Switching Power Supply.
To solve above-mentioned technical problem, embodiment of the present utility model provides a kind of three segment drivers, for driving
The high-voltage MOS pipe of dynamic Switching Power Supply；Three segment drivers include：First P-channel metal-oxide-semiconductor (MP11), the second P-channel MOS
Pipe (MP12), the 3rd P-channel metal-oxide-semiconductor (MP13), the first N-channel MOS pipe (MN11), the second N-channel MOS pipe (MN12), the 3rd N
Channel MOS tube (MN13) and the 4th N-channel MOS pipe (MN14)；
The source electrode of the first P-channel metal-oxide-semiconductor (MP11) is connected to power end, and grid is connected to three segment drivers
The first control end, drain electrode be connected with the source electrode of the second P-channel metal-oxide-semiconductor (MP12), the second P-channel metal-oxide-semiconductor
(MP12) drain electrode is connected to the drive end of three segment drivers, and grid is connected to the second control of three segment drivers
End processed；The source electrode of the 3rd P-channel metal-oxide-semiconductor (MP13) is connected to the power end, and grid is connected to second control end,
Drain electrode is connected to the drive end；
The drain electrode of the second N-channel MOS pipe (MN12) is connected to the drive end, and grid is connected to second control
End, source electrode are connected to the drain electrode of the first N-channel MOS pipe (MN11)；The grid of the first N-channel MOS pipe (MN11) is
3rd control end of three segment drivers, source electrode are connected to the lowest electric potential point of three segment drivers；3rd N
The drain electrode of channel MOS tube (MN13) is connected to the source electrode of the second N-channel MOS pipe (MN12), and grid is that described three segmentations are driven
4th control end of dynamic device, source electrode are connected to the lowest electric potential point；The drain electrode connection of the 4th N-channel MOS pipe (MN14)
In the drive end, grid is connected to second control end, and source electrode is connected to the lowest electric potential point.
It is of the present utility model embodiment further provides a kind of drive circuit, for the injectron of driving switch power supply
(MH) with high pressure continued flow tube (ML), the drive circuit includes：One or three segment drivers (301), the two or three segment drivers
(302) with non-overlapping unit (303)；
Non-overlapping unit (303) and the two or three segment drivers described in one or three segment drivers (301) Jing
(302) connect；The non-overlapping unit (303) is for producing dead band；
One or three segment drivers (301), for driving the injectron (MH)；Wherein, described first
The cut-in voltage V of the supply voltage of three segment drivers (301) to the injectron (MH)THBetween, using strong driving, drive
Move the injectron (MH) saturation region conducting state is entered from linear zone conducting state；In the VTHTo subthreshold voltage
VTH-Between, using weak driving, slow down the rate of change of electric current in the injectron (MH)；Wherein, the VTH-Than the VTH
Value it is little；In the VTH-To between the lowest electric potential of the one or three segment drivers (301), using strong driving, drive described
Injectron (MH) is completely switched off；
Two or three segment drivers (302), for driving the high pressure continued flow tube (ML)；Wherein, described second
The cut-in voltage V of the supply voltage of three segment drivers (302) to the high pressure continued flow tube (ML)THBetween, using strong driving, drive
Move the high pressure continued flow tube (ML) saturation region conducting state is entered from linear zone conducting state；In the VTHTo subthreshold voltage
VTH-Between, using weak driving, slow down the rate of change of electric current in the high pressure continued flow tube (ML)；Wherein, the VTH-Than the VTH
Value it is little；In the VTH-To between the lowest electric potential of the two or three segment drivers (302), using strong driving, drive described
High pressure continued flow tube (ML) is completely switched off.
This utility model embodiment in terms of existing technologies, according to metal-oxide-semiconductor (injectron and high pressure afterflow
Pipe) switching process the characteristics of experience linear zone, saturation region, four operation intervals in sub-threshold region and cut-off region respectively, by metal-oxide-semiconductor
Gate source voltage point three stage control, first, in the cut-in voltage V of supply voltage to metal-oxide-semiconductorTHBetween, using strong driving, drive MOS
Pipe quickly enters saturation region conducting state from linear zone conducting state；In VTHTo subthreshold voltage VTH-Between, using weak driving,
Slow down the rate of change of electric current in metal-oxide-semiconductor；In VTH-To between the lowest electric potential of the driver of metal-oxide-semiconductor, using strong driving, MOS is driven
Pipe is completely switched off；So, while overvoltage and EMC indexs is taken into account can improve switching speed and reduce Dead Time, significantly
The efficiency of lifting switch power supply.
Description of the drawings
Fig. 1 is high pressure DC-DC voltage dropping power supply structural representations of the prior art；
Fig. 2 is high-voltage driving circuit structural representation of the prior art；
Fig. 3 is the driving circuit structure schematic diagram of this utility model first embodiment；
Fig. 4 is the view of each working cycle of the drive circuit in this utility model first embodiment；
Fig. 5 is the main circuit structure schematic diagram of the level translator in this utility model first embodiment；
Fig. 6 is that the high level pulse of the level translator in this utility model first embodiment produces circuit structure and illustrates
Figure；
Fig. 7 is the course of work and each key node voltage wave of the level translator in this utility model first embodiment
Shape figure；
Fig. 8 is the driving circuit structure schematic diagram of this utility model second embodiment.
Specific embodiment
It is to make the purpose of this utility model, technical scheme and advantage clearer, new to this practicality below in conjunction with accompanying drawing
Each embodiment of type is explained in detail.However, it will be understood by those skilled in the art that each in this utility model
In embodiment, in order that reader more fully understands the application and proposes many ins and outs.But, even if there is no these skills
Art details and many variations based on following embodiment and modification, it is also possible to realize the application technical side required for protection
Case.
First embodiment of the present utility model is related to a kind of drive circuit, for the injectron of driving switch power supply
MH and high pressure continued flow tube ML, the drive circuit concrete structure as shown in figure 3, including：One or three segment drivers the 301, the 2nd 3
Segment drivers 302 and non-overlapping unit 303.
One or three segment drivers, 301 Jing non-overlapping unit 303 is connected with the two or three segment drivers 302；Non-overlapping list
Unit 303 is used to produce dead band.
One or three segment drivers 301, for driving injectron MH；Wherein, in the one or three segment drivers 301
The cut-in voltage V of supply voltage to injectron MHTHBetween, using strong driving, drive injectron MH to lead from linear zone
Logical state quickly enters saturation region conducting state；In VTHTo subthreshold voltage VTH-Between, using weak driving, slow down high-voltage switch gear
The rate of change of electric current in pipe MH；Wherein, VTH-Compare VTHValue it is little；In VTH-To the one or three segment drivers 301 lowest electric potential it
Between, using strong driving, drive injectron MH completely switched off.
Two or three segment drivers 302, for driving high pressure continued flow tube ML；Wherein, in the two or three segment drivers 302
The cut-in voltage V of supply voltage to high pressure continued flow tube MLTHBetween, using strong driving, drive high pressure continued flow tube ML to lead from linear zone
Logical state quickly enters saturation region conducting state；In VTHTo subthreshold voltage VTH-Between, using weak driving, slow down high pressure afterflow
The rate of change of electric current in pipe ML；Wherein, VTH-Compare VTHValue it is little；In VTH-To the two or three segment drivers 302 lowest electric potential it
Between, using strong driving, drive high pressure continued flow tube ML completely switched off.
This utility model embodiment in terms of existing technologies, according to metal-oxide-semiconductor (injectron and high pressure afterflow
Pipe) switching process of (injectron with high pressure continued flow tube) experiences linear zone, saturation region, sub-threshold region and cut-off region four respectively
The characteristics of individual operation interval, by metal-oxide-semiconductor gate source voltage point three stage control, first, in the cut-in voltage of supply voltage to metal-oxide-semiconductor
VTHBetween, using strong driving, drive metal-oxide-semiconductor to quickly enter saturation region conducting state from linear zone conducting state；In VTHTo subthreshold
Threshold voltage VTH-Between, using weak driving, slow down the rate of change of electric current in metal-oxide-semiconductor；In VTH-To the minimum electricity of the driver of metal-oxide-semiconductor
Between gesture, using strong driving, drive metal-oxide-semiconductor completely switched off；So, can be while overvoltage and EMC indexs be taken into account, Ke Yiti
High switching speed and reduction Dead Time, are obviously improved the efficiency of Switching Power Supply.
Specifically, the one or three segment drivers (301) include：First P-channel metal-oxide-semiconductor (MP11), the second P-channel MOS
Pipe MP12, the 3rd P-channel metal-oxide-semiconductor MP13, the first N-channel MOS pipe MN11, the second N-channel MOS pipe MN12, the 3rd N-channel MOS
Pipe MN13 and the 4th N-channel MOS pipe MN14.
The source electrode of the first P-channel metal-oxide-semiconductor MP11 is connected to the power end of the one or three segment drivers 301, and grid is connected to
First control end of the one or three segment drivers 301, drain electrode are connected with the source electrode of the second P-channel metal-oxide-semiconductor MP12, the second P-channel
The drain electrode of metal-oxide-semiconductor MP12 is connected to the drive end HDRV of the one or three segment drivers 301, and grid is connected to the one or three drive part by part
Second control end of device 301；The source electrode of the 3rd P-channel metal-oxide-semiconductor MP13 is connected to the power end of the one or three segment drivers 301,
Grid is connected to the second control end of the one or three segment drivers 301, and drain electrode is connected to the driving of the one or three segment drivers 301
End HDRV.
The drain electrode of the second N-channel MOS pipe MN12 is connected to the drive end of the one or three segment drivers 301, grid connection
In the second control end of the one or three segment drivers 301, source electrode is connected to the drain electrode of the first N-channel MOS pipe MN11；First N ditches
The grid of road metal-oxide-semiconductor MN11 is the 3rd control end of the one or three segment drivers 301, and source electrode is connected to the one or three segment drivers
301 lowest electric potential point；The drain electrode of the 3rd N-channel MOS pipe MN13 is connected to the source electrode of the second N-channel MOS pipe MN12, and grid is
4th control end of the one or three segment drivers 301, source electrode are connected to the lowest electric potential point of the one or three segment drivers 301；The
The drain electrode of four N-channel MOS pipe MN14 is connected to the drive end HDRV of the one or three segment drivers 301, and grid is connected to the one or three
Second control end of segment drivers 301, source electrode are connected to the lowest electric potential point of the one or three segment drivers 301.Wherein, first
The power supply of three segment drivers 301 is Bootstrap power supply BOOT, and the lowest electric potential point of the one or three segment drivers 301 is switch
The switch terminals of the drive circuit of power supply.
Two or three segment drivers 302 include：4th P-channel metal-oxide-semiconductor MP14, the 5th P-channel metal-oxide-semiconductor MP15, the 6th P ditches
Road metal-oxide-semiconductor MP16, the 5th N-channel MOS pipe MN17, the 6th N-channel MOS pipe MN18, the 7th N-channel MOS pipe MN19 and the 8th N ditches
Road metal-oxide-semiconductor MN20.
The source electrode of the 4th P-channel metal-oxide-semiconductor MP14 is connected to the power end of the two or three segment drivers 302, and grid is connected to
First control end of the two or three segment drivers 302, drain electrode are connected with the source electrode of the 5th P-channel metal-oxide-semiconductor MP15, the 5th P-channel
The drain electrode of metal-oxide-semiconductor MP15 is connected to the drive end LDRV of the two or three segment drivers 302, and grid is connected to the two or three drive part by part
Second control end of device 302；The source electrode of the 6th P-channel metal-oxide-semiconductor MP16 is connected to the power end of the two or three segment drivers 302,
Grid is connected to the second control end of the two or three segment drivers 302, and drain electrode is connected to the driving of the two or three segment drivers 302
End LDRV.
The drain electrode of the 6th N-channel MOS pipe MN18 is connected to the drive end of the two or three segment drivers 302, grid connection
In the second control end of the two or three segment drivers 302, source electrode is connected to the drain electrode of the 5th N-channel MOS pipe MN17；5th N ditches
The grid of road metal-oxide-semiconductor MN17 is the 3rd control end of the two or three segment drivers 302, and source electrode is connected to the two or three segment drivers
302 lowest electric potential point；The drain electrode of the 7th N-channel MOS pipe MN19 is connected to the source electrode of the 6th N-channel MOS pipe MN18, and grid is
4th control end of the two or three segment drivers 302, source electrode are connected to the lowest electric potential point of the two or three segment drivers 302；The
The drain electrode of eight N-channel MOS pipe MN20 is connected to the drive end LDRV of the two or three segment drivers 302, and grid is connected to the two or three
Second control end of segment drivers 302, source electrode are connected to the lowest electric potential point of the two or three segment drivers 302.Wherein, second
The power supply of three segment drivers 302 is constant voltage source VDD, and the lowest electric potential point of the two or three segment drivers 302 is ground terminal.
Non-overlapping unit 303 includes：First phase inverter I9, the second phase inverter I15, the 3rd phase inverter I22, the 4th phase inverter
I23, the 5th phase inverter I5, hex inverter I6, the 7th phase inverter I16, the 8th phase inverter I17, the first low and high level transducer
H-LLSHIFT2, the first nor gate I14, the first NAND gate I4 and the first low high level transducer L-HLSHIFT2.
The input of the first phase inverter I9 is connected to the first control end of the one or three segment drivers 301, outfan connection
In the input of the first low and high level transducer H-LLSHIFT2, the outfan of the first low and high level transducer H-LLSHIFT2 connects
The first input end of the first nor gate I14 is connected to, second input of the first nor gate I14 is connected to the of the first NAND gate I4
One input, the outfan of the first nor gate I14 are connected to the input of the second phase inverter I15, the output of the second phase inverter I15
End is connected to the outfan of the 7th phase inverter I16, and the outfan of the 7th phase inverter I16 is connected to the input of the 8th phase inverter I17
End, the outfan of the 8th phase inverter I17 are connected to the second control end, the two or three segmentation of the two or three segment drivers 302 simultaneously
3rd control end of driver 302.
Second input of the first NAND gate I4 is connected to the outfan of the 4th phase inverter I23, and the 4th phase inverter I23's is defeated
Enter the outfan that end is connected to the 3rd phase inverter I22, the input of the 3rd phase inverter I22 is connected to the two or three segment drivers
302 the 3rd control end.
The outfan of the first NAND gate I4 is connected to the input of the first low high level transducer L-HLSHIFT2, and first is low
The outfan of high level transducer L-HLSHIFT2 is connected to the input of the 5th phase inverter I5, the first low high level transducer L-
The outfan of HLSHIFT2 is also attached to the 3rd control end of the one or three segment drivers 301；The outfan of the 5th phase inverter I5
The input of hex inverter I6 is connected to, the outfan of hex inverter I6 is connected to the of the one or three segment drivers 301
Two control ends.
Drive circuit also includes first comparator 304, the second comparator 305, the first buffer 306, the second buffer
307th, the 3rd buffer 308, the 4th buffer 309 are compared with the second single tube with the 9th phase inverter I3, the first single tube comparator 310
Device 311.
First comparator 304, the first buffer 306, the 9th phase inverter I3 are sequentially connected in series to the one or three segment drivers
301) the first control end；First buffer 306) with the 9th phase inverter I3) connecting node be additionally coupled to the one or three segmentation drive
4th control end of dynamic device 301.
The first input end of the second buffer 307 is connected to the outfan of the first low high level transducer L-HLSHIFT2,
First outfan is connected to the input of the first phase inverter I9, and the second outfan is connected to the of the one or three segment drivers 301
Three control ends, the second input are connected to the first single tube comparator 310；First single tube comparator 310 is connected to the one or three segmentation
Between the lowest electric potential point of the power end of driver 301 and the one or three segment drivers 301, the first single tube comparator 310 also connects
It is connected to the drive end HDRV of the one or three segment drivers 301.
Second comparator 305, the 3rd buffer 308 are sequentially connected in series to the first control end of the two or three segment drivers 302.
The first input end of the 4th buffer 309 is connected to the outfan of the second phase inverter I15, and the first outfan is connected to
The input of the 3rd phase inverter I22, the second outfan of the 4th buffer 309 are connected to the of the two or three segment drivers 302
Three control ends, the second input are connected to the second single tube comparator 311；Second single tube comparator 311 is connected to the two or three segmentation
Between the lowest electric potential point of the power end of driver 302 and the two or three segment drivers 302, the second single tube comparator 311 also connects
It is connected to the drive end LDRV of the two or three segment drivers 302.
First comparator 304, for detecting the signal of SW saltus steps from high to low, judges MH pipes from linear zone to saturation region
Conversion；First buffer 306 is for being transformed into the drive level consistent with HDRV by the output signal of first comparator；First
Single tube comparator 310 is used for the voltage for detecting HDRV, judges conversion of the MH pipes from sub-threshold region to cut-off region；Second buffer
307 are used to transmit the output signal of the first single tube comparator, control the shut-off of MN11 pipes；Second comparator 305 is used to detect SW
The signal of saltus step from low to high, judges conversion of the ML pipes from saturation region to linear zone；Second single tube comparator 311 is used to judge ML
Conversion of the pipe from cut-off region to sub-threshold region；3rd buffer 308 for by the output signal of the second comparator be transformed into
LDRV consistent drive level；4th buffer 309 is used to transmit the output signal of the second single tube comparator, control MN17 pipes
Shut-off.
Specifically, first comparator 304 includes：First resistor R4 and the 7th P-channel metal-oxide-semiconductor MP10.First resistor R4 mono-
End is connected to external power source VIN, and the other end is connected to the source electrode of the 7th P-channel metal-oxide-semiconductor MP10, the 7th P-channel metal-oxide-semiconductor MP10's
Drain electrode is connected to the lowest electric potential point of the one or three segment drivers 301, grid input predeterminated voltage signal VCLAMP；Wherein, preset
Voltage signal VCLAMPThe difference of the voltage signal of voltage signal and stabilized power source VDD equal to external power source VIN.
First buffer 306 includes：Tenth phase inverter I1, the 11st phase inverter I2, the second low and high level transducer H-
LLSHIFT1, the second low high level transducer L-HLSHIFT1, the input of the tenth phase inverter I1 be connected to first resistor R4 with
The connecting node of the 7th P-channel metal-oxide-semiconductor MP10, outfan are connected to the input of the 11st phase inverter I2, the 11st phase inverter
The outfan of I2 is connected to the input of the second low and high level transducer H-LLSHIFT1, the second low and high level transducer H-
The outfan of LLSHIFT1 is connected to the input of the second low high level transducer L-HLSHIFT1, the second low high level transducer
The outfan of L-HLSHIFT1 is connected to the input of the 9th phase inverter I3.
Second buffer 307 includes：Second NAND gate I10, the 12nd phase inverter I7, the 13rd phase inverter I8 and the 14th
Phase inverter I11；The first input end of the second NAND gate I10 is connected to the first input end of the second buffer 307, the second input
The first outfan of the second buffer 307 is connected to, outfan is connected to the input of the 14th phase inverter I11, and the 14th is anti-
The outfan of phase device I11 is connected to the second outfan of the second buffer 307, and the input of the 12nd phase inverter I7 is connected to
Second input of two buffers 307, outfan are connected to the input of the 13rd phase inverter I8, and the 13rd phase inverter I8's is defeated
Go out the first outfan that end is connected to the second buffer 307.
First single tube comparator 310 includes：Second resistance R5 and the 9th N-channel MOS pipe MN15；Second resistance R5 one end connects
The power end of the one or three segment drivers 301 is connected to, the other end is connected to the drain electrode of the 9th N-channel MOS pipe MN15, the 9th N ditches
The source electrode of road metal-oxide-semiconductor MN15 is connected to the lowest electric potential point of the one or three segment drivers 301, and drain electrode is connected to the one or three segmentation and drives
The drive end HDRV of dynamic device 301；The connecting node of second resistance R5 and the 9th N-channel MOS pipe MN15 is connected to the second buffer
307 the second input.
Second comparator 305 includes：Tenth N-channel MOS pipe MN16 and 3rd resistor R6；Tenth N-channel MOS pipe MN16's
Drain electrode is connected to the lowest electric potential point of the one or three segment drivers 301, and source electrode is connected to one end of 3rd resistor R6, grid connection
In stabilized power source VDD；The other end of 3rd resistor R6 is connected to the lowest electric potential point of the two or three segment drivers 302.
3rd buffer 308 includes：15th phase inverter I12 and the tenth hex inverter I13；15th phase inverter I12's
Input is connected to the connecting node of the tenth N-channel MOS pipe MN16 and 3rd resistor R6, and outfan is connected to the tenth hex inverter
The input of I13, the outfan of the tenth hex inverter I13 are connected to the first control end of the two or three segment drivers 302.
4th buffer 309 includes：3rd NAND gate I20, the 17th phase inverter I21, eighteen incompatible medicamentss phase device I18 and the tenth
Nine phase inverter I19；The first input end of the 3rd NAND gate I20 is connected to the first input end of the 4th buffer 309, the second input
End is connected to the first outfan of the 4th buffer 309, and outfan is connected to the input of the 17th phase inverter I21, and the 17th
The outfan of phase inverter I21 is connected to the second outfan of the 4th buffer 309, the input connection of eighteen incompatible medicamentss phase device I18
In the second input of the 4th buffer 309, outfan is connected to the input of the 19th phase inverter I19, the 19th phase inverter
The outfan of I19 is connected to the first outfan of the 4th buffer 309.
Second single tube comparator 311 includes：11st N-channel MOS pipe MN21 and the 4th resistance R7.
4th resistance R7 one end is connected to stabilized power source VDD, and the other end is connected to the leakage of the 11st N-channel MOS pipe MN21
Pole；The source electrode of the 11st N-channel MOS pipe MN21 is connected to the lowest electric potential point of the two or three segment drivers 302, and grid is connected to
The drive end LDRV of the two or three segment drivers 302；The connecting node of the 11st N-channel MOS pipe MN21 and the 4th resistance R7 connects
It is connected to the second input of the 4th buffer 309.
Operationally, R4, MP10 detect the high level voltage of SW, are turned by phase inverter I1, phase inverter I2, height-low level
Parallel operation H-LLSHIFT1, low-high level translator L-HLSHIT1, phase inverter I3 controlling the shut-off of MP11, MN13, with rapid
Power tube is allowed to switch between linear zone and saturation region, wherein, VCLAMP=VIN-Vdd.
R6, MN16 detect the low level voltage of SW, control the shut-off of MP14, MN19 by phase inverter I12, phase inverter I13,
To allow rapidly injectron MH to switch between linear zone and saturation region.The single tube comparator detection HDRV that R5, MN15 are constituted
Voltage, when HDRV-SW voltages reach VTH-When by phase inverter I7, phase inverter I8, NAND gate I10, phase inverter I11 control
The shut-off of MN11, the single tube comparator that R7, MN21 are constituted detect the voltage of LDRV, when LDRV voltages reach VTH-When by anti-phase
Device I18, phase inverter I19, NAND gate I20, phase inverter I21 control the shut-off of MN17.
Each working cycle of the drive circuit is made up of four continuous states, specifically refers to Fig. 4：First state：
As PWM=0, SW=GND=0, for MH pipe drive parts, MP11, MP12, MP13, MN13 cut-off, MN11, MN12 and
MN14 is turned on, HDRV=SW, V1=VBOOT, the cut-off of MH pipes；For ML pipe drive parts, MP14, MP15, MP16, MN19 are turned on,
MN18, MN20, MN17 end, the conducting of LDRV=VDD, V2=GND, ML pipe, and now power-supply system is in freewheeling state.
Second state：When PWM jumps to " 1 " from " 0 ", SW is also in SW=GND states, for ML pipe drive parts
Circuit, MP15, MP16 cut-off, tri- pipe of MN18, MN19, MN20 are simultaneously turned on, and make LDRV voltages from VDD rapid decreases.Work as LDRV
Drop to VTH-When, the cut-off of MN21 pipes, V2 voltages jump to VDD from GND, turn on MN17 by I18, I19, I20, I21,
LDRV hales rapidly GND, the cut-off of ML pipes, but as the afterflow of inductance is acted on, extracts electricity from GND by ML substrate diodes
Stream so that SW drops to below GND.V2 ends MN12, MN14 by I22, I23, I4, L-HLSHIFT2, I5, I6 simultaneously,
MP12, MP13 are turned on, and HDRV voltages rise, when HDRV reaches the cut-in voltage V of power tube MHTHWhen, flow through the electric current in MH pipes
Gradually increase from zero, when SW is gradually transitions VIN from GND, the comparator upset of MP10, R4 composition turns on MP11, HDRV
Driving force strengthen, the rate of climb accelerate, make MH pipes quickly enter fully on state.
The third state：Now, PWM=1, SW=VIN, for ML pipe drive parts, M17, M18, M20 are turned on, MN19,
MP14, MP15, MP16 end, LDRV=GND, V2=VDD；For MH pipe drive parts, MP11, MP12, MP13, MN13 lead
It is logical, MN11, MN12, MN14 cut-off, HDRV=VBOOT, v1=SW.Now Switching Power Supply is in charged state.
4th state：When PWM jumps to " 0 " from " 1 ", SW is in SW=VIN states, for the electricity of MH pipe drive parts
Road, MP12, MP13, MN11 cut-off, tri- pipe of MN12, MN13, MN14 simultaneously turns on, make HDRV-SW voltages from BOOT-SW it is quick under
Drop to the cut-in voltage V of MHTH, MH pipes enter critical conduction mode, and electric current is gradually reduced, and SW begins to decline；When SW drop to it is close
During ground voltage, SW ends MN13 by R4, MP10, I1, I2, H-LLSHIFT1, L-HLSHIFT1, slow down the shut-off of HDRV
Speed, reduces the current change rate of MH pipes, that is, reduces the overvoltage of MH pipe drain terminals；When HDRV-SW drops to VTH-When,
MN15 pipes end, and v1 voltages jump to BOOT from SW switching signals, turn on MN11 by I7, I8, I10, I11, and HDRV is rapid
SW is haled, MH pipes are completely switched off, but as the afterflow of inductance is acted on, electric current is extracted from GND by ML substrate diodes so that
SW drops to below GND.End MN18, MN20 by I9, H-LLSHIFT2, I14, I15, I16, I17 simultaneously, MP15, MP16
Pipe is turned on, and LDRV voltages are climbed to VDD, and ML enters fully on state.
Further, in the present embodiment, level translator includes 2 fast charging and discharging passages 601, can accelerate electricity
Flat transient state conversion speed, while not increasing the power consumption of static state.Below with low-high level translator L-H LSHIFT circuit structures
As a example by, it is introduced.As shown in Fig. 5～6, Fig. 5 is main circuit, and Fig. 6 is two high level pulses increased in signal input part
Produce circuit.Level translator main circuit in present embodiment includes：MP17～24, MN22～31, electric capacity CP1, CP2, electricity
Stream source I, VO1, VO2 are the first outfan, the second outfan respectively, INN, INP, IPO, INO be respectively MN24, MN25, MN22,
The input of MN23；Two high level pulses produce circuit by phase inverter I26, I27, I28, I30, nor gate I29, I31 and electricity
Resistance R8, R9, electric capacity C1, C2 composition, IN is signal input part.When the pwm signal of input IN occurs saltus step every time, add
NMOS tube MN22 or MN23 produce high level burst pulse in short-term, to CP1 or CP2 fast charging and dischargings.
As shown in fig. 7, wherein, Vthp is P ditches for the specific work process of level translator and each key event voltage waveform
The cut-in voltage of road metal-oxide-semiconductor；When it is low-level logic signal to be input into IN ends, MN24 closures, MN25 are ended, now VO1=
VBOOT-VGSP1, VGSP1For the gate source voltage of MP17, VO2=VBOOT, after comparator, VOUT=SW；When IN is jumped to from " 0 "
When " 1 ", IPO ends are maintained " 0 ", and INO produces high level pulse of the width for T, when this pulse jumps to " 1 " by " 0 ",
The path that VO2 is constituted to formation MN27 and MN23 between ground, to CP2 quick charges, simultaneously because the mirror image of MP19 and MP20 is made
With MP19 forms same electric current to CP1 repid discharges so that VO1 terminal voltages are raised, and work as VO1>During VO2, comparator upset,
VOUT=VBOOT.When this pulse is tuned to " 0 " by " 1 ", VO1=VBOOT, VOUT=VBOOT-VGSP2, wherein, VGSP2For MP24's
Gate source voltage, VOUT=VBOOTConstant, pulse width t is determined by the product of R8 and C1.When IN is in stable " 0 " or " 1 " shape
During state, this fast charging and discharging loop is closed, and maintains the level for determining by a less tail current I.
Second embodiment of the present utility model is related to a kind of drive circuit.Second embodiment is in first embodiment
On the basis of made further to improve, in this utility model second embodiment, to first comparator 304 and the first buffer
306 are simplified, concrete as shown in figure 8, realizing simple.
Specifically, in the present embodiment, first comparator 304 includes P-channel metal-oxide-semiconductor MP25, P-channel metal-oxide-semiconductor
MP10 and resistance R4, MP10 source electrodes are connected to external power source VIN, grid output switching signal SW, and drain electrode is connected to the leakage of MP25
Pole, even based on stabilized power source VDD, source electrode is even based on R4 one end, R4 other ends ground connection for the grid of MP25.
First buffer 306 includes the tenth phase inverter I1 being sequentially connected in series and the second low high level transducer L-
HLSHIFT1。
The 4th embodiment of this utility model is related to a kind of three segment drivers, as shown in figure 3, three segment drivers can
To be the one or three segment drivers 301 or the two or three segment drivers 302, below by taking the one or three segment drivers 301 as an example
Three segment drivers in present embodiment are introduced.Three segment drivers in present embodiment include：First P-channel
Metal-oxide-semiconductor MP11, the second P-channel metal-oxide-semiconductor MP12, the 3rd P-channel metal-oxide-semiconductor MP13, the first N-channel MOS pipe MN11, the second N-channel
Metal-oxide-semiconductor MN12, the 3rd N-channel MOS pipe MN13 and the 4th N-channel MOS pipe MN14.
The source electrode of the first P-channel metal-oxide-semiconductor MP11 is connected to power end, and grid is connected to the first control of three segment drivers
End, drain electrode are connected with the source electrode of the second P-channel metal-oxide-semiconductor MP12, and the drain electrode of the second P-channel metal-oxide-semiconductor MP12 is connected to three segmentations drive
The drive end of dynamic device, grid are connected to the second control end of three segment drivers；The source electrode connection of the 3rd P-channel metal-oxide-semiconductor MP13
In power end, grid is connected to the second control end, and drain electrode is connected to drive end.
The drain electrode of the second N-channel MOS pipe MN12 is connected to drive end, and grid is connected to the second control end, and source electrode is connected to
The drain electrode of the first N-channel MOS pipe MN11；The grid of the first N-channel MOS pipe MN11 is the 3rd control end of three segment drivers,
Source electrode is connected to the lowest electric potential point of three segment drivers；The drain electrode of the 3rd N-channel MOS pipe MN13 is connected to the second N-channel MOS
The source electrode of pipe MN12, grid is the 4th control end of three segment drivers, and source electrode is connected to lowest electric potential point；4th N-channel MOS
The drain electrode of pipe MN14 is connected to drive end, and grid is connected to the second control end, and source electrode is connected to lowest electric potential point.
High-voltage MOS pipe can be the injectron of Switching Power Supply；Power supply be Bootstrap power supply BOOT, lowest electric potential point
For the switch terminals of the drive circuit of Switching Power Supply；Or, high-voltage MOS pipe can be the high pressure continued flow tube of Switching Power Supply；Power supply is
Constant voltage source VDD, lowest electric potential point are ground terminal.
It is seen that, present embodiment is the device embodiment corresponding with first embodiment, and present embodiment can be with
First embodiment is worked in coordination enforcement.The relevant technical details mentioned in first embodiment still have in the present embodiment
Effect, in order to reduce repetition, is repeated no more here.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in
In first embodiment.
It is noted that each module involved in present embodiment is logic module, in actual applications, one
Individual logical block can be a part for a physical location, or a physical location, can be with multiple physics lists
The combination of unit is realized.Additionally, in order to project innovative part of the present utility model, will not be with this reality of solution in present embodiment
Introduced with the less close unit of new proposed technical problem relation, but there is no which during this is not intended that present embodiment
Its unit.
It will be understood by those skilled in the art that the respective embodiments described above are to realize of the present utility model being embodied as
Example, and in actual applications, can to which, various changes can be made in the form and details, without departing from spirit of the present utility model
And scope.
Claims (8)
1. a kind of three segment drivers, it is characterised in that for the high-voltage MOS pipe of driving switch power supply；Three drive part by part
Device includes：First P-channel metal-oxide-semiconductor (MP11), the second P-channel metal-oxide-semiconductor (MP12), the 3rd P-channel metal-oxide-semiconductor (MP13), a N ditches
Road metal-oxide-semiconductor (MN11), the second N-channel MOS pipe (MN12), the 3rd N-channel MOS pipe (MN13) and the 4th N-channel MOS pipe
(MN14)；
The source electrode of the first P-channel metal-oxide-semiconductor (MP11) is connected to power end, and grid is connected to the of three segment drivers
One control end, drain electrode are connected with the source electrode of the second P-channel metal-oxide-semiconductor (MP12), the second P-channel metal-oxide-semiconductor (MP12)
Drain electrode is connected to the drive end of three segment drivers, and grid is connected to the second control end of three segment drivers；Institute
The source electrode for stating the 3rd P-channel metal-oxide-semiconductor (MP13) is connected to the power end, and grid is connected to second control end, and drain electrode connects
It is connected to the drive end；
The drain electrode of the second N-channel MOS pipe (MN12) is connected to the drive end, and grid is connected to second control end,
Source electrode is connected to the drain electrode of the first N-channel MOS pipe (MN11)；The grid of the first N-channel MOS pipe (MN11) is described
3rd control end of three segment drivers, source electrode are connected to the lowest electric potential point of three segment drivers；3rd N-channel
The drain electrode of metal-oxide-semiconductor (MN13) is connected to the source electrode of the second N-channel MOS pipe (MN12), and grid is three segment drivers
The 4th control end, source electrode is connected to the lowest electric potential point；The drain electrode of the 4th N-channel MOS pipe (MN14) is connected to institute
Drive end is stated, grid is connected to second control end, and source electrode is connected to the lowest electric potential point.
2. three segment drivers according to claim 1, it is characterised in that height of the high-voltage MOS pipe for Switching Power Supply
Compress switch pipe；The power supply is Bootstrap power supply (BOOT), and the lowest electric potential point is the drive circuit of the Switching Power Supply
Switch terminals；Or,
High pressure continued flow tube of the high-voltage MOS pipe for Switching Power Supply；The power supply be constant voltage source (VDD), the lowest electric potential
Point is ground terminal.
3. a kind of drive circuit, it is characterised in that the injectron (MH) for driving switch power supply and high pressure continued flow tube
(ML), the drive circuit includes：One or three segment drivers (301), the two or three segment drivers (302) and non-overlapping unit
(303)；
Non-overlapping unit (303) and the two or three segment drivers (302) described in one or three segment drivers (301) Jing
Connection；The non-overlapping unit (303) is for producing dead band；
One or three segment drivers (301), for driving the injectron (MH)；Wherein, at described one or three point
The cut-in voltage V of the supply voltage of segment driver (301) to the injectron (MH)THBetween, using strong driving, drive institute
State injectron (MH) saturation region conducting state is entered from linear zone conducting state；In the VTHTo subthreshold voltage VTH-It
Between, using weak driving, slow down the rate of change of electric current in the injectron (MH)；Wherein, the VTH-Than the VTHValue
It is little；In the VTH-To between the lowest electric potential of the one or three segment drivers (301), using strong driving, the high pressure is driven
Switching tube (MH) is completely switched off；
Two or three segment drivers (302), for driving the high pressure continued flow tube (ML)；Wherein, at described two or three point
The cut-in voltage V of the supply voltage of segment driver (302) to the high pressure continued flow tube (ML)THBetween, using strong driving, drive institute
State high pressure continued flow tube (ML) saturation region conducting state is entered from linear zone conducting state；In the VTHTo subthreshold voltage VTH-It
Between, using weak driving, slow down the rate of change of electric current in the high pressure continued flow tube (ML)；Wherein, the VTH-Than the VTHValue
It is little；In the VTH-To between the lowest electric potential of the two or three segment drivers (302), using strong driving, the high pressure is driven
Continued flow tube (ML) is completely switched off.
4. drive circuit according to claim 3, it is characterised in that the one or three segment drivers (301) include：The
One P-channel metal-oxide-semiconductor (MP11), the second P-channel metal-oxide-semiconductor (MP12), the 3rd P-channel metal-oxide-semiconductor (MP13), the first N-channel MOS pipe
(MN11), the second N-channel MOS pipe (MN12), the 3rd N-channel MOS pipe (MN13) and the 4th N-channel MOS pipe (MN14)；
The source electrode of the first P-channel metal-oxide-semiconductor (MP11) is connected to the power end of the one or three segment drivers (301), grid
Pole is connected to the first control end of the one or three segment drivers (301), drains and the second P-channel metal-oxide-semiconductor (MP12)
Source electrode connection, the drain electrode of the second P-channel metal-oxide-semiconductor (MP12) is connected to the drive of the one or three segment drivers (301)
Moved end (HDRV), grid are connected to the second control end of the one or three segment drivers (301)；The 3rd P-channel metal-oxide-semiconductor
(MP13) source electrode is connected to the power end of the one or three segment drivers (301), and grid is connected to the one or three segmentation
Second control end of driver (301), drain electrode are connected to the drive end (HDRV) of the one or three segment drivers (301)；
The drain electrode of the second N-channel MOS pipe (MN12) is connected to the drive end of the one or three segment drivers (301), grid
Pole is connected to the second control end of the one or three segment drivers (301), and source electrode is connected to the first N-channel MOS pipe
(MN11) drain electrode；The grid of the first N-channel MOS pipe (MN11) for the one or three segment drivers (301) the 3rd
Control end, source electrode are connected to the lowest electric potential point of the one or three segment drivers (301)；The 3rd N-channel MOS pipe
(MN13) drain electrode is connected to the source electrode of the second N-channel MOS pipe (MN12), and grid is the one or three segment drivers
(301) the 4th control end, source electrode are connected to the lowest electric potential point of the one or three segment drivers (301)；The 4th N ditches
The drain electrode of road metal-oxide-semiconductor (MN14) is connected to the drive end (HDRV) of the one or three segment drivers (301), and grid is connected to institute
The second control end of the one or three segment drivers (301) is stated, source electrode is connected to the minimum of the one or three segment drivers (301)
Potential point；
Two or three segment drivers (302) include：4th P-channel metal-oxide-semiconductor (MP14), the 5th P-channel metal-oxide-semiconductor (MP15),
Six P-channel metal-oxide-semiconductors (MP16), the 5th N-channel MOS pipe (MN17), the 6th N-channel MOS pipe (MN18), the 7th N-channel MOS pipe
(MN19) with the 8th N-channel MOS pipe (MN20)；
The source electrode of the 4th P-channel metal-oxide-semiconductor (MP14) is connected to the power end of the two or three segment drivers (302), grid
Pole is connected to the first control end of the two or three segment drivers (302), drains and the 5th P-channel metal-oxide-semiconductor (MP15)
Source electrode connection, the drain electrode of the 5th P-channel MOS pipe (MP15) is connected to the drive of the two or three segment drivers (302)
Moved end (LDRV), grid are connected to the second control end of the two or three segment drivers (302)；The 6th P-channel metal-oxide-semiconductor
(MP16) source electrode is connected to the power end of the two or three segment drivers (302), and grid is connected to the two or three segmentation
Second control end of driver (302), drain electrode are connected to the drive end (LDRV) of the two or three segment drivers (302)；
The drain electrode of the 6th N-channel MOS pipe (MN18) is connected to the drive end of the two or three segment drivers (302), grid
Pole is connected to the second control end of the two or three segment drivers (302), and source electrode is connected to the 5th N-channel MOS pipe
(MN17) drain electrode；The grid of the 5th N-channel MOS pipe (MN17) for the two or three segment drivers (302) the 3rd
Control end, source electrode are connected to the lowest electric potential point of the two or three segment drivers (302)；The 7th N-channel MOS pipe
(MN19) drain electrode is connected to the source electrode of the 6th N-channel MOS pipe (MN18), and grid is the two or three segment drivers
(302) the 4th control end, source electrode are connected to the lowest electric potential point of the two or three segment drivers (302)；The 8th N ditches
The drain electrode of road metal-oxide-semiconductor (MN20) is connected to the drive end (LDRV) of the two or three segment drivers (302), and grid is connected to institute
The second control end of the two or three segment drivers (302) is stated, source electrode is connected to the minimum of the two or three segment drivers (302)
Potential point.
5. drive circuit according to claim 4, it is characterised in that the power supply of the one or three segment drivers (301)
For Bootstrap power supply (BOOT), the lowest electric potential point of the one or three segment drivers (301) is the drive of the Switching Power Supply
The switch terminals on galvanic electricity road；
The power supply of the two or three segment drivers (302) be constant voltage source (VDD), the two or three segment drivers (302)
Lowest electric potential point be ground terminal.
6. drive circuit according to claim 4, it is characterised in that the non-overlapping unit (303) includes：First is anti-phase
It is device (I9), the second phase inverter (I15), the 3rd phase inverter (I22), the 4th phase inverter (I23), the 5th phase inverter (I5), the 6th anti-
Phase device (I6), the 7th phase inverter (I16), the 8th phase inverter (I17), the first low and high level transducer (H-LLSHIFT2), first
Nor gate (I14), the first NAND gate (I4) and the first low high level transducer (L-HLSHIFT2)；
The input of first phase inverter (I9) is connected to the first control end of the one or three segment drivers (301), defeated
Go out the input that end is connected to the first low and high level transducer (H-LLSHIFT2), the first low and high level transducer
(H-LLSHIFT2) outfan is connected to the first input end of first nor gate (I14), first nor gate (I14)
The second input be connected to the first input end of first NAND gate (I4), the outfan of first nor gate (I14)
It is connected to the input of second phase inverter (I15), it is anti-that the outfan of second phase inverter (I15) is connected to the described 7th
The outfan of phase device (I16), the outfan of the 7th phase inverter (I16) are connected to the input of the 8th phase inverter (I17)
End, the outfan of the 8th phase inverter (I17) are connected to the second control of the two or three segment drivers (302) simultaneously
End, the 3rd control end of the two or three segment drivers (302)；
Second input of first NAND gate (I4) is connected to the outfan of the 4th phase inverter (I23), and the described 4th
The input of phase inverter (I23) is connected to the outfan of the 3rd phase inverter (I22), the 3rd phase inverter (I22) it is defeated
Enter the 3rd control end that end is connected to the two or three segment drivers (302)；
The outfan of first NAND gate (I4) is connected to the input of the described first low high level transducer (L-HLSHIFT2)
End, the outfan of the first low high level transducer (L-HLSHIFT2) are connected to the input of the 5th phase inverter (I5)
End, the outfan of the first low high level transducer (L-HLSHIFT2) are also attached to the one or three segment drivers
(301) the 3rd control end；The outfan of the 5th phase inverter (I5) is connected to the input of the hex inverter (I6),
The outfan of the hex inverter (I6) is connected to the second control end of the one or three segment drivers (301).
7. drive circuit according to claim 6, it is characterised in that also including first comparator (304), the second comparator
(305), the first buffer (306), the second buffer (307), the 3rd buffer (308), the 4th buffer (309) are anti-with the 9th
Phase device (I3), the first single tube comparator (310) and the second single tube comparator (311)；
The first comparator (304), first buffer (306), the 9th phase inverter (I3) are sequentially connected in series to described
First control end of the one or three segment drivers (301)；The company of first buffer (306) and the 9th phase inverter (I3)
Connect the 4th control end that node is additionally coupled to the one or three segment drivers (301)；
The first input end of second buffer (307) is connected to the described first low high level transducer (L-HLSHIFT2)
Outfan, the first outfan are connected to the input of first phase inverter (I9), and the second outfan is connected to the described 1st
3rd control end of segment drivers (301), the second input are connected to the first single tube comparator (310)；First single tube
Comparator (310) is connected to the power end of the one or three segment drivers (301) and the one or three segment drivers (301)
Lowest electric potential point between, the first single tube comparator (310) is also attached to the drive of the one or three segment drivers (301)
Moved end (HDRV)；
Second comparator (305), the 3rd buffer (308) are sequentially connected in series to the two or three segment drivers
(302) the first control end；
The first input end of the 4th buffer (309) is connected to the outfan of second phase inverter (I15), the first output
End is connected to the input of the 3rd phase inverter (I22), and the second outfan of the 4th buffer (309) is connected to described
3rd control end of the two or three segment drivers (302), the second input are connected to the second single tube comparator (311)；Institute
State power end and the described 2nd 3 segmentation that the second single tube comparator (311) is connected to the two or three segment drivers (302)
Between the lowest electric potential point of driver (302), the second single tube comparator (311) is also attached to the two or three drive part by part
The drive end (LDRV) of device (302).
8. drive circuit according to claim 7, it is characterised in that the first comparator (304) includes：First resistor
(R4) with the 7th P-channel metal-oxide-semiconductor (MP10)；
Described first resistor (R4) one end is connected to external power source (VIN), and the other end is connected to the 7th P-channel metal-oxide-semiconductor
(MP10) source electrode, the drain electrode of the 7th P-channel metal-oxide-semiconductor (MP10) are connected to the one or three segment drivers (301)
Lowest electric potential point, grid input predeterminated voltage signal (VCLAMP)；Wherein, the predeterminated voltage signal (VCLAMP) outer equal to described
The difference of the voltage signal of portion's power supply (VIN) and the voltage signal of stabilized power source (VDD)；
First buffer (306) includes：Tenth phase inverter (I1), the 11st phase inverter (I2), the conversion of the second low and high level
Device (H-LLSHIFT1), the second low high level transducer (L-HLSHIFT1)；The input connection of the tenth phase inverter (I1)
In the first resistor (R4) and the connecting node of the 7th P-channel metal-oxide-semiconductor (MP10), it is anti-phase that outfan is connected to the described 11st
The input of device (I2), the outfan of the 11st phase inverter (I2) are connected to the second low and high level transducer (H-
LLSHIFT1 input), it is low that the outfan of the second low and high level transducer (H-LLSHIFT1) is connected to described second
The input of high level transducer (L-HLSHIFT1), the outfan of the second low high level transducer (L-HLSHIFT1) connect
It is connected to the input of the 9th phase inverter (I3)；
Second buffer (307) includes：Second NAND gate (I10), the 12nd phase inverter (I7), the 13rd phase inverter (I8)
With the 14th phase inverter (I11)；The first input end of second NAND gate (I10) is connected to second buffer (307)
First input end, the second input is connected to the first outfan of second buffer (307), and outfan is connected to described
The input of the 14th phase inverter (I11), the outfan of the 14th phase inverter (I11) are connected to second buffer
(307) the second outfan, the input of the 12nd phase inverter (I7) are connected to the second of second buffer (307)
Input, outfan are connected to the input of the 13rd phase inverter (I8), the outfan of the 13rd phase inverter (I8)
It is connected to the first outfan of second buffer (307)；
The first single tube comparator (310) includes：Second resistance (R5) and the 9th N-channel MOS pipe (MN15)；Described second is electric
Resistance (R5) one end is connected to the power end of the one or three segment drivers (301), and the other end is connected to the 9th N-channel
The drain electrode of metal-oxide-semiconductor (MN15), the source electrode of the 9th N-channel MOS pipe (MN15) are connected to the one or three segment drivers
(301) lowest electric potential point, drain electrode are connected to the drive end (HDRV) of the one or three segment drivers (301)；Described second
It is second defeated that resistance (R5) and the connecting node of the 9th N-channel MOS pipe (MN15) are connected to second buffer (307)
Enter end；
Second comparator (305) includes：Tenth N-channel MOS pipe (MN16) and 3rd resistor (R6)；Tenth N-channel
The drain electrode of metal-oxide-semiconductor (MN16) is connected to the lowest electric potential point of the one or three segment drivers (301), and source electrode is connected to described
One end of three resistance (R6), grid are connected to the stabilized power source (VDD)；The other end of the 3rd resistor (R6) is connected to institute
State the lowest electric potential point of the two or three segment drivers (302)；
3rd buffer (308) includes：15th phase inverter (I12) and the tenth hex inverter (I13)；Described 15th is anti-
The input of phase device (I12) is connected to the connecting node of the tenth N-channel MOS pipe (MN16) and the 3rd resistor (R6),
Outfan is connected to the input of the tenth hex inverter (I13), and the outfan of the tenth hex inverter (I13) is connected to
First control end of the two or three segment drivers (302)；
4th buffer (309) includes：3rd NAND gate (I20), the 17th phase inverter (I21), eighteen incompatible medicamentss phase device
(I18) with the 19th phase inverter (I19)；The first input end of the 3rd NAND gate (I20) is connected to the 4th buffer
(309) first input end, the second input are connected to the first outfan of the 4th buffer (309), outfan connection
In the input of the 17th phase inverter (I21), the outfan of the 17th phase inverter (I21) is connected to the described 4th and delays
The second outfan of device (309) is rushed, the input of the eighteen incompatible medicamentss phase device (I18) is connected to the 4th buffer (309)
The second input, outfan is connected to the input of the 19th phase inverter (I19), the 19th phase inverter (I19)
Outfan be connected to the first outfan of the 4th buffer (309)；
The second single tube comparator (311) includes：11st N-channel MOS pipe (MN21) and the 4th resistance (R7)；
Described 4th resistance (R7) one end is connected to the stabilized power source (VDD), and the other end is connected to the 11st N-channel
The drain electrode of metal-oxide-semiconductor (MN21)；The source electrode of the 11st N-channel MOS pipe (MN21) is connected to the two or three segment drivers
(302) lowest electric potential point, grid are connected to the drive end (LDRV) of the two or three segment drivers (302)；Described tenth
One N-channel MOS pipe (MN21) is connected to the second of the 4th buffer (309) with the connecting node of the 4th resistance (R7)
Input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621087815.9U CN206099773U (en) | 2016-09-27 | 2016-09-27 | Three sectional drive ware and drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621087815.9U CN206099773U (en) | 2016-09-27 | 2016-09-27 | Three sectional drive ware and drive circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452076A (en) * | 2016-09-27 | 2017-02-22 | 上海智浦欣微电子有限公司 | Voltage control method, three-subsection driver and drive circuit |
| CN109842285A (en) * | 2019-02-27 | 2019-06-04 | 南京融芯微电子有限公司 | Shorten the driving circuit of dead time suitable for synchronous DC-DC converter driver |
-
2016
- 2016-09-27 CN CN201621087815.9U patent/CN206099773U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106452076A (en) * | 2016-09-27 | 2017-02-22 | 上海智浦欣微电子有限公司 | Voltage control method, three-subsection driver and drive circuit |
| CN106452076B (en) * | 2016-09-27 | 2019-03-15 | 上海智浦欣微电子有限公司 | Voltage control method, three segment drivers and driving circuit |
| CN109842285A (en) * | 2019-02-27 | 2019-06-04 | 南京融芯微电子有限公司 | Shorten the driving circuit of dead time suitable for synchronous DC-DC converter driver |
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| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20170412 Effective date of abandoning: 20190315 |
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| AV01 | Patent right actively abandoned |