CN206021129U - Real time clock unit in a kind of microcontroller SOC - Google Patents

Abstract

The utility model discloses real time clock unit in a kind of microcontroller SOC, including reset control module, clock generation module, RTC time blocks, Clock gating module and microcontroller core, the microcontroller core connects Clock gating module, and Clock gating module connects reset control module, clock generation module and RTC time blocks respectively.The beneficial effects of the utility model are：In this programme, when microcontroller SOC in a dormant state, worked in low frequency RTC block wake up after, can respond ensuing sleep request at once, rather than need etc. the RTC clock of at least 2 low frequencies.Thereby so that microcontroller core can reenter resting state in time, so that microcontroller SOC can be applied to the application scenario stricter to power consumption requirements.

Description

Real time clock unit in a kind of microcontroller SOC

Technical field

The present invention relates to a kind of clock unit, real time clock unit in specifically a kind of microcontroller SOC.

Background technology

In a lot of products applications, how particularly battery powered use occasion accomplishes that low-power consumption is one and weighs very much The problem that wants.Real-time clock (RTC, Real Time Clock) module is conventional in the low-power consumption application of microcontroller SOC One function module.A lot of low-power consumption application scenarios, in order to pursue lower power consumption, is required for using in microcontroller SOC Real-time clock module.In the occasion of general low-power consumption application, user's application all can allow microcontroller SOC long-times to be put as far as possible In the sleep pattern (Sleep Mode) of low-power consumption, and essence is carried out by the real-time clock module (RTC) in microcontroller SOC True timing, when timing is reached, RTC block produces wake request signal, and microcontroller SOC is called out by sleep pattern Wake up, then microcontroller SOC carries out the work of next stage again.

Content of the invention

It is an object of the invention to provide real time clock unit in a kind of microcontroller SOC, to solve above-mentioned background technology The problem of middle proposition.

For achieving the above object, the present invention provides following technical scheme：

Real time clock unit in a kind of microcontroller SOC, including reset control module, clock generation module, RTC timing moulds Block, Clock gating module and microcontroller core, the microcontroller core connect Clock gating module, Clock gating module point Lian Jie not reset control module, clock generation module and RTC time blocks；

Preferred version as the present invention：The Clock gating module includes depositor R1, depositor R2, on-off control list First GAME, phase inverter INV1, phase inverter INV2 and OR gate OR.

Compared with prior art, the invention has the beneficial effects as follows：In this programme, when microcontroller SOC is in dormancy shape State, worked in low frequency RTC block wake up after, can respond ensuing sleep request at once, rather than need etc. The RTC clock of at least 2 low frequencies.Thereby so that microcontroller core can reenter resting state in time, so that micro- Controller SOC can be applied to the application scenario stricter to power consumption requirements.

Description of the drawings

Fig. 1 is the structured flowchart of real time clock unit in microcontroller SOC.

Specific embodiment

Accompanying drawing in below in conjunction with the embodiment of the present invention, to the embodiment of the present invention in technical scheme carry out clear, complete Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiment.It is based on Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made Embodiment, belongs to the scope of protection of the invention.

Fig. 1 is referred to, real time clock unit in a kind of microcontroller SOC produces mould including reset control module, clock Block, RTC time blocks, Clock gating module and microcontroller core, the microcontroller core connect Clock gating module, when Clock gating module connects reset control module, clock generation module and RTC time blocks respectively；

Clock gating module includes depositor R1, depositor R2, phase inverter INV1, switch control unit GAME, phase inverter INV2 and OR gate OR.

The present invention operation principle be：Reseting module (reset_gen)：

Reseting module is responsible for the main reset signal for producing chip：Keyboard scan logical reset signal (rstn_rtc), micro- Controller core reset signal (rstn_core).In the chips, reset signal is Low level effective.

Clock module (clock_gen)：

Clock module is responsible for the Core Operational clock (clk_core) for producing chip.

The working time of RTC simulations is provided by outside 32KHz crystal oscillators

RTC block (RTC)：

This module is timed according to the 32KHz clocks that external crystal-controlled oscillation is provided.This module can carry out configuration enable with user, Configuration timing etc..After RTC block is enabled, its internal intervalometer starts timing, when the timing for reaching configuration When, wake-up signal wake_req will be produced.

Clock gating module (CLK_CTRL)：

Clock gating module is responsible for gating the Core Operational clock (clk_core) of chip, the clock after gate (clk_core) as the work clock of microcontroller core.In order that microcontroller SOC can be applied to power consumption requirements more Plus strict application scenario, user's application can allow microcontroller SOC long-times to be placed in the sleep pattern (Sleep of low-power consumption Mode).When microcontroller SOC in a dormant state, can be carried out by the real-time clock module (RTC) in microcontroller SOC Accurate timing, after timing is reached, RTC block produces wake request signal, by microcontroller SOC by sleep pattern Wake up.

Clock gating module receives the sleep request (sleep_req) of microcontroller core, produces clock and enables signal Clk_enable (low level output represents closing microcontroller core work clock) is exported to clock switch control unit (GATE), so as to by microcontroller core work clock (clk_core_gc) close.Clock gating module receives RTC block (RTC) wake request (wake_req), (high level output represents unlatching microcontroller to produce clock enable signal clk_enable Device Core Operational clock) export to clock switch control unit (GATE), so as to by microcontroller core work clock (clk_ Core_gc) open.

The operation principle of Clock gating module is as shown in Figure 1.Clock gating module receives the dormancy of microcontroller core Request signal (sleep_req), sleep request signal (sleep_req) are connected to the D ends of depositor R2.Microcontroller core Sleep request (sleep_req) is a pulse signal, and effective pulse width is 1 microcontroller core clock cycle.When When sleep_req is effectively asked, the output signal (sleep_en) of depositor R2 will be latched as high level output state.sleep_ En signals are connected to the input of OR gate OR after phase inverter INV2 is negated.Another input of OR gate OR is connected to Wake up gate-control signal (wake_en).In the case of without effectively waking up, gate-control signal (wake_en) is waken up for low level, institute Signal clk_enable is enabled with clock to be input into clock switch control unit (GATE) as low level state, so as to by microcontroller Device Core Operational clock (clk_core_gc) cuts out, and saves power consumption in the case of realizing dormancy.Although sleep_req signals has Effect pulse width be 1 microcontroller core clock cycle, but due to the work clock of depositor R2 be gate after kernel Clock clk_core_gc, so output signal sleep_en of depositor R2 can continue after sleep_req invalidating signals High level output signal is latched as, so that clock enables signal clk_enable and is input into clock switch control for low level state Thus unit (GATE) processed, microcontroller core are also continuously in resting state.When RTC block reaches the timing of user setup Between after, RTC block will produce wake request signal, and the output of depositor R1 can believe with wake-up corresponding logic circuit Number wake_en is high level output state, and then thus the output signal of OR gate OR also changes high level output state, export to Clock switch control unit (GATE), so that open microcontroller core work clock (clk_core_gc).In microcontroller Verification Clock gating module (CLK_CTRL) feedback kernel wakes up feedback signal (wake_rps).Kernel wakes up feedback signal (wake_rps), when representing microcontroller core in a dormant state for low level, it is that high level represents that microcontroller core is in During working condition.After microcontroller core is waken up in the presence of gate-control signal (wake_en) is waken up, by microcontroller It is high significant level that core is input into and wakes up feedback signal (wake_rps) to the kernel of Clock gating module (CLK_CTRL), through anti- Change low level after phase device INV1.The output of phase inverter INV1 is connected to the asynchronous reset inputs of depositor R1, thus will Depositor R1 resets.After depositor R1 resets, wake up gate-control signal (wake_en) and low electricity will be switched to by high effective status at once Flat output state.By the effect of above-mentioned logic, gate-control signal can will be waken up in time after microcontroller core is waken up (wake_en) low level output state will be switched to by high effective status.Therefore, when microcontroller core is called out from park mode After waking up, ensuing sleep request can be responded at once, reenter low-power consumption mode.And in general design, when micro- After controller kernel is waken up, in addition it is also necessary to which, after waiting two microcontroller core clock cycle, microcontroller core could again Enter low-power consumption mode.Therefore, present design can realize lower power consumption, it is adaptable to which harsher to power consumption requirements should Use occasion.

It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie In the case of spirit or essential attributes without departing substantially from the present invention, the present invention can be realized in other specific forms.Therefore, no matter From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power Profit is required rather than described above is limited, it is intended that all in the implication and scope of the equivalency of claim by falling Change is included in the present invention.Any reference in claim should not be considered as and limit involved claim.

Moreover, it will be appreciated that although this specification is been described by according to embodiment, not each embodiment is only wrapped Contain an independent technical scheme, this narrating mode of description is only that those skilled in the art should for clarity Using description as an entirety, the technical scheme in each embodiment can also form those skilled in the art through appropriately combined Understandable other embodiment.

Claims (2)

1. real time clock unit in a kind of microcontroller SOC, including reset control module, clock generation module, RTC timing moulds Block, Clock gating module and microcontroller core, it is characterised in that the microcontroller core connects Clock gating module, when Clock gating module connects reset control module, clock generation module and RTC time blocks respectively.

2. real time clock unit in a kind of microcontroller SOC according to claim 1, it is characterised in that the clock gate Control module includes depositor R1, depositor R2, phase inverter INV1, switch control unit GAME, phase inverter INV2 and OR gate OR.