CN205992527U - Chip package board structure - Google Patents
Chip package board structure Download PDFInfo
- Publication number
- CN205992527U CN205992527U CN201621035686.9U CN201621035686U CN205992527U CN 205992527 U CN205992527 U CN 205992527U CN 201621035686 U CN201621035686 U CN 201621035686U CN 205992527 U CN205992527 U CN 205992527U
- Authority
- CN
- China
- Prior art keywords
- substrate
- chip
- board structure
- package board
- chip package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model discloses a kind of chip package board structure, including multilager base plate, it is fixedly connected between substrate and substrate, wherein one laminar substrate is provided with multiple chip hole (2.1) for housing chip (5).This board structure can install multiple chips, so that the levelness between chip is relatively consistent.
Description
Technical field
This utility model is related to chip encapsulation technology field, more particularly to chip package board structure and have
Many camera lenses camera module of this board structure.
Background technology
In chip encapsulation technology, current chip be substantially individual packages on substrate that is to say, that in multicore
In the situation of piece, one piece of substrate only carries a chip, is separate between substrate and substrate.Such as, in the market
The two chips of the twin-lens camera module sold are individually enclosed on one piece of substrate.And twin-lens camera module is to lens assembly
High with the status requirement of chip.And two chips are individually enclosed on one piece of substrate, it is difficult to ensure that the level of two chips
Degree is consistent, and that is, two chips of many camera lenses camera module need to be maintained at the same horizontal plane in the ideal situation, thus shadow
Ring the performance of dual camera module.
Utility model content
The technical problems to be solved in the utility model is to provide a kind of chip package board structure, this board structure energy
Multiple chips are installed, so that the levelness between chip is relatively consistent.
Technical solution of the present utility model is to provide a kind of chip package board structure with following structure,
Including multilager base plate, it is fixedly connected between substrate and substrate, wherein one laminar substrate is provided with multiple chips for housing chip
Hole.
After above structure, chip package board structure of the present utility model, compared with prior art, have following
Advantage：
Wherein one laminar substrate due to chip package board structure of the present utility model is provided with multiple chip hole, will be many
Individual integrated chip is on one piece of substrate, it is possible to decrease the difficulty of the levelness between control chip, enables the levelness between chip
Relatively it is consistent, thus the performance of chip package can be improved.
As improvement, the lower surface that the substrate on the upside of described chip hole is located at the region above chip hole is provided with conductive stud
Block.After adopting the structure, the connection between chip and circuit is more convenient.
As improvement, described substrate is provided with two-layer, and described chip hole is on underlying substrate.
Brief description
Fig. 1 is the cross section structure diagram of the embodiment one of chip package board structure of the present utility model.
Fig. 2 is the cross section structure diagram of the embodiment two of chip package board structure of the present utility model.
Shown in figure：1st, first substrate, 1.1, through hole, 2, second substrate, 2.1, chip hole, 3, conductive projection.
Specific embodiment
The utility model is described in further detail with specific embodiment below in conjunction with the accompanying drawings.
Embodiment one
Refer to shown in Fig. 1, chip package board structure of the present utility model includes first substrate 1 and second substrate 2,
It is fixedly connected between described first substrate 1 and second substrate 2, described first substrate 1 is located at the upper of described second substrate 2
Side, in this specific embodiment, is fixedly connected by glue between described first substrate 1 and second substrate 2.Described second substrate
2 are provided with multiple chip hole 2.1 for housing chip.Described first substrate 1 is located under the region of chip hole 2.1 top
Surface is provided with conductive projection 3.
Embodiment two
Refer to shown in Fig. 2, chip package board structure of the present utility model includes first substrate 1 and second substrate 2,
It is fixedly connected between described first substrate 1 and second substrate 2, described first substrate 1 is located at the upper of described second substrate 2
Side, in this specific embodiment, is fixedly connected by glue between described first substrate 1 and second substrate 2.Described second substrate
2 are provided with multiple chip hole 2.1 for housing chip.Described first substrate 1 is located under the region of chip hole 2.1 top
Surface is provided with conductive projection 3.The middle part that described first substrate 1 is located at the region of chip hole 2.1 top is provided with through hole 1.1.
Claims (3)
1. a kind of chip package board structure, including multilager base plate, be fixedly connected between substrate and substrate it is characterised in that：
Wherein one laminar substrate is provided with multiple chip hole (2.1) for housing chip (5).
2. chip package board structure according to claim 1 it is characterised in that：On the upside of described chip hole (2.1)
The lower surface in region that is located above chip hole (2.1) of substrate be provided with conductive projection (3).
3. chip package board structure according to claim 2 it is characterised in that：Described substrate is provided with two-layer, institute
The chip hole (2.1) stated is on underlying substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621035686.9U CN205992527U (en) | 2016-08-31 | 2016-08-31 | Chip package board structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201621035686.9U CN205992527U (en) | 2016-08-31 | 2016-08-31 | Chip package board structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205992527U true CN205992527U (en) | 2017-03-01 |
Family
ID=58105521
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621035686.9U Expired - Fee Related CN205992527U (en) | 2016-08-31 | 2016-08-31 | Chip package board structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205992527U (en) |
-
2016
- 2016-08-31 CN CN201621035686.9U patent/CN205992527U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170301 Termination date: 20210831 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |