CN205921597U - Is there IRIG who returns to school B sign indicating number module - Google Patents
Is there IRIG who returns to school B sign indicating number module Download PDFInfo
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- CN205921597U CN205921597U CN201620619389.2U CN201620619389U CN205921597U CN 205921597 U CN205921597 U CN 205921597U CN 201620619389 U CN201620619389 U CN 201620619389U CN 205921597 U CN205921597 U CN 205921597U
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Abstract
The utility model discloses an is there IRIG who returns to school B sign indicating number module, including FPGA chip and multimode fiber head, the multimode fiber head sends head and multimode fiber receipt head including multimode fiber, does the FPGA chip include IRIG B decoder module, delay compensation module and UART module and a IO interface, the 2nd IO interface, the 3rd IO interface, fourth IO interface, the 5th IO interface and the 6th IO interface, does multimode fiber send the head through the 3rd IO interface and IRIG B decoder module connects, IRIG B decoder module passes through the 2nd IO interface and imports 1PPS's bus connection, IRIG B decoder module passes through the bus connection of fourth IO interface and input time information, is the delay compensation module through a IO interface and input IRIG the bus connection of B sign indicating number, delay compensation module and the 6th IO interface connection, IRIG the B decoder module running state module is connected, running state module and UART module are connected, UART module and the 5th IO interface connection. The utility model discloses have the function of returning to school, guarantee by time service device's time accuracy.
Description
Technical field
This utility model belongs to the intelligent output board of synchronised clock in power distribution automation, be more particularly to a kind of have return to school
Irig-b code module.
Background technology
The synchronization accuracy of irig-b (dc) code, up to tens nanosecond orders, serial time code, has six kinds of forms.I.e.
irig—a、b、d、e、g、h.Their the frame rate difference that main difference is that timing code, from the d lattice of a frame per hour the slowest
Formula is to the g form of every ten millisecond of one frame the fastest.Irig-b000 is widely used in power system.In power system, especially
It is that intelligent grid adopts advanced sensing and e measurement technology, advanced equipment and technology, advanced control method and advanced determining
Plan supports the application of systems technology, and these advanced technologies all rely on clearly logical sequence.But in actual motion environment,
Due to the difference of transmission material and transmission path distance different thus leading to the time disunity of each time service equipment, do not reach
Precision when 1us pair of the quasi- code requirement of state's network mark.Traditional irig-b code module only has output port, does not have receiving port, because
This can only ensure module delivery outlet time precision it is impossible to ensure reach by time service equipment pair when precision.
Utility model content
In order to solve said one or multiple technical problem, this utility model offer is a kind of the irig-b code mould returned to school
Part.
The technical solution of the utility model is as follows:
There is the irig-b code module returned to school, including fpga chip and multimode fibre head, multimode fibre head includes multimode fibre
Delivery header and multimode fibre receive head, and fpga chip receives head and is connected with multimode fibre delivery header with multimode fibre respectively,
Fpga chip is connected with ept terminal,
Fpga chip includes irig-b decoder module, phase bits comparison module, temporal information conversion check module, delay compensation mould
Block, running status module and uart module and an i/o interface, the 2nd i/o interface, the 3rd i/o interface, the 4th i/o interface,
5th i/o interface and the 6th i/o interface, multimode fibre delivery header passes through the 3rd i/o interface and irig-b decoder module connects,
Irig-b decoder module is connected with phase bits comparison module and temporal information conversion check module respectively, and phase bits comparison module passes through second
The bus of i/o interface and input 1pps connects, and temporal information conversion check module passes through the 4th i/o interface and input time information
Bus connects, and delay compensation module passes through an i/o interface and the bus of input irig-b code connects, delay compensation module and the
Six i/o interfaces connect, and phase bits comparison module and temporal information conversion check module are connected with running status module respectively, described operation
Block of state and uart module connect, and uart module passes through the 5th i/o interface and ept terminal connects.
Its advantage is: signal stream through path is: the benchmark of ept terminal reception arrival self-clocking device cpu plate
After time signal, reference time signal is transferred to fpga chip；Ept terminal receives the running status letter of fpga chip simultaneously
Breath, by this information transmission to Synchronization Clock cpu plate.After fpga chip receives reference time signal, to multimode fibre
The transmission reference time signal of delivery header, multimode fibre delivery header by reference time signal by ttl level conversion optical signal after, and
It is sent out reference time signal.Reference time signal reaches by time service equipment by communication optical fiber cable, through by time service equipment
The multimode fibre being put back into after amplification in module receives head, and multimode fibre receives head and by optical signal, reference signal is converted to ttl
Level, and return to fpga chip, fpga chip carries out to signal of returning to school processing calculating, draws path delay.
Fpga chip to the handling process of signal of returning to school is: passes through optical fiber from the irig-b code being returned by time service device
Defeated, it is input to multimode fibre and receives head, multimode fibre receives head and optical signal irig-b code is changed into ttl level signal, passes through
3rd i/o interface of fpga chip transmits to irig-b decoder module, obtains " returning to school after the decoding of irig-b decoder module
1pps " and " temporal information of returning to school ".Phase bits comparison module passes through the " total of the 2nd i/o interface input to " return to school 1pps " and bus
Line inputs 1pps " carry out 1pps phase bit comparison, obtain " the 1pps deviant " returning irig-b code；Temporal information conversion check module
" temporal information of returning to school " and bus are passed through with the 4th i/o interface entrance " bus input time information " carries out the anti-school of temporal information
Test, obtain " the temporal information deviant " returning irig-b code.Delay compensation module is according to " 1pps deviant " and " temporal information
" bus inputs irig-b code " that deviant " passes through an i/o interface input to bus carries out outgoing route compensation, through revising
Irig-b code after compensation passes through the 6th i/o interface output.According to " 1pps deviant " and " temporal information is inclined for running status module
Shifting value " calculates the running status of transmission path delay and module, and these information carry out after parallel-serial conversion through uart module,
Exported by the 5th i/o interface.
This utility model has function of returning to school it is ensured that reaching by the time accuracy of time signal to signal.
In some embodiments, also include power module, power module is connected with fpga chip and multimode fibre head respectively
Connect.
Its advantage is: power supply is responsible for power supply, and the control chip of power module is max1951, input voltage dc24v,
Produce dc3.3v and dc5v through dc-dc circuit, dc3.3v is fpga chip power supply；Dc5v powers for multimode fibre head.
In some embodiments, fpga chip, multimode fibre head and power module are arranged on module body, module
Installing hole is offered on body.
Its advantage is: installs the mounting blocks for connecting with cabinet by installing hole.
Brief description
Fig. 1 is a kind of structural representation having the irig-b code module returned to school of this utility model one embodiment；
Fig. 2 is a kind of signal having the fpga chip of irig-b code module returned to school of this utility model one embodiment
Figure.
The title of the corresponding component represented by figure numeral:
1.fpga chip, 10. running status module, 11.irig-b decoder module, 111. phase bits comparison module, 112. when
Between information conversion check module, 12. delay compensation module, 13.uart module, 14. the oneth i/o interfaces, 15. the 2nd i/o interfaces,
16. the 3rd i/o interfaces, 17. the 4th i/o interfaces, 18. the 5th i/o interfaces, 19. the 6th i/o interfaces, 2. multimode fibre head, 21.
Multimode fibre delivery header, 22. multimode fibres receive head, 3.ept terminal, 4. power module, 5. module body, 51. installing holes.
Specific embodiment
As shown in Figure 1-2, this utility model provide a kind of have the irig-b code module returned to school, include fpga chip 1 with many
Mode fiber head 2.Multimode fibre head 2 includes multimode fibre delivery header 21 and multimode fibre reception 22.Fpga chip 1 respectively with many
Mode fiber delivery header 21 and and multimode fibre reception 22 connection.Fpga chip 1 is connected with ept terminal 3.
Fpga chip 1 include irig-b decoder module 11, phase bits comparison module 111, temporal information conversion check module 112,
Delay compensation module 12, running status module 10 and uart module 13 and an i/o interface 14, the 2nd i/o interface the 15, the 3rd
I/o interface 16, the 4th i/o interface 17, the 5th i/o interface 18 and the 6th i/o interface 19.Multimode fibre delivery header 21 passes through the 3rd
I/o interface 16 and irig-b decoder module 11 connect.Irig-b decoder module 11 is believed with phase bits comparison module 111 and time respectively
Breath conversion check module 112 connects, and phase bits comparison module 111 passes through the 2nd i/o interface 15 and the bus of input 1pps connects.Time
Information conversion check module 112 passes through the 4th i/o interface 17 and the bus of input time information connects.Delay compensation module 12 is passed through
The bus of the first i/o interface 14 and input irig-b code connects.Delay compensation module 12 is connected with the 6th i/o interface 19.Phase place
Comparison module 111 and temporal information conversion check module 112 are connected with running status module 10 respectively.Running status module 10 He
Uart module 13 connects.Uart module 13 passes through the 5th i/o interface 18 and ept terminal 3 connects.
Signal stream through path is: ept terminal 3 receives after the reference time signal of Synchronization Clock cpu plate, will
Reference time signal is transferred to fpga chip 1；Ept terminal 3 receives the running state information of fpga chip 1 simultaneously, by this information
Send the cpu plate of Synchronization Clock to.After fpga chip 1 receives reference time signal, to multimode fibre delivery header 21
Send reference time signal, multimode fibre delivery header 21 by reference time signal by ttl level conversion optical signal after, and to outgoing
Send reference time signal.Reference time signal is reached by time service equipment by communication optical fiber cable, after being amplified by time service equipment
It is put back into the multimode fibre reception 22 in module, reference signal is converted to ttl electricity by optical signal by multimode fibre reception 22
Flat, and return to fpga chip 1, fpga chip 1 carries out to signal of returning to school processing calculating, draws path delay.
Fpga chip 1 to the handling process of signal of returning to school is: passes through optical fiber from the irig-b code being returned by time service device
Defeated, it is input to multimode fibre reception 22, irig-b code optical signal is changed into ttl level signal, leads to by multimode fibre reception 22
The 3rd i/o interface 16 crossing fpga chip 1 transmits to irig-b decoder module 11, after irig-b decoder module 11 decoding
To " return to school 1pps " and " temporal information of returning to school ".Phase bits comparison module 111 passes through the 2nd i/o interface to " return to school 1pps " and bus
" bus inputs 1pps " of 15 inputs carries out 1pps phase bit comparison, obtains " the 1pps deviant " returning irig-b code；Time believes
" bus input time information " that breath conversion check module passes through the 4th i/o interface 17 entrance to " temporal information of returning to school " and bus is entered
Row temporal information conversion check, obtains " the temporal information deviant " returning irig-b code.Delay compensation module 12 is according to " 1pps is inclined
Shifting value " and " temporal information deviant " bus is passed through an i/o interface 14 input " bus inputs irig-b code " carry out defeated
Outbound path compensates, and the irig-b code after correction-compensation is exported by the 6th i/o interface 19.Running status module 10 basis
" 1pps deviant " and " temporal information deviant " calculates the running status of transmission path delay and module, these information warps
Cross after uart module carries out parallel-serial conversion, exported by the 5th i/o interface 18.
In the present embodiment, also include power module 4, power module 4 respectively with fpga chip 1 and multimode fibre head 2
Connect.Power module is responsible for power supply, and the control chip of power module is max1951, input voltage dc24v, through dc-dc circuit
Produce dc3.3v and dc5v, dc3.3v powers for fpga chip 1；Dc5v powers for multimode fibre head 2.Fpga chip 1, multimode light
Fibre 2 and power module 4 are arranged on module body 5, and module body 5 offers installing hole 51.Pacified by installing hole 51
Fill the mounting blocks for connecting with cabinet.
Above-described is only a kind of some embodiments having the irig-b code module returned to school of this utility model, for this
For the those of ordinary skill of field, on the premise of not paying creative work, some deformation can also be made and improve, these
Broadly fall into protection domain of the present utility model.
Claims (3)
1. a kind of have the irig-b code module returned to school it is characterised in that including fpga chip and multimode fibre head, described multimode light
Fine head includes multimode fibre delivery header and multimode fibre and receives head, described fpga chip respectively with multimode fibre delivery header and and many
Mode fiber receives head and connects, and described fpga chip is connected with ept terminal,
Described fpga chip includes irig-b decoder module, phase bits comparison module, temporal information conversion check module, delay compensation mould
Block, running status module and uart module and an i/o interface, the 2nd i/o interface, the 3rd i/o interface, the 4th i/o interface,
5th i/o interface and the 6th i/o interface, described multimode fibre delivery header passes through the 3rd i/o interface and irig-b decoder module connects
Connect, described irig-b decoder module is connected with phase bits comparison module and temporal information conversion check module respectively, described phase bit comparison
Module passes through the 2nd i/o interface and the bus of input 1pps connects, and described temporal information conversion check module passes through the 4th i/o interface
Connect with the bus of input time information, described delay compensation module passes through an i/o interface and the bus of input irig-b code
Connect, described delay compensation module is connected with the 6th i/o interface, and described phase bits comparison module and temporal information conversion check module are divided
It is not connected with running status module, described running status module and uart module connect, and described uart module is connect by the 5th i/o
Mouth is connected with ept terminal.
2. according to claim 1 have the irig-b code module returned to school it is characterised in that also including power module, described
Power module is connected with fpga chip and multimode fibre head respectively.
3. according to claim 2 have the irig-b code module returned to school it is characterised in that described fpga chip, multimode light
Fine head and power module are arranged on module body, and described module body offers installing hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620619389.2U CN205921597U (en) | 2016-06-21 | 2016-06-21 | Is there IRIG who returns to school B sign indicating number module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620619389.2U CN205921597U (en) | 2016-06-21 | 2016-06-21 | Is there IRIG who returns to school B sign indicating number module |
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| CN201620619389.2U Active CN205921597U (en) | 2016-06-21 | 2016-06-21 | Is there IRIG who returns to school B sign indicating number module |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994908A (en) * | 2017-11-22 | 2018-05-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method for improving B timing code decoding performances |
-
2016
- 2016-06-21 CN CN201620619389.2U patent/CN205921597U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107994908A (en) * | 2017-11-22 | 2018-05-04 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method for improving B timing code decoding performances |
| CN107994908B (en) * | 2017-11-22 | 2021-07-30 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | Method for improving B time code decoding performance |
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