CN205920296U - Array substrate and contain its display panel - Google Patents
Array substrate and contain its display panel Download PDFInfo
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- CN205920296U CN205920296U CN201620792144.XU CN201620792144U CN205920296U CN 205920296 U CN205920296 U CN 205920296U CN 201620792144 U CN201620792144 U CN 201620792144U CN 205920296 U CN205920296 U CN 205920296U
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Abstract
The application discloses array substrate and contain its display panel, array substrate include display area and the non - display area who surrounds display area, array substrate includes the base plate, sets up the first insulation layer on the base plate, non - display area is including a border area territory and the 2nd border area territory of intercommunication, wherein, the first insulation layer is provided with first logical groove in a border area territory, and the first insulation layer is provided with the second in the 2nd border area territory and leads to the groove, and first logical groove leads to the groove intercommunication with the second, the lateral wall and the diapire in first logical groove are first contained angle, and the lateral wall that the second leads to the groove is the second contained angle with the diapire, and the angle of first contained angle is not less than the angle of second contained angle, array substrate is still including setting up the first metal layer in a border area territory, including many barss line in the first metal layer. The scheme of this application embodiment had both realized blocking the route that display area was invaded to external steam, can improve when the form signal line exposure failure or sculpture failure again and the signal line short circuit that arouses.
Description
Technical field
The disclosure relates generally to Display Technique and in particular to touch-control Display Technique, more particularly, to a kind of array base palte and bag
Display floater containing it.
Background technology
The existing touch-control display panel from appearance embedded touch structure, its display signal and touching signals are by same integrated
Circuit evolving.Fig. 1 shows the existing schematic top plan view from the array base palte of display floater holding embedded touch structure.As figure
Shown in 1, array base palte 100 includes viewing area aa, the non-display area 11 being located at around the aa of viewing area and is located at non-display area 11
Integrated circuit ic.
Lead-out area s1 of the data wire that integrated circuit ic is connected with the drain/source of viewing area aa and integrated circuit ic with aobvious
Show that lead-out area s2 of the touching signals line that the touch control electrode in area connects has overlapping region.Wherein, data wire is used for display surface
The drain/source of plate conveys the display signal that integrated circuit produces.Touching signals line is used for the touch control electrode conveying to display floater
Touch-control drive signal.In order to prevent short circuit between data wire and touching signals line, data wire and the setting of touching signals line different layers.
Simultaneously as different layers setting data wire and touching signals line between have insulating barrier, therefore, different layers setting data wire and
Touching signals line easily forms coupled capacitor.And coupled capacitor can increase the load of display floater.In order to reduce holding wire and touch
Coupled capacitor between control holding wire, can arrange thicker organic film, touch-control between data wire and touching signals line
Holding wire is arranged on the top of organic film.
In addition, entering viewing area aa to block steam, can have to above-mentioned in the non-display area 11 of array base palte 100
Machine film layer carries out grooving.In prior art, for preventing touching signals line from causing touch-control to believe due to exposing unsuccessfully or etching unsuccessfully
Number line short circuit, generally carries out grooving to the organic film in the non-display area not including touching signals line, and to including touch-control
Organic film part not grooving in the non-display area of holding wire.In Fig. 1,110 is the non-display area not including touching signals line
The grooving of the organic film in domain is in the projection of array base palte.But, because the corresponding organic film of touching signals line does not dig
Groove, as shown in figure 1, steam 12 enters the viewing area aa of array base palte 100 easily by organic film, causes including this array base
The touch-control display panel less reliable of plate.
Utility model content
In view of drawbacks described above of the prior art or deficiency are it is desirable to provide a kind of array base palte and the display surface comprising it
Plate is it is intended to solve at least one technical problem present in prior art.
The application one side provides a kind of array base palte, including the non-display area of viewing area and encirclement viewing area
Domain；Array base palte includes substrate, is arranged at the first insulating barrier on substrate；Non-display area includes the first rim area connecting
Domain and the second frame region；Wherein, the first insulating barrier is provided with the first groove in the first frame region, and the first insulating barrier is second
Frame region is provided with the second groove, and the first groove is connected with the second groove；The side wall of the first groove and diapire are in the first angle,
The side wall of the second groove and diapire are in the second angle, and the angle of the first angle is not less than the angle of the second angle；Array base palte is also
Including the first metal layer being arranged on the first frame region, the first metal layer includes many signal line.
The application second aspect provides a kind of display floater, and display floater includes above-mentioned array base palte.
The scheme that the embodiment of the present application provides, is provided with the of touching signals line by the non-display area in array base palte
First groove is set in the organic film of one frame region, and the side wall of the wherein first groove and diapire angle are not less than other
Angle between the side wall of the second groove in the organic film in partial non-display area and diapire, had both achieved blocking-up outer
Boundary's steam invades the path of viewing area by organic film, can improve again and expose when forming the photoetching process of touching signals line
Light fails or etches the unsuccessfully touching signals line short circuit causing.
Brief description
By reading the detailed description that non-limiting example is made made with reference to the following drawings, other of the application
Feature, objects and advantages will become more apparent upon:
Fig. 1 show viewing area in existing array base palte, non-display area and be located at non-display area fluting and
The relative position relation of integrated circuit；
Fig. 2 shows the schematic top plan view of the application array base palte；
Fig. 3 shows the schematic cross-section of the first frame region of array base palte shown in Fig. 2 along cc ' direction；
Fig. 4 shows the enlarged diagram of the first groove shown in Fig. 3；
Fig. 5 shows the schematic cross-section of the second frame region of array base palte shown in Fig. 2 along dd ' direction；
Fig. 6 shows the enlarged diagram of the second groove shown in Fig. 5；
Fig. 7 shows the schematic cross-section of the first frame region of array base palte shown in Fig. 2 along ee ' direction；
Fig. 8 shows the schematic top plan view of the viewing area aa of the application array base palte；
Fig. 9 shows the structural representation of the application display floater.
Specific embodiment
With reference to the accompanying drawings and examples the application is described in further detail.It is understood that this place is retouched
The specific embodiment stated is used only for explaining relevant utility model, rather than the restriction to this utility model.Further need exist for explanation
, for the ease of description, in accompanying drawing, illustrate only the part related to utility model.
It should be noted that in the case of not conflicting, the embodiment in the application and the feature in embodiment can phases
Mutually combine.To describe the application below with reference to the accompanying drawings and in conjunction with the embodiments in detail.
Refer to Fig. 2, Fig. 2 shows the schematic top plan view of the application array base palte.As shown in Fig. 2 array base palte 200 wraps
Include the non-display area around viewing area aa and viewing area aa that is to say, that non-display area surrounds viewing area aa.Non-
Viewing area can include the first frame region 21 and the second frame region.Wherein, the first frame region 21 and the second rim area
Domain connection collectively forms non-display area.
As shown in Fig. 2 the first frame region 21 is arranged on the side of viewing area aa, the second frame region and the first frame
Non-display area outside region 21 formation viewing area aa will be that is to say, that the first frame region 21 and the second frame region will show
Show that region aa surrounds.
In some optional implementations of the present embodiment, viewing area aa is rectangle, and the second frame region includes arranging
In the first area 221 of the first frame region 21 offside, it is arranged at the second area 222 and of the first frame region 21 sides adjacent
Three regions 223.
It is alternatively possible in the first frame region 21 arrange integrated circuit ic, integrated circuit ic be used for display when to
Data wire provides display signal, and integrated circuit ic is additionally operable to, in touch-control, provide touch-control drive signal and receive touch control detection
Signal.
In the present embodiment, it is formed with fluting in the non-display area of array base palte 200.Fluting inclusion is formed at the first side
The first groove in frame region 21 and the second groove being formed in the second frame region.In Fig. 2 211 and 224 are respectively the
One groove and the second groove are to the orthographic projection of array base palte 200 place plane.
In conjunction with Fig. 3 and Fig. 5, Fig. 3 shows that the first frame region of array base palte shown in Fig. 2 is shown along the section in cc ' direction
It is intended to；Fig. 5 shows the schematic cross-section of the second frame region of array base palte shown in Fig. 2 along dd ' direction；As Fig. 3, Fig. 5 institute
Show, array base palte include substrate 201, be arranged at second metal layer 202 on substrate 201, setting and second metal layer 202 it
On the second insulating barrier 203, be arranged on the first insulating barrier 204 on the second insulating barrier 203.As shown in figure 3, with the first frame
Region corresponding array base palte region also includes being arranged on the first metal layer 205 on the first insulating barrier 204.May be appreciated
It is to be further typically provided with one layer of insulating barrier to the first metal layer 205 with protective effect on the first metal layer 205.
As shown in Figure 3 and Figure 5, it is provided with the first groove 211 corresponding to the first frame region in the first insulating barrier 204
With the second groove 224 corresponding to the second frame region.Fig. 4 shows the enlarged diagram of the first groove shown in Fig. 3.As figure
Shown in 4, the first groove 211 includes a two side wall k2 and k2 ' and diapire k1, wherein side wall k2 and k2 ' respectively with diapire k1
Between angle equal.Assume that the angle between side wall k2 ' and diapire k1 is the first angle t1.
As shown in fig. 6, it illustrates the enlarged diagram of the second groove shown in Fig. 5.In figure 6, the second groove 224 includes
A two side wall j2 and j2 ' and diapire j1.The angle between diapire j1 is equal respectively for wherein side wall j2 and j2 '.Assume
Angle between side wall j2 ' and diapire j1 is the second angle t2.
In conjunction with Fig. 3 to Fig. 6, the first angle t1 is less, namely the gradient (slope of the side wall k2 and side wall k2 ' of the first groove 211
Degree refers to formed acute angle between side wall and diapire place plane) bigger.When the first angle t1 is smaller, namely the first groove
When the gradient of 211 side wall k2 and k2 ' is larger, when the first insulating barrier forms the first metal layer, in above-mentioned the first metal layer
On when forming holding wire using existing photoetching process, due to side wall k2, k2 ' intersection and the neighbouring metal with diapire k1 respectively
Pile up cause under-exposure or expose unsuccessfully and the bad incidence rate that causes holding wire short-circuit is higher.For example little in the first angle t1
When 150 °, namely when the gradient of side wall k2 and k2 ' of the first groove 211 is more than 30 °, the holding wire causing for above-mentioned reasons
The bad incidence rate of short circuit is far above 30%.The yield requirement of batch production display floater cannot be met.When the first angle t1 gets over
Greatly, namely the gradient of side wall k2 and k2 ' of the first groove 211 gets over hour, form the first metal layer on the first insulating barrier
In technical process, in the first groove 211 side wall k2, k2 ' respectively with the intersection of diapire k1 and near be less susceptible to produce metal
Pile up.
In the present embodiment, angle the first angle t1 between the side wall k2 of the first groove 211 and diapire k1 can be set
It is set to not less than angle the second angle t2 between the side wall j2 and diapire j1 of the second groove 224.That is the first angle t1
The second angle t2 can be more than.When the first angle t1 is more than the second angle t2, the gradient of the first groove 211 side wall k2 and k2 '
The gradient than the second groove 224 side wall j2 and j2 ' relatively relaxes, as such, it is possible to improve form the first gold medal on the first insulating barrier
When belonging to layer, in the first groove 211 side wall k2, k2 ' respectively with the intersection of diapire k1 and near metal accumulation phenomenon, thus dropping
Low follow-up use exposure technology is formed during holding wire on the first metal layer because metal accumulation causes under-exposure or exposure to lose
The incidence rate of the holding wire short circuit losing and causing.
In addition, when the first angle t1 is between 155 °～180 °, being caused due to the metal accumulation being formed during metal level
Post-exposure is not enough or exposes unsuccessfully causes the bad incidence rate of holding wire short circuit within the scope of acceptable.When first
When angle t1 is equal to 155 °, namely when the gradient of side wall k2 and k2 ' of the first groove 211 is equal to 25 °, in existing photoetching process bar
Under part, the incidence rate of the holding wire short circuit causing for above-mentioned reasons is about 2% about；When the first angle is equal to 165 °,
When i.e. the gradient of side wall k2 and k2 ' of the first groove 211 is equal to 15 °, under the conditions of existing photoetching process, draw for above-mentioned reasons
The incidence rate of the holding wire short circuit rising is about 0.01%.That is, when the first angle t1 meets 155 °≤t1 < 180 °,
When i.e. the gradient of side wall k2 and k2 ' of the first groove 211 is between 0 °～25 °, can reasonable solve due to forming metal
Metal accumulation during layer and cause the short-circuit problem of the holding wire that under-exposure or expose unsuccessfully causes.
It is understood that can also be by the second of the side wall j2 and j2 ' time of the second groove 224 shown in Fig. 5 and Fig. 6
Angle t2 is arranged to equal with the first angle t1, namely the second angle t2 can be arranged between 155 °≤t1 < 180 °.
In some optional implementations of the present embodiment, the A/F k4 of the first groove 211 is more than or equal to second
The A/F j4 of groove 224.Wherein A/F be groove orthographic projection from two side walls to array base palte place plane it
Between ultimate range.Assume that the width of diapire of the first groove 211 is equal with the width of the diapire of the second groove 224, when first
When the A/F k4 of groove 211 is more than the A/F j4 of the second groove 224, the gradient of the first groove 211 side wall k2 and k2 '
The gradient than the second groove 224 side wall j2 and j2 ' relatively relaxes, as such, it is possible to improve form the first gold medal on the first insulating barrier
When belonging to layer, in the first groove 211 side wall k2, k2 ' respectively with the intersection of diapire k1 and near metal accumulation phenomenon, Jin Ergai
Deal with problems arising from an accident to continue and formed on the first metal layer during holding wire because metal accumulation causes under-exposure or exposure to lose using exposure technology
The holding wire poor short circuit losing and causing.
In some optional implementations of the present embodiment, as shown in Figure 3 and Figure 5, the diapire k1 of the first groove 211 and
The surface that the diapire j1 of the second groove 224 is contacted with the first insulating barrier 204 with the second insulating barrier 203 is located at same level.?
That is, the diapire of the first groove 211 and the second groove 224 is the surface near the first insulating barrier 204 for second insulating barrier 203
A part.Namely first groove 211 and the second groove 224 depth be the first insulating barrier 204 thickness.In the present embodiment one
A bit in optional implementation, the first insulating barrier 204 material is organic compound that is to say, that the first insulating barrier 204 is organic membrane
Layer.First insulating barrier 204 is set to organic film, can effectively reduce between the first metal layer 205 and second metal layer 202
Coupled capacitor.
In some optional implementations of the present embodiment, the material of the second insulating barrier 203 can be inorganic compound, example
As silicon nitride (sinx).That is, the second insulating barrier 203 is inorganic film.The structure of inorganic compound is dense, water
Vapour is easily detected by.So, due to arranging the first groove 211 and the second groove 224 in the first insulating barrier 204, steam is by outer
Boundary enters into inorganic film through the first groove 211 and the second groove 224 after invading part organic film 204, and steam is further
The path invading viewing area is cut off by the second insulating barrier 203, improves the reliability of the display floater comprising this array base palte
Property.
In the present embodiment, as shown in fig. 7, it illustrates the first frame region cutting along ee ' of array base palte shown in Fig. 2
Face schematic diagram, in the figure 7, is formed with many signal line 23 in the first metal layer 205.Holding wire 23 shown in the figure 7 and
The diapire contact of one groove；In addition, holding wire can also be with the sidewall contact of the first groove that is to say, that holding wire be and
Two insulating barrier contacts, but contact with the organic film forming the first logical groove sidewall.Every signal line 23 is by the first frame region
Extend to viewing area.
In some optional implementations of the present embodiment, as shown in Figure 3 and Figure 5, the width j3 of the second groove 224 diapire
Less than or equal to the first groove 211 diapire width k3 that is to say, that the width k3 of diapire of the first groove 211 can be big
Width in the second groove 224 diapire j3.When the width k3 of the first groove 211 diapire is set greater than the second groove 224 bottom
During the width j3 of wall, the distance between two side walls of the first groove 211 increase, and so, form the on the first insulating barrier 204
During one metal level 205, the first groove 211 two side walls respectively with the intersection of diapire and near produced stacks of metal layers
The long-pending probability to the relatively under-exposure of thick metal layers or exposure failure being not easy to overlap together, reducing follow-up photoetching process.
In addition, the width of the diapire of groove is wider, the effect that steam is blocked is bigger.The width k3 of the diapire of the first groove 211 sets
Putting can be according to considering the needs of the blocking-up to steam, photoetching process condition and to the first metal layer 205 and second
Between metal level 202, the requirement of coupled capacitor is being configured.Optional it is also possible to width j3 by the second groove 224 diapire
It is arranged to identical with the width k3 of the diapire of the first groove 211.Width j3 and the first groove 211 when the second groove 224 diapire
Diapire width k3 identical when, it is possible to use identical process conditions form the first groove 211 and the second groove 224, simplify
The technique forming the first groove 211 and second groove 224.
Please continue to refer to Fig. 8, it illustrates the schematic top plan view of the viewing area aa of the application array base palte.As shown in figure 8,
It is provided with multiple touch control electrode 24 in the viewing area aa of array base palte, plurality of touch control electrode 24 is arranged in array.Fig. 7
Shown in the first metal layer 205 in holding wire 23 can be touching signals line.Each touch control electrode 24 is corresponding thereto
Touching signals line 23 extend to viewing area aa one end electrical connection.The other end of touching signals line 23 be arranged on the first side
The integrated circuit electrical connection in frame region.Multiple touch control electrode can be touch control electrode in the touch-control stage, on the image display stage
State multiple touch control electrode and can be multiplexed with public electrode.
In some optional implementations of the present embodiment, as shown in fig. 7, being arranged on the second insulating barrier 203 and substrate 201
Between second metal layer 202 in be formed with a plurality of data lines 22, every data line 22 and the collection being arranged on the first frame region
Circuit is become to connect to receive the display signal of integrated circuit transmission.
It is understood that the application array base palte also includes some known features, for example, many on formation array base palte
Individual pixel cell, in order to unnecessarily obscure embodiment of the disclosure, structure known to these is not given in the present embodiment
Bright.
The application also provides a kind of display floater, refer to Fig. 9, it illustrates the structural representation of the application display floater
Figure.As shown in figure 9, the application display floater includes above-mentioned array base palte 200, it is oppositely arranged with above-mentioned array base palte 200
Color membrane substrates 300, are arranged on the liquid crystal layer l between array base palte 200 and color membrane substrates 300 and are arranged on array base palte and coloured silk
Spacer p between ilm substrate.
Above description is only the preferred embodiment of the application and the explanation to institute's application technology principle.People in the art
Member is it should be appreciated that involved utility model scope is however it is not limited to the particular combination of above-mentioned technical characteristic in the application
Technical scheme, also should cover simultaneously without departing from described utility model design in the case of, by above-mentioned technical characteristic or its be equal to
Other technical schemes that feature carries out combination in any and formed.Such as features described above is had with (but not limited to) disclosed herein
The technical scheme that the technical characteristic having similar functions is replaced mutually and formed.
Claims (12)
1. a kind of array base palte is it is characterised in that described array base palte includes viewing area and surrounds the non-of described viewing area
Viewing area；
Described array base palte includes substrate, is arranged at the first insulating barrier on described substrate；
Described non-display area includes the first frame region and the second frame region connecting；
Wherein, described first insulating barrier is provided with the first groove in described first frame region, and described first insulating barrier is described
Second frame region is provided with the second groove, and described first groove is connected with described second groove；
The side wall of described first groove and diapire are in the first angle, and the side wall of described second groove and diapire are in the second angle, institute
The angle stating the first angle is not less than the angle of described second angle；
Described array base palte also includes being arranged on the first metal layer of described first frame region, and described the first metal layer includes
Many signal line.
2. array base palte according to claim 1 is it is characterised in that described array base palte also includes integrated circuit, described
Integrated circuit is arranged on described first frame region；
A plurality of described holding wire is electrically connected with described integrated circuit.
3. array base palte according to claim 2 is it is characterised in that described first frame region is arranged on described viewing area
The side in domain, described second frame region include being arranged at described first frame region offside first area, be arranged at described
The second area of the first frame region sides adjacent and the 3rd region.
4. array base palte according to claim 3, it is characterised in that the angle of described first angle is more than 155 °, is less than
180°.
5. array base palte according to claim 3 is it is characterised in that the width of described second groove diapire is less than or waits
Width in described first groove diapire.
6. array base palte according to claim 3 is it is characterised in that the A/F of described first groove is more than or waits
A/F in described second groove.
7. array base palte according to claim 1 is it is characterised in that described the first metal layer is arranged on described first insulation
On layer, described holding wire is contacted with the diapire of described first groove or the side wall of described first groove.
8. array base palte according to claim 2 is it is characterised in that described holding wire is touching signals line；
The described viewing area of described array base palte includes multiple touch control electrode of array arrangement, each described touch control electrode and its phase
One end electrical connection of corresponding described touching signals line；
The other end of described touching signals line is electrically connected with described integrated circuit；
Wherein, the plurality of touch control electrode is multiplexed with public electrode.
9. array base palte according to claim 2 it is characterised in that
Described array base palte also includes the second insulating barrier being arranged between described substrate and described first insulating barrier；And
It is arranged on the second metal layer between described substrate and described second insulating barrier；
It is formed with a plurality of data lines in described second metal layer；
Described data wire is electrically connected with described integrated circuit.
10. array base palte according to claim 1 is it is characterised in that described first insulating layer material is organic compound.
11. array base paltes according to claim 9 are it is characterised in that described second insulating layer material is inorganic compound.
A kind of 12. display floaters are it is characterised in that described display floater includes the array described in claim 1-11 any one
Substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620792144.XU CN205920296U (en) | 2016-07-26 | 2016-07-26 | Array substrate and contain its display panel |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620792144.XU CN205920296U (en) | 2016-07-26 | 2016-07-26 | Array substrate and contain its display panel |
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| CN205920296U true CN205920296U (en) | 2017-02-01 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113990904A (en) * | 2021-10-26 | 2022-01-28 | 昆山国显光电有限公司 | Display panel and display device |
| CN115236909A (en) * | 2022-08-08 | 2022-10-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| WO2023141761A1 (en) * | 2022-01-25 | 2023-08-03 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor and display apparatus |
-
2016
- 2016-07-26 CN CN201620792144.XU patent/CN205920296U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113990904A (en) * | 2021-10-26 | 2022-01-28 | 昆山国显光电有限公司 | Display panel and display device |
| WO2023141761A1 (en) * | 2022-01-25 | 2023-08-03 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method therefor and display apparatus |
| CN115236909A (en) * | 2022-08-08 | 2022-10-25 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| CN115236909B (en) * | 2022-08-08 | 2023-10-13 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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