CN205883195U

CN205883195U - Clock signal's level shift amplitude control circuit

Info

Publication number: CN205883195U
Application number: CN201620837985.8U
Authority: CN
Inventors: 蒋奇; 谭昭禹
Original assignee: Chengdu Bosiwei Technology Co Ltd
Current assignee: Chengdu Bosiwei Technology Co Ltd
Priority date: 2016-08-04
Filing date: 2016-08-04
Publication date: 2017-01-11
Anticipated expiration: 2026-08-04

Abstract

The utility model discloses a clock signal's level shift amplitude control circuit, including MOS switch circuit and operating circuit, the operating circuit include that one or more realizes level shift and amplitude adjustment's load driving circuit, MOS switch circuit is connected with every load driving circuit respectively. The utility model provides a clock signal's level shift amplitude control circuit, the operating circuit of managing MOS switch circuit and drive load separates for when realizing level shift, also can avoid in the load equivalent capacitance to MOS pipe switch circuit's influence, whole clock signal's level shift circuit work is more stable, and simultaneously, this application can be counterpointed the range of lagging level and controlled, makes it be in zero to between the maximum value.

Description

A kind of level shift amplitude control circuit of clock signal

Technical field

This utility model relates to the level shift amplitude control circuit of a kind of clock signal.

Background technology

In many power supplys analog signal processing circuit, often need clock control signal is carried out level shift, right to realize The control of the analogue signal of different common mode electrical levels, as it is shown in figure 1, in conventional level displacement circuit, utilize two electric capacity electricity Flat displacement-capacitance C10, C20 and two metal-oxide-semiconductors M10, M20, constitute level displacement circuit in conjunction with phase inverter, by one end of load It is directly connected to the common port of electric capacity C20 Yu M20 drain electrode, the other end ground connection of load, realizes the displacement of level, but, negative Carry the equivalent capacity of Cload bigger time, can exist and carry out the situation of dividing potential drop with electric capacity C20, cause electric capacity C20 Yu M20 to drain Common port level magnitudes reduces, and M1 pipe turn-on effect is bad, conducting endless sentiments condition occurs so that circuit malfunction under serious conditions； Meanwhile, level magnitudes cannot be controlled after this circuit level displacement so that it is be in zero between maximum.

Utility model content

The purpose of this utility model is to overcome the deficiencies in the prior art, it is provided that the level shift amplitude of a kind of clock signal Control circuit.

The purpose of this utility model is achieved through the following technical solutions: the level shift amplitude of a kind of clock signal Control circuit, including MOS switch circuit and operating circuit, described operating circuit include one or more realize level shift and The load driving circuits that amplitude adjusts；Described MOS switch circuit is connected with each load driving circuits respectively；

Described MOS switch circuit includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first electric capacity, the second electric capacity and phase inverter；The The source electrode of one metal-oxide-semiconductor and the second metal-oxide-semiconductor is all connected with the first level terminal；The grid of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor are even Connecing, the drain electrode of the first metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor；The drain electrode of the first metal-oxide-semiconductor is believed with clock also by the first electric capacity Number end connect；The input of described phase inverter is connected with clock signal terminal, and the outfan of phase inverter passes through the second electric capacity and second The drain electrode of metal-oxide-semiconductor connects；

Described load driving circuits includes the 3rd metal-oxide-semiconductor, the 3rd electric capacity, the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor；Described 3rd The source electrode of metal-oxide-semiconductor is connected with drive level end, and the grid of the 3rd metal-oxide-semiconductor and the drain electrode of the first metal-oxide-semiconductor connect, the 3rd metal-oxide-semiconductor Drain electrode is connected with the outfan of phase inverter by the 3rd electric capacity；The drain electrode of described 3rd metal-oxide-semiconductor is also with the source electrode of the 4th metal-oxide-semiconductor even Connecing, the grid of the 4th metal-oxide-semiconductor connects break-make control level end；The drain electrode of the 4th metal-oxide-semiconductor is connected with the drain electrode of the 5th metal-oxide-semiconductor, the The source ground of five metal-oxide-semiconductors, the grid of the 5th metal-oxide-semiconductor connects clock signal terminal.

In described load driving circuits, after the common port output displacement by the 4th metal-oxide-semiconductor drain electrode and the drain electrode of the 5th metal-oxide-semiconductor Level, for loaded work piece；The common port of the 4th metal-oxide-semiconductor drain electrode and the drain electrode of the 5th metal-oxide-semiconductor is connected with the first end of load, load Second end ground connection.

In described operating circuit, each load driving circuits is identical.

In described operating circuit, each load driving circuits connects different drive level ends.

The beneficial effects of the utility model are: the application is by metal-oxide-semiconductor on-off circuit and drives the operating circuit of load to carry out Separate so that while realizing level shift, it is also possible to avoid the equivalent capacity impact on metal-oxide-semiconductor on-off circuit in load, The level displacement circuit work of whole clock signal is more stable, and meanwhile, the amplitude of level after displacement can be carried out by the application Control so that it is be in zero between maximum.

Accompanying drawing explanation

Fig. 1 is the schematic diagram of conventional level shift circuit；

Fig. 2 is the circuit theory diagrams of this utility model embodiment one；

Fig. 3 is the level shift design sketch of this utility model embodiment one；

Fig. 4 is the circuit theory diagrams of this utility model embodiment two；

Fig. 5 is the level shift design sketch of this utility model embodiment two.

Detailed description of the invention

The technical solution of the utility model is described in further detail below in conjunction with the accompanying drawings, but protection domain of the present utility model It is not limited to the following stated.

The level shift amplitude control circuit of a kind of clock signal, including MOS switch circuit and operating circuit, described work One or more load driving circuits realizing level shift and amplitude adjustment is included as circuit；Described MOS switch circuit is respectively It is connected with each load driving circuits；

Described MOS switch circuit include the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the first electric capacity C1, the second electric capacity C2 and Phase inverter F；The source electrode of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is all connected with the first level terminal V1；The grid of the first metal-oxide-semiconductor M1 Drain electrode with the second metal-oxide-semiconductor M2 is connected, and the drain electrode of the first metal-oxide-semiconductor M1 is connected with the grid of the second metal-oxide-semiconductor M2；First metal-oxide-semiconductor M1 Drain electrode be connected with clock signal terminal CLK also by the first electric capacity C1；The input of described phase inverter F and clock signal terminal CLK Connecting, the outfan of phase inverter F is connected by the drain electrode of the second electric capacity C2 and the second metal-oxide-semiconductor M2；

Described load driving circuits includes the 3rd metal-oxide-semiconductor M3, the 3rd electric capacity C3, the 4th metal-oxide-semiconductor M4 and the 5th metal-oxide-semiconductor M5； The source electrode of described 3rd metal-oxide-semiconductor M3 is connected with drive level end, and the grid of the 3rd metal-oxide-semiconductor M3 and the drain electrode of the first metal-oxide-semiconductor M1 are even Connecing, the drain electrode of the 3rd metal-oxide-semiconductor M1 is connected by the outfan of the 3rd electric capacity C3 and phase inverter F；The drain electrode of described 3rd metal-oxide-semiconductor M3 The also source electrode with the 4th metal-oxide-semiconductor M4 is connected, and the grid of the 4th metal-oxide-semiconductor M4 connects break-make control level end；The leakage of the 4th metal-oxide-semiconductor M4 Pole is connected with the drain electrode of the 5th metal-oxide-semiconductor M5, the source ground of the 5th metal-oxide-semiconductor M5, and the grid of the 5th metal-oxide-semiconductor M5 connects clock signal End CLK.

In described load driving circuits, by the 4th metal-oxide-semiconductor M4 drain electrode and the common port output displacement of the 5th metal-oxide-semiconductor M5 drain electrode After level, for loaded work piece；The common port of the 4th metal-oxide-semiconductor M4 drain electrode and the 5th metal-oxide-semiconductor M5 drain electrode is with the first end of load even Connect, the second end ground connection of load.

In embodiments herein one, when described operating circuit comprises a load driving circuits, whole clock is believed Number level shift amplitude control circuit as in figure 2 it is shown,

As it is shown on figure 3, in this embodiment, clock signal terminal CLK input clock signal level is 0 ~ VDD1, phase inverter Power supply is VDD1, and phase inverter output level is 0 ~ VDD1:

By level shift electric capacity C1, C2 and M1, M2 constitutes a shift circuit intersected, clock signal be displaced to V1 ~ VDD1+V1 voltage location, signal is S1, S2, signal S1 with drive M3, it is achieved the displacement of S3 signal, S3 signal be also displaced to V2 ~ VDD1+V2 voltage location.

Clock signal is 0, and phase inverter is output as 1, and electric capacity C1 terminal voltage s1 is that V1, M2/M3 switch off, and C2 terminal voltage is VDD1+V1, M1 turn on, and C1 is charged to V1, C3 terminal voltage and exports load C load, and S4 end output signal is V2+VDD1；Time Clock signal is 1, and phase inverter is output as 0, and C1 terminal voltage is VDD1+V1, M2/M3 switch conduction, and electric capacity C2/C3 is charged to V1, electricity Holding C3 and be charged to V2, M4 shutoff, M5 opens, and S4 end is output as 0；

Therefore the S4 of output can be displaced to 0 ~ V2+VDD1.

Electric capacity C1, the size driving M2/M3, M2/M3 is the least, and therefore the value of C1 is the least, and concrete value design meets Condition C 1 > ((VT+V2) * CS1)/(VDD1+V1-VT-V2), here VT is the threshold voltage of M2/M3, and CS1 is to include M1's Cds(source drain capacitance) electric capacity, the gate capacitance of M2/M3, also have parasitic capacitance after domain, the value of C1 also needs to the bigger of setting, with Time be necessary to ensure that V1-V2 < VT, when M3 gate voltage is V1, M3 does not haves conducting situation.

Electric capacity C2, it is desirable to driving M1, therefore C2 needs to meet condition C 2 > (VT* (CS2))/(VDD1-VT), here VT For the threshold voltage of M13, CS1 is the gate electric capacity including M1, the Cds electric capacity of M2, also has parasitic capacitance after domain, and the value of C2 is also Need the bigger of setting.

As it is shown on figure 3, for electric capacity C3, in theory, in the case of reasonably, S3 signal is also displaced to V2 ~ VDD1+V2 electricity Pressure position, corresponding S4 signal can also be displaced to 0 ~ VDD1+V2 position,

But it practice, electric capacity C3, it is desirable to drive arranging of Cload, C3 to need to meet wanting of Load clock signal amplitude Ask, C3 (Vout* (CS3+Cload))/(VDD1-Vout), CS3 electric capacity includes the Cds electric capacity of M3/M4/M5, the most permissible Output amplitude peak demand is realized by arranging of C3 of regulation, such as, scalable C3 size, limit the maximum displacement of S4 signal Level.

MOS switch M1/M2/M3, is here required to meet the compensation requirement of charge leakage, the least during charge leakage, because of It is the least that the size of this M1/M2/M3 can be done.

As shown in Figure 4, in embodiments herein two, when operating circuit includes multiple load driving circuits, formed Many level displacement circuits；Each load driving circuits is identical, and meanwhile, each load driving circuits connects varying level Drive level end.

Different load driving circuits, is controlled by drive level end, therefore obtains different level shift results, right to supply The loaded work piece answered, level shift result as it is shown in figure 5,

It can be seen that one of them load driving circuits connects drive level end level when being V2, level shift to 0 ~ VDD1+ V2, obtains signal s4 and drives respective load work；Another load driving circuits connects drive level end when being Vn, and level shift is arrived 0 ~ VDD1+Vn, obtains signal sn1, drives corresponding loaded work piece.

Claims

1. the level shift amplitude control circuit of a clock signal, it is characterised in that: include MOS switch circuit and work electricity Road, described operating circuit includes one or more load driving circuits realizing level shift and amplitude adjustment；Described MOS opens Close circuit to be connected with each load driving circuits respectively；

Described MOS switch circuit includes the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the first electric capacity, the second electric capacity and phase inverter；First The source electrode of metal-oxide-semiconductor and the second metal-oxide-semiconductor is all connected with the first level terminal；The grid of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor are even Connecing, the drain electrode of the first metal-oxide-semiconductor is connected with the grid of the second metal-oxide-semiconductor；The drain electrode of the first metal-oxide-semiconductor is believed with clock also by the first electric capacity Number end connect；The input of described phase inverter is connected with clock signal terminal, and the outfan of phase inverter passes through the second electric capacity and second The drain electrode of metal-oxide-semiconductor connects；

Described load driving circuits includes the 3rd metal-oxide-semiconductor, the 3rd electric capacity, the 4th metal-oxide-semiconductor and the 5th metal-oxide-semiconductor；Described 3rd metal-oxide-semiconductor Source electrode be connected with drive level end, the drain electrode of the grid of the 3rd metal-oxide-semiconductor and the first metal-oxide-semiconductor connects, and the drain electrode of the 3rd metal-oxide-semiconductor is led to Cross the 3rd electric capacity to be connected with the outfan of phase inverter；The drain electrode of described 3rd metal-oxide-semiconductor also source electrode with the 4th metal-oxide-semiconductor is connected, and The grid of four metal-oxide-semiconductors connects break-make control level end；The drain electrode of the 4th metal-oxide-semiconductor is connected with the drain electrode of the 5th metal-oxide-semiconductor, the 5th MOS The source ground of pipe, the grid of the 5th metal-oxide-semiconductor connects clock signal terminal.

The level shift amplitude control circuit of a kind of clock signal the most according to claim 1, it is characterised in that: described negative Carry in drive circuit, by the level after the common port output displacement of the 4th metal-oxide-semiconductor drain electrode and the drain electrode of the 5th metal-oxide-semiconductor, for load work Make；The common port of the 4th metal-oxide-semiconductor drain electrode and the drain electrode of the 5th metal-oxide-semiconductor is connected with the first end of load, the second end ground connection of load.

The level shift amplitude control circuit of a kind of clock signal the most according to claim 1, it is characterised in that: described work Making in circuit, each load driving circuits is identical.

The level shift amplitude control circuit of a kind of clock signal the most according to claim 1, it is characterised in that: described work Making in circuit, each load driving circuits connects different drive level ends.