CN205845471U

CN205845471U - A kind of bilateral scanning unit and gate driver circuit

Info

Publication number: CN205845471U
Application number: CN201620819681.9U
Authority: CN
Inventors: 敦栋梁
Original assignee: Tianma Microelectronics Co Ltd; Shanghai AVIC Optoelectronics Co Ltd
Current assignee: Tianma Microelectronics Co Ltd; Shanghai AVIC Optoelectronics Co Ltd
Priority date: 2016-07-29
Filing date: 2016-07-29
Publication date: 2016-12-28
Anticipated expiration: 2026-07-29

Abstract

The utility model discloses a kind of bilateral scanning unit and gate driver circuit, bilateral scanning unit includes first order subelement and second level subelement, bilateral scanning unit can export scanning signal step by step along first order subelement to the direction of second level subelement, scanning signal can also be exported step by step along second level subelement to the direction of first order subelement, and in scanning process, first order subelement and second level subelement cooperate, when making wherein one-level subelement export scanning signal, another grade of subelement does not export scanning signal.The technical scheme that this utility model provides, bilateral scanning unit can export two-stage scan signal step by step, and interact by first order subelement and second level subelement and simplify the structure of bilateral scanning unit, and meet the multifarious demand of gate driver circuit.

Description

A kind of bilateral scanning unit and gate driver circuit

Technical field

This utility model relates to showing scanning technique field, more specifically, relates to a kind of bilateral scanning unit and grid Pole drive circuit.

Background technology

Along with the development of electronic technology, display device has been widely used in each row field and various electronic product, becomes For the part that people's live and work is indispensable, such as TV, mobile phone, computer, personal digital assistant etc..Existing display dress In putting, display device includes gate driver circuit, and gate driver circuit is mainly used in scanning multistage gate line, with by scanning Gate line and the pel array electrically connected with gate line is scanned, and then coordinate All other routes structure to carry out the aobvious of picture Show.Due to the people's multifarious demand to gate driver circuit, therefore gate driver circuit be designed to developer now One of main research tendency.

Utility model content

In view of this, this utility model provides a kind of bilateral scanning unit and gate driver circuit, bilateral scanning unit Two-stage scan signal can be exported step by step, and interact by first order subelement and second level subelement and simplify two-way sweeping Retouch the structure of unit, and meet the multifarious demand of gate driver circuit.

For achieving the above object, the technical scheme that this utility model provides is as follows:

A kind of bilateral scanning unit, described bilateral scanning unit includes first order subelement and second level subelement, wherein, Described first order subelement includes: the first input module, the first pull-up node, the first pull-up control module, the second pull-up control Module, the first pull-down node, the first drop-down control module, the second drop-down control module, the first drop-down generation module, the first output Module and the first outfan；And, described second level subelement includes: the second input module, the second pull-up node, the 3rd pull-up Control module, the 4th pull-up control module, the second pull-down node, the 3rd drop-down control module, the 4th drop-down control module, second Drop-down generation module, the second output module and the second outfan；

Described first input module controls the first voltage end and described first pull-up in response to the first signal controlling end On-state between node and between control tertiary voltage end and described first outfan, and control end in response to second Signal and control the second voltage end and described first pull-up node between and control described tertiary voltage end with described first export On-state between end, wherein, the level of the signal of described first voltage end and the output of the second voltage end is contrary；

Described second input module controls described first voltage end and described second in response to the 3rd signal controlling end The on-state pulled up between node and control between described tertiary voltage end and described second outfan, and in response to the 4th Control end signal and control described second voltage end and described second pull-up node between and control described tertiary voltage end and On-state between described second outfan, wherein, the structure of described first input module and the second input module is identical；

Described first pull-up control module controls described first drop-down joint in response to the signal of described first pull-up node The connection put between described tertiary voltage end and control between described first pull-down node and described first drop-down generation module State；Described second pull-up control module in response to described second pull-up node signal and control described first pull-down node with Between described tertiary voltage end and the on-state that controls between described first pull-down node and described first drop-down generation module；

Described 3rd pull-up control module controls described second drop-down joint in response to the signal of described second pull-up node The connection put between described tertiary voltage end and control between described second pull-down node and described second drop-down generation module State；Described 4th pull-up control module in response to described first pull-up node signal and control described second pull-down node with Between described tertiary voltage end and the on-state that controls between described second pull-down node and described second drop-down generation module, Wherein, described first pull-up control module is identical with the structure of the 3rd pull-up control module, and described second pull-up control module Identical with the structure of the 4th pull-up control module；

Described first drop-down generation module controls described first signal end and described in response to the signal of the first signal end On-state between first pull-down node；

Described second drop-down generation module controls described secondary signal end with described in response to the signal of secondary signal end On-state between second pull-down node, and described first drop-down generation module and the structure phase of the second drop-down generation module With；

Described first drop-down control module controls described first pull-up joint in response to the signal of described first pull-down node The on-state put between described tertiary voltage end and control between described tertiary voltage end and described first outfan；Described Second drop-down control module controls described first pull-up node and the described 3rd in response to the signal of described second pull-down node Between voltage end and the on-state that controls between described tertiary voltage end and described first outfan；

Described 3rd drop-down control module controls described second pull-up joint in response to the signal of described second pull-down node The on-state put between described tertiary voltage end and control between described tertiary voltage end and described second outfan；Described 4th drop-down control module controls described second pull-up node and the described 3rd in response to the signal of described first pull-down node Between voltage end and the on-state that controls between described tertiary voltage end and described second outfan, wherein, described first time Draw control module identical with the structure of the 3rd drop-down control module, and described and drop-down control module and the 4th drop-down control mould The structure of block is identical；

Described first output module controls the first clock signal terminal and institute in response to the signal of described first pull-up node State the on-state between the first outfan, and, described second output module is in response to the signal of described second pull-up node And control the on-state between second clock signal end and described second outfan, wherein, described first clock signal terminal and The signal phase difference of second clock signal end output is 180 degree, and described first output module and the structure of the second output module Identical.

Compared to prior art, the technical scheme that this utility model provides at least has the advantage that

This utility model provides a kind of bilateral scanning unit and gate driver circuit, and bilateral scanning unit includes first Level subelement and second level subelement, bilateral scanning unit can along first order subelement to the direction of second level subelement step by step Output scanning signal, it is also possible to export scanning signal step by step along second level subelement to the direction of first order subelement, and sweeping During retouching, first order subelement and second level subelement cooperate, when making the scanning signal of one-level subelement output wherein, Another grade of subelement does not export scanning signal.The technical scheme that this utility model provides, bilateral scanning unit can export step by step Two-stage scan signal, and interact by first order subelement and second level subelement and simplify the knot of bilateral scanning unit Structure, and meet the multifarious demand of gate driver circuit.

Accompanying drawing explanation

In order to be illustrated more clearly that this utility model embodiment or technical scheme of the prior art, below will be to embodiment Or the required accompanying drawing used is briefly described in description of the prior art, it should be apparent that, the accompanying drawing in describing below is only It is embodiment of the present utility model, for those of ordinary skill in the art, on the premise of not paying creative work, also Other accompanying drawing can be obtained according to the accompanying drawing provided.

The structural representation of a kind of bilateral scanning unit that Fig. 1 provides for the embodiment of the present application；

The structural representation of the another kind of bilateral scanning unit that Fig. 2 provides for the embodiment of the present application；

The sequential chart of a kind of forward scan that Fig. 3 a provides for the embodiment of the present application；

The sequential chart of a kind of reverse scan that Fig. 3 b provides for the embodiment of the present application；

The structural representation of another bilateral scanning unit that Fig. 4 provides for the embodiment of the present application；

The structural representation of another bilateral scanning unit that Fig. 5 provides for the embodiment of the present application；

The structural representation of a kind of gate driver circuit that Fig. 6 provides for the embodiment of the present application.

Detailed description of the invention

Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under making creative work premise The every other embodiment obtained, broadly falls into the scope of this utility model protection.

As described in background, due to the people's multifarious demand to gate driver circuit, therefore raster data model electricity Road be designed to developer's one of main research tendency now.

Based on this, the embodiment of the present application provides a kind of bilateral scanning unit, driving method and gate driver circuit, two-way Scanning element can export two-stage scan signal step by step, and simple by first order subelement and the interaction of second level subelement Change the structure of bilateral scanning unit, and meet the multifarious demand of gate driver circuit.For achieving the above object, the application The technical scheme that embodiment provides is as follows, specifically combines shown in Fig. 1 to Fig. 6, and the technical scheme providing the embodiment of the present application is entered The description that row is detailed.

With reference to shown in Fig. 1, for the structural representation of a kind of bilateral scanning unit that the embodiment of the present application provides, wherein, double Being applied to gate driver circuit to scanning element, described bilateral scanning unit includes:

First order subelement and second level subelement, wherein, described first order subelement includes: the first input module 101, First pull-up node P1, the first pull-up control module 2011, second pull up control module the 2012, first pull-down node Q1, first Drop-down control module 3011, second drop-down control module 3012, first drop-down generation module the 401, first output module 501 and One outfan Gout1；And, described second level subelement includes: the second input module 102, second pulls up node P2, on the 3rd Control module the 2021, the 4th is drawn to pull up control module the 2022, second pull-down node Q2, the 3rd drop-down control module the 3021, the 4th Drop-down control module 3022, second drop-down generation module the 402, second output module 502 and the second outfan Gout2；

Described first input module 101 controls the first voltage end DIR1 and institute in response to the first signal controlling end SET1 The on-state stating between the first pull-up node P1 and control between tertiary voltage end V3 and described first outfan Gout1, with And in response to second control end RESET1 signal and control the second voltage end DIR2 and described first pull-up node P1 between and Control the on-state between described tertiary voltage end V3 and described first outfan Gout1, wherein, described first voltage end The level of the signal of DIR1 and the second voltage end DIR2 output is contrary；

Described second input module 102 controls described first voltage end DIR1 in response to the 3rd signal controlling end SET2 And the described second connection pulling up between node P2 and controlling between described tertiary voltage end V3 and described second outfan Gout2 State, and control described second voltage end DIR2 and described second pull-up joint in response to the 4th signal controlling end RESET2 Between some P2 and the on-state that controls between described tertiary voltage end V3 and described second outfan Gout2, wherein, described the One input module 101 is identical with the structure of the second input module 102；

Described first pull-up control module 2011 controls described first in response to the signal of described first pull-up node P1 Between pull-down node Q1 and described tertiary voltage end V3 and control described first pull-down node Q1 and described first drop-down generation mould On-state between block 401；Described second pull-up control module 2012 is in response to the described second signal pulling up node P2 Control between described first pull-down node Q1 and described tertiary voltage end V3 and control described first pull-down node Q1 and described the On-state between one drop-down generation module 401；

Described 3rd pull-up control module 2021 controls described second in response to the signal of described second pull-up node P2 Between pull-down node Q2 and described tertiary voltage end V3 and control described second pull-down node Q2 and described second drop-down generation mould On-state between block 402；Described 4th pull-up control module 2022 is in response to the described first signal pulling up node P1 Control between described second pull-down node Q2 and described tertiary voltage end V3 and control described second pull-down node Q2 and described the On-state between two drop-down generation modules 402, wherein, described first pull-up control module 2011 and the 3rd pull-up control mould The structure of block 2021 is identical, and described second pull-up control module 2012 is identical with the structure of the 4th pull-up control module 2022；

Described first drop-down generation module 401 controls described first letter in response to the signal of the first signal end Vclock1 Number end Vclock1 and described first pull-down node Q1 between on-state；

Described second drop-down generation module 402 controls described second letter in response to the signal of secondary signal end Vclock2 On-state number between end Vclock2 and described second pull-down node Q2, and described first drop-down generation module 401 and second The structure of drop-down generation module 402 is identical；

Described first drop-down control module 3011 controls described first in response to the signal of described first pull-down node Q1 Between pull-up node P1 and described tertiary voltage end V3 and control described tertiary voltage end V3 and described first outfan Gout1 it Between on-state；Described second drop-down control module 3012 controls described in response to the signal of described second pull-down node Q2 First pulls up between node P1 and described tertiary voltage end V3 and controls described tertiary voltage end V3 and described first outfan On-state between Gout1；

Described 3rd drop-down control module 3021 controls described second in response to the signal of described second pull-down node Q2 Between pull-up node P2 and described tertiary voltage end V3 and control described tertiary voltage end V3 and described second outfan Gout2 it Between on-state；Described 4th drop-down control module 3022 controls described in response to the signal of described first pull-down node Q1 Second pulls up between node P2 and described tertiary voltage end V3 and controls described tertiary voltage end V3 and described second outfan On-state between Gout2, wherein, described first drop-down control module 3011 and the structure of the 3rd drop-down control module 3021 Identical, and described and drop-down control module 3012 is identical with the structure of the 4th drop-down control module 3022；

Described first output module 501 controls the first clock signal terminal in response to the signal of described first pull-up node P1 On-state between CK1 and described first outfan Gout1, and, described second output module 502 is in response to described second Pull up the signal of node P2 and control the on-state between second clock signal end CK2 and described second outfan Gout2, its In, the signal phase difference of described first clock signal terminal CK1 and second clock signal end CK2 output is 180 degree, and described first Output module 501 is identical with the structure of the second output module 502.

The bilateral scanning unit that the embodiment of the present application provides, it includes first order subelement and second level subelement, double Can be along first order subelement to the scanning direction of second level subelement to scanning element, additionally it is possible to along second level subelement to The scanning direction of one-level subelement, and then realize bilateral scanning.Additionally, the first order subelement and that the embodiment of the present application provides The comprising modules structure of two grades of subelements is identical, and the composition structure of modules is the most identical, by first order subelement and Two grades of subelements interaction in scanning process so that when when wherein one-level subelement output scanning signal, another level Subelement does not export scanning signal, with meet two-stage subelement step by step export scanning signal purpose, and, by two-stage sub-list The interphase interaction of unit, and without two-stage subelement being controlled when scanning impact by external circuit, it is ensured that two-way sweep The line construction retouching unit is simple, it is easy to accomplish.

Shown in Fig. 2, a kind of concrete bilateral scanning unit providing the embodiment of the present application is described in detail. Wherein, the structural representation of the another kind of bilateral scanning unit that Fig. 2 provides for the embodiment of the present application.

With reference to shown in Fig. 2, described first input module 101 that the embodiment of the present application provides includes: the first transistor M1, the Two-transistor M2, third transistor M3 and the 4th transistor M4；

The grid of described the first transistor M1 is connected to described first and controls end SET1, the first of described the first transistor M1 End is connected to described first voltage end DIR1, and second end of described the first transistor M1 is connected to described first pull-up node P1； The grid of described transistor seconds M2 is connected to the described second the first end controlling end RESET1, described transistor seconds M2 and connects To described second voltage end DIR2, second end of described transistor seconds M2 is connected to described first pull-up node P1；Described The grid of three transistor M3 is connected to described first and controls end SET1, and the first end of described third transistor M3 is connected to described the Three voltage end V3, the second end of described third transistor M3 is connected to described first outfan Gout1；Described 4th transistor M4 Grid be connected to described second control end RESET1, first end of described 4th transistor M4 is connected to described tertiary voltage end V3, second end of described 4th transistor M4 is connected to described first outfan Gout1；

Owing to the first input module 101 is identical with the composition structure of the second output module 102, so the second input module 102 include four transistors equally, i.e. and, described second input module 102 includes: the 16th transistor M16, the 17th Transistor M17, the 18th transistor M18 and the 19th transistor M19；

The grid of described 16th transistor M16 is connected to the described 3rd and controls end SET2, described 16th transistor M16 The first end be connected to described first voltage end DIR1, second end of described 16th transistor M16 is connected on described second Draw node P2；The grid of described 17th transistor M17 is connected to the described 4th and controls end RESET2, described 17th transistor First end of M17 is connected to described second voltage end DIR2, and second end of described 17th transistor M17 is connected to described second Pull-up node P2；The grid of described 18th transistor M18 is connected to the described 3rd and controls end SET2, described 18th transistor First end of M18 is connected to described tertiary voltage end V3, and second end of described 18th transistor M18 is connected to described second defeated Go out to hold Gout2；The grid of described 19th transistor M19 is connected to the described 4th and controls end RESET2, described 19th crystal First end of pipe M19 is connected to described tertiary voltage end V3, and second end of described 19th transistor M19 is connected to described second Outfan Gout2.

It should be noted that the first transistor M1 of the embodiment of the present application offer, transistor seconds M2, third transistor M3 Identical with the conductivity type of the 4th transistor M4；And, the 16th transistor M16, the 17th transistor M17, the 18th crystal The conductivity type of pipe M18 and the 19th transistor M19 is identical.It addition, in the application one embodiment, owing to needs are by first The signal drawing node P1 and second pull-up node P2 is clear and definite, for the first input module 101, controls end first When SET1 controls to connect between the first pull-up node P1 and the first voltage end DIR1, second controls end RESET1 can not control simultaneously Connect between first pull-up node P1 and the second voltage end DIR2, and, control end RESET1 second and control the first pull-up joint When connecting between some P1 and the second voltage end DIR2, first controls end SET1 can not control the first pull-up node P1 and first simultaneously Connect between voltage end DIR1；Same, for the second input module 102, control end SET2 the 3rd and control on second When drawing connection between node P2 and the first voltage end DIR1, the 4th controls end RESET2 can not control the second pull-up node P2 simultaneously With second connect between voltage end DIR2, and, control end RESET2 the 4th and control the second pull-up node P2 and the second voltage When connecting between end DIR1, the 3rd controls end SET2 can not control between the second pull-up node P2 and the first voltage end DIR1 simultaneously Connect.It is to say, the first transistor M1 and transistor seconds M2 can not simultaneously turn on, and, the 16th transistor M16 and 17 transistor M17 can not simultaneously turn on equally.

Additionally, the signal that the tertiary voltage end V3 that the embodiment of the present application provides exports can be high level signal, it is also possible to For low level signal, need to carry out specific design according to reality application to this, mainly meet the signal of tertiary voltage end V3 output For can not raster polar curve (i.e. the pel array being connected with gate line can not be scanned by this signal) and can not controlling and the The transistor turns that three voltage end V3 directly or indirectly connect.

With reference to shown in Fig. 2, the described first pull-up control module 2011 that the embodiment of the present application provides includes: the 5th transistor M5 and the 6th transistor M6；

The grid of described 5th transistor M5 is connected to described first pull-up node P1, the first of described 5th transistor M5 End is connected to described tertiary voltage end V3, and second end of described 5th transistor M5 is connected to described first pull-down node Q1；Institute The grid stating the 6th transistor M6 is connected to described first pull-up node P1, and first end of described 6th transistor M6 is connected to institute Stating tertiary voltage end V3, second end of described 6th transistor M5 is connected to described first drop-down generation module 401；

Owing to the first pull-up control module 2011 is identical with the composition structure of the 3rd pull-up control module 2021, so the 3rd Pull-up control module 2021 includes two transistors equally, i.e. and, described 3rd pull-up control module 2021 includes: second Ten transistor M20 and the 21st transistor M21；

The grid of described 20th transistor M20 is connected to described second pull-up node P2, described 20th transistor M20 The first end be connected to described tertiary voltage end V3, second end of described 20th transistor M20 is connected to described second drop-down Node Q2；The grid of described 21st transistor M21 is connected to described second pull-up node P2, described 21st transistor First end of M21 is connected to described tertiary voltage end V3, and second end of described 21st transistor M21 is connected to described second Drop-down generation module 402.

With reference to shown in Fig. 2, described second pull-up control module 2012 includes: the 7th transistor M7 and the 8th transistor M8；

The grid of described 7th transistor M7 is connected to described second pull-up node P2, the first of described 7th transistor M7 End is connected to described tertiary voltage end V3, and second end of described 7th transistor M7 is connected to described first pull-down node Q1；Institute The grid stating the 8th transistor M8 is connected to described second pull-up node P2, and first end of described 8th transistor M8 is connected to institute Stating tertiary voltage end V3, second end of described 8th transistor M8 is connected to described first drop-down generation module 401；

Owing to the second pull-up control module 2012 is identical with the composition structure of the 4th pull-up control module 2022, so the 4th Pull-up control module 2022 includes two transistors equally, i.e. and, described 4th pull-up control module 2022 includes: second Ten two-transistor M22 and the 23rd transistor M23；

The grid of described 20th two-transistor M22 is connected to described first pull-up node P1, described 22nd crystal First end of pipe M22 is connected to described tertiary voltage end V3, and second end of described 20th two-transistor M22 is connected to described Two pull-down node Q2；The grid of described 23rd transistor M23 be connected to described first pull-up node P1, the described 23rd First end of transistor M23 is connected to described tertiary voltage end V3, and second end of described 23rd transistor M23 is connected to institute State the second drop-down generation module 402.

And, with reference to shown in Fig. 2, the described first drop-down generation module 401 that the embodiment of the present application provides includes: the 9th is brilliant Body pipe M9 and the tenth transistor M10；

The grid of described 9th transistor M9 is connected to described 6th transistor M6 and second end of the 8th transistor M8, institute The first end stating the 9th transistor M9 is connected to second end of described first signal end Vclock1, described 9th transistor M9 even It is connected to described first pull-down node Q1；Grid and first end of described tenth transistor M10 are connected to described first signal end Vclock1, second end of described tenth transistor M10 is connected to described 6th transistor M6 and the second of the 8th transistor M8 End；

Owing to the first drop-down generation module 401 is identical with the composition structure of the second drop-down generation module 402, so second time Generation module 402 is drawn to include two transistors equally, i.e. and, described second drop-down generation module 402 includes: the 20th Four transistor M24 and the 25th transistor M25；

The grid of described 24th transistor M24 is connected to described 21st transistor M21 and the 23rd crystal Second end of pipe M23, first end of described 24th transistor M24 is connected to described secondary signal end Vclock2, and described Second end of 24 transistor M24 is connected to described second pull-down node Q2；The grid of described 25th transistor M25 and First end is connected to described secondary signal end Vclock2, and second end of described 25th transistor M25 is connected to described 21 transistor M21 and second end of the 23rd transistor M23.

It should be noted that in the application one embodiment, the 5th transistor M5, the 6th transistor M6, the 7th transistor M7, the 8th transistor M8, the 20th transistor M20, the 21st transistor M21, the 20th two-transistor M22 and the 23rd The conductivity type of transistor M23 is identical；And, the 9th transistor M9, the tenth transistor M10, the 24th transistor M24 and The conductivity type of 25 transistor M25 is identical.Wherein, when the 6th transistor M6 and/or the 8th transistor M8 turns on, need Ensure the first drop-down generation module 401 can not and the first pull-down node Q1 between connect, so needing tertiary voltage end V3 to export Signal control between the first drop-down generation module 401 and the first pull-down node Q1 end；And, when the 21st transistor During M21 and/or the 23rd transistor M23 conducting, need also exist for ensureing that the second drop-down generation module 402 can not be drop-down with second Connect between node Q2, so the signal needing tertiary voltage end V3 to export controls the second drop-down generation module 402 and second time Draw and end between node Q2.Wherein, in the application one embodiment, in order to ensure that the signal that tertiary voltage end V3 exports plays control Make between drop-down generation module and pull-down node the purpose of cut-off, described 6th transistor M6 that the application one embodiment provides and The breadth length ratio of the 8th transistor M8 is all higher than the breadth length ratio of described tenth transistor M10；And, described 21st transistor The breadth length ratio of M21 and the 23rd transistor M23 is all higher than the breadth length ratio of described 25th transistor M25.The application for 6th transistor M6, the 8th transistor M8, the tenth transistor M10, the 21st transistor M21, the 23rd transistor M23 and The concrete scope of the breadth length ratio of the 25th transistor M25 does not limits, and needs to carry out specific design according to reality application to this.

With reference to shown in Fig. 2, the described first drop-down control module 3011 that the embodiment of the present application provides includes: the 11st crystal Pipe M11 and the tenth two-transistor M12；

The grid of described 11st transistor M11 is connected to described first pull-down node Q1, described 11st transistor M11 The first end be connected to described tertiary voltage end V3, second end of described 11st transistor M11 be connected to described first pull-up Node P1；The grid of described tenth two-transistor M12 is connected to described first pull-down node Q1, described tenth two-transistor M12 The first end be connected to described tertiary voltage end V3, second end of described tenth two-transistor M12 be connected to described first output End Gout1；

Owing to the first drop-down control module 3011 is identical with the composition structure of the 3rd drop-down control module 3021, so the 3rd Drop-down control module 3021 includes two transistors equally, i.e. and, described 3rd drop-down control module 3021 includes: second 16 transistor M26 and the 27th transistor M27；

The grid of described 26th transistor M26 is connected to described second pull-down node Q2, described 26th crystal First end of pipe M26 is connected to described tertiary voltage end V3, and second end of described 26th transistor M26 is connected to described Two pull-up node P2；The grid of described 27th transistor M27 is connected to described second pull-down node Q2, and the described 27th First end of transistor M27 is connected to described tertiary voltage end V3, and second end of described 27th transistor M27 is connected to institute State the second outfan Gout2.

And, the embodiment of the present application provide described second drop-down control module 3012 include: the 13rd transistor M13 and 14th transistor M14；

The grid of described 13rd transistor M13 is connected to described second pull-down node Q2, described 13rd transistor M13 The first end be connected to described tertiary voltage end V3, second end of described 13rd transistor M13 be connected to described first pull-up Node P1；The grid of described 14th transistor M14 is connected to described second pull-down node Q2, described 14th transistor M14 The first end be connected to described tertiary voltage end V3, second end of described 14th transistor M14 be connected to described first output End Gout1；

Owing to the second drop-down control module 3012 is identical with the composition structure of the 4th drop-down control module 3022, so, the Four drop-down control modules 3022 include two transistors equally, i.e. and, described 4th drop-down control module 3022 includes: the 28 transistor M28 and the 29th transistor M29；

The grid of described 28th transistor M28 is connected to described first pull-down node Q1, described 28th crystal First end of pipe M28 is connected to described tertiary voltage end V3, and second end of described 28th transistor M28 is connected to described Two pull-up node P2；The grid of described 29th transistor M29 is connected to described first pull-down node Q1, and the described 29th First end of transistor M29 is connected to described tertiary voltage end V3, and second end of described 29th transistor M29 is connected to institute State the second outfan Gout2.

With reference to shown in Fig. 2, described first output module 501 that the embodiment of the present application provides includes: the 15th transistor M15 With the first bootstrap capacitor C1；

The grid of described 15th transistor M15 and first pole plate of described first bootstrap capacitor C1 are connected to described One pull-up node P1, first end of described 15th transistor M15 is connected to described first clock signal terminal CK1, and the described tenth Second end of five transistor M15 is connected for described first outfan Gout1 with second pole plate of described first bootstrap capacitor C1, That is, second end of described 15th transistor M15 is connected with second pole plate of described first bootstrap capacitor C1 and with described One outfan Gout1 is connected；

Owing to the first output module 501 is identical with the composition structure of the second output module 502, so the second output module 502 include a transistor and a bootstrap capacitor equally, i.e. and, described second output module 502 includes: the 30th transistor M30 and the second bootstrap capacitor C2；

The grid of described 30th transistor M30 and first pole plate of described second bootstrap capacitor C2 are connected to described Two pull-up node P2, first end of described 30th transistor M30 is connected to described second clock signal end CK2, and the described 3rd Second end of ten transistor M30 is connected for described second outfan Gout2 with second pole plate of described second bootstrap capacitor C2, That is, second end of described 30th transistor M30 is connected with second pole plate of described second bootstrap capacitor C2 and with described Two outfan Gout2 are connected.

In the above-mentioned any one embodiment of the application, described first signal end Vclock1 and second letter that the application provides The level of signal of number end Vclock2 output can be identical.Additionally, in order to reduce power consumption, described first letter that the application provides The level of signal of number end Vclock1 and secondary signal end Vclock2 output can be contrary, and described first signal end The signal of Vclock1 and secondary signal end Vclock2 output is frame reverse signal；That is, scan through at described gate driver circuit After finishing a frame picture, the signal of the first signal end Vclock1 and secondary signal end Vclock2 output is the most anti-phase.And, this Shen The each transistor that please provide is both preferably thin film transistor (TFT).

The all modules of bilateral scanning unit the embodiment of the present application provided below in conjunction with driving method and composition Conducting and the cut-off situation of each transistor of each module are described further.It should be noted that it is brilliant with first below Body pipe M1 to the 30th transistor M30 is N-type transistor, and, tertiary voltage end V3 output signal is low level signal, and Scanning signal is to illustrate as a example by high level signal.

Shown in Fig. 1, Fig. 2, Fig. 3 a and Fig. 3 b, the driving method providing the embodiment of the present application carries out detailed retouching State.Wherein, the driving method that the embodiment of the present application provides, it is applied to above-mentioned bilateral scanning unit, described driving method includes: First stage T1, second stage T2, phase III T3 and fourth stage T4.

With reference to shown in Fig. 3 a, for the sequential chart of a kind of forward scan that the embodiment of the present application provides, i.e. along first order sub-list Unit to second level subelement is scanned, and wherein, the signal of the first voltage end DIR1 output is high level signal, and the second voltage The signal of end DIR2 output is low level signal.When scanning along described first order subelement to second level subelement:

At described first stage T1, described first input module 101 is in response to the described first signal controlling end SET1 Control between the first voltage end DIR1 and described first pull-up node P1 and control tertiary voltage end V3 and described first outfan Connect between Gout1；Wherein, described first pull-up control module 2011 is controlled in response to the signal of described first pull-up node P1 Make between described first pull-down node Q1 and described tertiary voltage end V3 and control described first pull-down node Q1 and described first End between drop-down generation module 401, and, described 4th pull-up control module 2022 is in response to described first pull-up node P1 Signal and control between described second pull-down node Q2 and described tertiary voltage end V3 connect and control described second drop-down joint End between some Q2 and described second drop-down generation module 402；Described first output module 501 is in response to described first pull-up joint Put the signal of P1 and control to connect between the first clock signal terminal CK1 and described first outfan Gout1；

Specifically combining shown in Fig. 2 and Fig. 3 a, at first stage T1, first controls end SET1 exports high level signal, and then Control the first transistor M1 and the conducting of third transistor M3 so that the signal of the first pull-up node P1 is that the first voltage end DIR1 is defeated The high level signal gone out and the signal of the first outfan Gout1 are the low level signal of tertiary voltage end V3 output.First pull-up Node P1 controls the 5th transistor M5 and the 6th transistor M6 conducting, and, control the 20th two-transistor M22 and the 23rd Transistor M23 turns on so that the signal of the first pull-down node Q1 and the second pull-down node Q2 is tertiary voltage end V3 output Low level signal and control end between the first drop-down generation module 401 and the first pull-down node Q1 and control the second drop-down life Become and end between module 402 and the second pull-down node Q2.First pull-up node P1 also controls the 15th transistor M15 conducting, will The low level signal of the first clock signal terminal CK1 output exports to the first outfan Gout1.

In described second stage T2, described first output module 501 is in response to the described first signal pulling up node P1 Control to connect between the first clock signal terminal CK1 and described first outfan Gout1, and described first clock signal terminal CK1 is defeated Go out signal for scanning signal；And, described second input module 102 controls described in response to the 3rd signal controlling end SET2 First voltage end DIR1 and described second pulls up between node P2 and controls described tertiary voltage end V3 and described second outfan Connect between Gout2；Wherein, described first pull-up control module 2011 is controlled in response to the signal of described first pull-up node P1 Make and connect between described first pull-down node Q1 and described tertiary voltage end V3 and control described first pull-down node Q1 with described End between first drop-down generation module 401；Described second pull-up control module 2012 is in response to described second pull-up node P2 Signal and control between described first pull-down node Q1 and described tertiary voltage end V3 connect and control described first drop-down joint End between some Q1 and described first drop-down generation module 401；And, described 3rd pull-up control module 2021 is in response to described The second pull-up signal of node P2 and control to connect between described second pull-down node Q2 and described tertiary voltage end V3 and control End between described second pull-down node Q2 and described second drop-down generation module 402；Described 4th pull-up control module 2022 Control between described second pull-down node Q2 and described tertiary voltage end V3 in response to the signal of described first pull-up node P1 Connect and control to end between described second pull-down node Q2 and described second drop-down generation module 402；Described second output mould Block 502 controls second clock signal end CK2 and described second outfan in response to the signal of described second pull-up node P2 Connect between Gout2；

Specifically combining shown in Fig. 2 and Fig. 3 a, in second stage T2, now the 15th transistor M15 is by the first clock signal The high level signal (i.e. scanning signal) of end CK1 output exports to the first outfan Gout1 and a pole of the first bootstrap capacitor C1 Plate, connected gate line is scanned by the first outfan Gout1, and the first bootstrap capacitor C1 will connect another pole plate The signal of the first pull-up node P1 is drawn high again.Owing to the signal of primary nodal point P1 is also higher high level signal, thus with The state of the transistor holding first stage T1 that primary nodal point P1 directly or indirectly connects is constant.It addition, when second stage T2 3rd controls end SET2 exports high level signal equally, and controls the 16th transistor M16 and the 18th transistor M18 conducting, Make the high level signal that signal is the first voltage end DIR1 output and the second outfan Gout2 of the second pull-up node P2 defeated Go out the low level signal of tertiary voltage end V3 output.It is brilliant that second pull-up node P2 controls the 20th transistor M20 and the 21st Body pipe M21 turns on, and, control the 7th transistor M7 and the 8th transistor M8 conducting so that the second pull-down node Q2 and first The signal of pull-down node Q1 is the low level signal of tertiary voltage end V3 output, and keeps controlling the first drop-down generation module 401 and the second drop-down generation module 402 cut-off state respectively and between the first pull-down node Q1 and the second pull-down node Q2.The Two pull-up node P2 also control the 30th transistor M30 conducting, and second clock signal end CK2 is exported by the 30th transistor M30 Low level signal output to the second outfan Gout2.

At described phase III T3, described second output module 502 is in response to the described second signal pulling up node P2 Control to connect between second clock signal end CK2 and described second outfan Gout2, and described second clock signal end output letter Number for scanning signal；And, described first input module 101 controls the signal of end RESET1 in response to described second and controls the Two voltage end DIR2 and described first pull up between node P1 and control described tertiary voltage end V3 and described first outfan Connect between Gout1；Wherein, described 3rd pull-up control module 2021 is controlled in response to the signal of described second pull-up node P2 Make and connect between described second pull-down node Q2 and described tertiary voltage end V3 and control described second pull-down node Q2 with described End between second drop-down generation module 402；Described second pull-up control module 2012 is in response to described second pull-up node P2 Signal and control between described first pull-down node Q1 and described tertiary voltage end V3 connect and control described first drop-down joint End between some Q1 and described first drop-down generation module 401；

Specifically combining shown in Fig. 2 and Fig. 3 a, at phase III T3, now the 30th transistor M30 is by second clock signal The high level signal (i.e. scanning signal) of end CK2 output exports to the second outfan Gout2 and a pole of the second bootstrap capacitor C2 Plate, connected gate line is scanned by the second outfan Gout2, and the second bootstrap capacitor C2 will connect another pole plate The signal of the second pull-up node P2 is drawn high again.Owing to the signal of secondary nodal point P2 is also higher high level signal, thus with The state of transistor holding second stage T2 that secondary nodal point P2 directly or indirectly connects is constant.It addition, when phase III T3 Second controls end RESET1 exports high level signal, and controls transistor seconds M2 and the 4th transistor M4 conducting so that first The signal of pull-up node P1 is the low level signal of the second voltage end DIR2 output and the signal of the first outfan Gout1 is the The low level signal of three voltage end V3 outputs；Now, the transistor being connected with the first pull-up node P1 is cut-off state.

In described fourth stage T4, described second input module 102 is in response to the described 4th signal controlling end RESET2 And control between described second voltage end DIR2 and described second pull-up node P2 and control described tertiary voltage end V3 with described Connect between second outfan Gout2；Wherein, described first drop-down generation module 401 is in response to the first signal end Vclock1's Signal and control described first signal end Vclock1 and control between described first pull-down node Q1 connect；And, described first Drop-down control module 3011 controls described first pull-up node P1 with described in response to the signal of described first pull-down node Q1 Between tertiary voltage end V3 and control between described tertiary voltage end V3 and described first outfan Gout1 connect；Described 4th Drop-down control module 3022 controls described second pull-up node P2 with described in response to the signal of described first pull-down node Q1 Between tertiary voltage end V3 and control between described tertiary voltage end V3 and described second outfan Gout2 connect；Or, described Second drop-down generation module 402 control in response to the signal of secondary signal end Vclock2 described secondary signal end Vclock2 with Connect between described second pull-down node Q2；And, described 3rd drop-down control module 3021 is in response to described second drop-down joint Put the signal of Q2 and control between described second pull-up node P2 and described tertiary voltage end V3 and control described tertiary voltage end Connect between V3 and described second outfan Gout2；Described second drop-down control module 3012 is in response to described second drop-down joint Put the signal of Q2 and control between described first pull-up node P1 and described tertiary voltage end V3 and control described tertiary voltage end Connect between V3 and described first outfan Gout1；

Specifically combining shown in Fig. 2 and Fig. 3 a, in fourth stage T4, the 4th controls end RESET2 exports high level signal, and Control the 17th transistor M17 and the 19th transistor M19 conducting so that the signal of the second pull-up node P2 is the second voltage end The low level signal of DIR2 output and the low level signal that signal is tertiary voltage end V3 output of the second outfan Gout2.By The transistor being connected with the first pull-up node P1 and the second pull-up node P2 when in fourth stage T4 is cut-off state, thus Can not again stop the first drop-down generation module 401 and the second drop-down generation module 402 respectively with the first pull-down node Q1 and Turn between second pull-down node Q2.Wherein, with reference to shown in Fig. 3 a, in the application one embodiment, the first signal end Vclock1 Output signal be high level signal and secondary signal end Vclock2 output signal be low level signal, thus, first time The tenth transistor M10 drawing generation module 401 responds the control of the high level signal of the first signal end Vclock1 output, by height Level signal transmits the grid to the 9th transistor M9, and then by after the 9th transistor M9 conducting, the first signal end Vclock1 is defeated The high level signal gone out exports to the first pull-down node Q1.First pull-down node Q1 controls the 11st transistor M11 and the 12nd Transistor M12 turns on, and, control the 28th transistor M28 and the 29th transistor M29 conducting so that the first pull-up The signal of node P1 and second pull-up node P2 and the signal of the first outfan Gout1 and the second outfan Gout2 are the 3rd The low level signal of voltage end V3 output.

Additionally, the signal of secondary signal end Vclock2 can also be high level signal when forward scan, and the first signal The signal of end Vclock1 is low level signal, is not particularly limited this application.

And, with reference to shown in Fig. 3 b, for the sequential chart of a kind of reverse scan that the embodiment of the present application provides, i.e. along second Level subelement is scanned to first order subelement, now, and the signal of the first voltage end DIR1 and the second voltage end DIR2 output Anti-phase, the i.e. first voltage end DIR1 output low level signal, and the second voltage end DIR2 exports high level signal, wherein, on edge When described second level subelement to first order subelement scans:

At described first stage T1, described second input module 102 is controlled in response to the 4th signal controlling end RESET2 Make between described second voltage end DIR2 and described second pull-up node P2 and control described tertiary voltage end V3 and described second Connect between outfan Gout2；Wherein, described 3rd pull-up control module 2021 is in response to the letter of described second pull-up node P2 Number and control between described second pull-down node Q2 and described tertiary voltage end V3 connect and control described second pull-down node Q2 And connect between described second drop-down generation module 402；Described second pull-up control module 2012 is in response to described second pull-up The signal of node P2 and control connect between described first pull-down node Q1 and described tertiary voltage end V3 and control described first Connect between pull-down node Q1 and described first drop-down generation module 401；Described second output module 502 is in response to described second Pull up the signal of node P2 and control to connect between second clock signal end CK2 and described second outfan Gout2；

Specifically combining shown in Fig. 2 and Fig. 3 b, at first stage T1, the 4th controls end RESET2 exports high point ordinary mail number, and Control the 17th transistor M17 and the 19th transistor M9 conducting so that the signal of the second pull-up node P2 is the second voltage end The high level signal of DIR2 output and the low level signal that signal is tertiary voltage end V3 output of the first outfan Gout1.The Two pull-up node P2 control the 20th transistor M20 and the 21st transistor M21 conducting, and, control the 7th transistor M7 With the 8th transistor M8 conducting so that the signal of the second pull-down node Q2 is the low level signal of tertiary voltage end V3 output, and Make the first drop-down generation module 401 and the second drop-down generation module 402 joint drop-down with the first pull-down node Q1 and second respectively Cut-off between some Q2.Second pull-up node P2 also controls the 30th transistor M30 conducting, and the 30th transistor M30 is by second The low level signal of clock signal terminal CK2 output exports to the second outfan Gout2.

In described second stage T2, described second output module 502 is in response to the described second signal pulling up node P2 Control to connect between second clock signal end CK2 and described second outfan Gout2, and described second clock signal end CK2 is defeated The signal gone out is described scanning signal；And, described first input module 101 is in response to the second signal controlling end RESET1 Control between the second voltage end DIR2 and described first pull-up node P1 and control tertiary voltage end V3 and described first outfan Connect between Gout1；Wherein, described 3rd pull-up control module 2021 is controlled in response to the signal of described second pull-up node P2 Make and connect between described second pull-down node Q2 and described tertiary voltage end V3 and control described second pull-down node Q2 with described Connect between second drop-down generation module 402；Described second pull-up control module 2012 is in response to described second pull-up node P2 Signal and control between described first pull-down node Q1 and described tertiary voltage end V3 connect and control described first drop-down joint Connect between some Q1 and described first drop-down generation module 401；Described second output module 502 is in response to described second pull-up joint Put the signal of P2 and control to connect between second clock signal end CK2 and described second outfan Gout2；And, described first Pull-up control module 2011 controls described first pull-down node Q1 with described in response to the signal of described first pull-up node P1 Connect between tertiary voltage end V3 and control to cut between described first pull-down node Q1 and described first drop-down generation module 401 Only；Described 4th pull-up control module 2022 controls described second drop-down joint in response to the signal of described first pull-up node P1 Connect between some Q2 and described tertiary voltage end V3 and control described second pull-down node Q2 and described second drop-down generation module End between 402；Described first output module 501 controls the first clock letter in response to the signal of described first pull-up node P1 Number end CK1 and described first outfan Gout1 between connect；

Specifically combining shown in Fig. 2 and Fig. 3 b, in second stage T2, now the 30th transistor M30 is by second clock signal The high level signal (i.e. scanning signal) of end CK2 output exports to the second outfan Gout2 and a pole of the second bootstrap capacitor C2 Plate, connected gate line is scanned by the second outfan Gout2, and the second bootstrap capacitor C2 will connect another pole plate The signal of the second pull-up node P2 is drawn high again.Owing to the signal of secondary nodal point P2 is also higher high level signal, thus with The state of the transistor holding first stage T1 that secondary nodal point P2 directly or indirectly connects is constant.It addition, when second stage T2 Second controls end RESET1 exports high point ordinary mail number, and controls transistor seconds M2 and the 4th transistor M4 conducting so that first The high level signal that signal is the second voltage end DIR2 output and the first outfan Gout1 that pull up node P1 are tertiary voltage The low level signal of end V3 output.First pull-up node P1 controls the 5th transistor M5 and the 6th transistor M6 conducting, and, control Make the 20th two-transistor M22 and the 23rd transistor M23 conducting so that the first pull-down node Q1 and the second pull-down node Q2 Signal be tertiary voltage end V3 output low level signal, and keep the first drop-down generation module 401 and the first drop-down joint End between some Q1 and control to end between the second drop-down generation module 402 and the second pull-down node Q2.First pull-up node P1 Also control the 15th transistor M15 conducting, the low level signal of the first clock signal terminal CK1 output is exported to the first outfan Gout1。

At described phase III T3, described first output module 501 is in response to the described first signal pulling up node P1 Control to connect between the first clock signal terminal CK1 and described first outfan Gout1, and described first clock signal terminal CK1 is defeated The signal gone out is described scanning signal；And, described second input module 102 is in response to the described 3rd signal controlling end SET2 And control between described first voltage end DIR1 and described second pull-up node P2 and control described tertiary voltage end V3 with described Connect between second outfan Gout2；Wherein, described first pull-up control module 2011 is in response to described first pull-up node P1 Signal and control between described first pull-down node Q1 and described tertiary voltage end V3 connect and control described first drop-down joint End between some Q1 and described first drop-down generation module 401；Described 4th pull-up control module 2022 is in response to described first Pull up the signal of node P1 and control to connect between described second pull-down node Q2 and described tertiary voltage end V3 and described in control End between second pull-down node Q2 and described second drop-down generation module 402；

Specifically combining shown in Fig. 2 and Fig. 3 b, at phase III T3, now the 15th transistor M15 is by the first clock signal The high level signal (i.e. scanning signal) of end CK1 output exports to the first outfan Gout1 and a pole of the first bootstrap capacitor C1 Plate, connected gate line is scanned by the first outfan Gout1, and the first bootstrap capacitor C1 will connect another pole plate The signal of the first pull-up node P1 is drawn high again.Owing to the signal of primary nodal point P1 is also higher high level signal, thus with The state of transistor holding second stage T2 that primary nodal point P1 directly or indirectly connects is constant.It addition, when phase III T3 3rd controls end SET2 exports high level signal, and controls the 16th transistor M16 and the 18th transistor M18 conducting so that The signal of the second pull-up node P2 is low level signal and the signal of the second outfan Gout2 of the first voltage end DIR1 output Low level signal for tertiary voltage end V3 output；Now, the transistor being connected with the second pull-up node P2 is cut-off state.

In described fourth stage T4, described first input module 101 is in response to the described first signal controlling end SET1 Control between the first voltage end DIR1 and described first pull-up node P1 and the described tertiary voltage end V3 of control is first defeated with described Go out to hold and connect between Gout1；Wherein, described first drop-down generation module 401 in response to the first signal end Vclock1 signal and Control described first signal end Vclock1 and control to connect between described first pull-down node Q1；And, described first drop-down control Molding block 3011 controls described first pull-up node P1 and described 3rd electricity in response to the signal of described first pull-down node Q1 Between pressure side V3 and control between described tertiary voltage end V3 and described first outfan Gout1 connect；Described 4th drop-down control Molding block 3022 controls described second pull-up node P2 and described 3rd electricity in response to the signal of described first pull-down node Q1 Between pressure side V3 and control between described tertiary voltage end V3 and described second outfan Gout2 connect；Or, described second time Generation module 402 is drawn to control described secondary signal end Vclock2 and described the in response to the signal of secondary signal end Vclock2 Connect between two pull-down node Q2；And, described 3rd drop-down control module 3021 is in response to described second pull-down node Q2 Signal and control between described second pull-up node P2 and described tertiary voltage end V3 and control described tertiary voltage end V3 and institute State and connect between the second outfan Gout2；Described second drop-down control module 3012 is in response to described second pull-down node Q2 Signal and control between described first pull-up node P1 and described tertiary voltage end V3 and control described tertiary voltage end V3 and institute State and connect between the first outfan Gout1.

Specifically combining shown in Fig. 2 and Fig. 3 b, in fourth stage T4, first controls end SET1 exports high level signal, and controls The first transistor M1 processed and the conducting of third transistor M3 so that the signal of the first pull-up node P1 is the first voltage end DIR1 output Low level signal and low level signal that the signal of the first outfan Gout1 is tertiary voltage end V3 output.Due to the 4th The transistor being connected with the first pull-up node P1 and the second pull-up node P2 during stage T4 is cut-off state, because being unable to again The secondary drop-down generation module of prevention first 401 and the second drop-down generation module 402 are drop-down with the first pull-down node Q1 and second respectively Turn between node Q2.Wherein, with reference to shown in Fig. 3 b, in the application one embodiment, the letter of the first signal end Vclock1 output Number for low level signal and secondary signal end Vclock2 output signal be high level signal, thus, the second drop-down generation mould The control of the high level signal of the 25th transistor M25 response secondary signal end Vclock2 output of block 402, by high level Signal transmits the grid to the 24th transistor M24, after then the 24th transistor M24 being turned on, and secondary signal end The high level signal of Vclock2 output exports to the second pull-down node Q2.Second pull-down node Q2 controls the 26th transistor M26 and the 27th transistor M27, and, control the 13rd transistor M13 and the 14th transistor M14 conducting so that second The signal of pull-up node P2 and first pull-up node P1 and the signal of the second outfan Gout2 and the first outfan Gout1 are The low level signal of tertiary voltage end V3 output.

Additionally, the signal of secondary signal end Vclock2 can also be low level signal when reverse scan, and the first signal The signal of end Vclock1 is high level signal, is not particularly limited this application.

Further, the problem random in order to avoid there is start wadding, the bilateral scanning unit that the embodiment of the present application provides is also Including the first initialization module and the second initialization module；First initialization module and the second initialization module are in scanning Before, the signal of the first pull-up node in bilateral scanning unit and the second pull-up node is resetted.With specific reference to shown in Fig. 4, For the structural representation of another bilateral scanning unit that the embodiment of the present application provides, wherein, described bilateral scanning unit also wraps Include:

The first initialization module 601 being connected with described first pull-up node P1, and, with described second pull-up node P2 The second initialization module 602 connected；

Wherein, described first initialization module 601 controls described first in response to the signal of reseting controling end Re_all On-state between pull-up node P1 and resetting voltage end V0, and, described second initialization module 602 is in response to described multiple Position controls the signal of end Re_all and controls the on-state between described second pull-up node P2 and described resetting voltage end V0.

Wherein, described first initialization module 601 that the embodiment of the present application provides may include that the 31st transistor M31；

The grid of described 31st transistor M31 is connected to described reseting controling end Re_all, and the described 31st is brilliant First end of body pipe M31 is connected to described resetting voltage end V0, and second end of described 31st transistor M31 is connected to described First pull-up node P1；

The composition structure of described first initialization module 601 and the second initialization module 602 can be identical, i.e. and, institute State the second initialization module 602 to include: the 30th two-transistor M32；

The grid of described 30th two-transistor M32 is connected to described reseting controling end Re_all, and the described 32nd is brilliant First end of body pipe M32 is connected to described resetting voltage end V0, and second end of described 30th two-transistor M32 is connected to described Second pull-up node P2.

It should be noted that the bilateral scanning unit that the embodiment of the present application provides is to implement corresponding to above-mentioned Fig. 3 a and Fig. 3 b During the bilateral scanning unit that example provides, the 31st transistor M31 and the 30th two-transistor M32 that the application provides can be N-type transistor, reseting controling end Re_all is high level signal before bilateral scanning unit scan, with by the 31st transistor M31 and the 30th two-transistor M32 conducting, is transmitted separately to the by the signal that the resetting voltage end V0 for low level signal exports One pull-up node P1 and the second pull-up node P2, so that the first pull-up node P1 and the second pull-up node P2 is carried out signal reset, Avoid the occurrence of the problem that start wadding is random.

Additionally, the first initialization module of the embodiment of the present application offer and the second initialization module can also be by drop-down Node carries out control of Electric potentials, indirectly to reach the purpose to pull-up node reset.With specific reference to shown in Fig. 5, implement for the application The structural representation of another bilateral scanning unit that example provides, wherein, described bilateral scanning unit includes:

The first initialization module 601 being connected with described first pull-down node Q1, and, with described second pull-down node Q2 The second initialization module 602 connected；

Wherein, described first initialization module 601 controls described first in response to the signal of reseting controling end Re_all On-state between pull-down node Q1 and described reseting controling end Re_all, and, described second initialization module 602 responds Control in the signal of described reseting controling end Re_all described second pull-down node Q2 and described reseting controling end Re_all it Between on-state.

Wherein, described first initialization module 601 that the application provides includes: the 31st transistor M31；

The grid of described 31st transistor M31 and the first end are connected to described reseting controling end, and the described 30th Second end of one transistor M31 is connected to described first pull-down node Q1；

And, described second initialization module 602 includes: the 30th two-transistor M32；

The grid of described 30th two-transistor M32 and the first end are connected to described reseting controling end, and the described 30th Second end of two-transistor M32 is connected to described second pull-down node Q2.

It should be noted that the bilateral scanning unit that the embodiment of the present application provides is to implement corresponding to above-mentioned Fig. 3 a and Fig. 3 b During the bilateral scanning unit that example provides, the 31st transistor M31 and the 30th two-transistor M32 that the application provides can be N-type transistor, reseting controling end Re_all is high level signal before bilateral scanning unit scan, with by the 31st transistor M31 and the 30th two-transistor M32 conducting, transmits respectively by the signal that the reseting controling end Re_all for high level signal exports To the first pull-down node Q1 and the second pull-down node Q2, connected respectively by the first pull-down node Q1 and the second pull-down node Q2 Drop-down control module, all and connects the first pull-up node P1 and the second pull-up node P2 between tertiary voltage end V3, Jin Ertong First pull-up node P1 and the second pull-up node P2 is resetted by the signal crossing tertiary voltage end V3, it is to avoid start wadding occur disorderly Problem.

Additionally, the embodiment of the present application additionally provides a kind of gate driver circuit, described gate driver circuit includes that n level is two-way Scanning element be first order bilateral scanning unit to n-th grade of bilateral scanning unit, wherein, every one-level bilateral scanning unit is Stating the bilateral scanning unit described in any one embodiment, n is the integer not less than 2.

Wherein, with reference to shown in Fig. 6, for the structural representation of a kind of gate driver circuit that the embodiment of the present application provides, its In, defining bilateral scanning unit described in adjacent two-stage is i-stage bilateral scanning unit 1i and i+1 level bilateral scanning unit 1 (i+ 1), i is the positive integer of no more than n；

The first outfan Gout1 of described i-stage bilateral scanning unit 1i and described i+1 level bilateral scanning unit 1 (i+ 1) the first control end SET1 is connected, the first outfan Gout1 of described i+1 level bilateral scanning unit 1 (i+1) and described the The second control end RESET1 of i level bilateral scanning unit 1i is connected；

The second outfan Gout2 of described i-stage bilateral scanning unit 1i and described i+1 level bilateral scanning unit 1 (i+ 1) the 3rd control end SET2 is connected, the second outfan Gout2 of described i+1 level bilateral scanning unit 1 (i+1) and described the The 4th control end RESET2 of i level bilateral scanning unit 1i is connected；

And, the first clock signal terminal CK1 of odd level bilateral scanning unit is same signal end and second clock signal End CK2 is same signal end, and the first clock signal terminal CK1 of even level bilateral scanning unit is same signal end and when second Clock signal end CK2 is same signal end.

It should be noted that in the gate driver circuit that the embodiment of the present application provides, when forward scan, the first order is double Control end SET2 to the first control end SET1 and the 3rd of scanning element and all provide initial control signal by outer signal line； And, when reverse scan, the second control end RESET1 and the 4th of n-th grade of bilateral scanning unit controls end RESET2 and all passes through External holding wire provides initial control signal.Additionally, due to need the n level bilateral scanning unit of cascade in scanning process All outfans export scanning signal step by step, therefore, when forward scan, first order bilateral scanning unit corresponding first time Its second clock signal end output scanning signal after clock signal end output scanning signal；Same, second level bilateral scanning unit Its second clock signal end output scanning signal after the first corresponding clock signal terminal output scanning signal, and, the first order is double After the second clock signal end of scanning element exports scanning signal, the first clock signal terminal of second level bilateral scanning unit is defeated Go out to scan signal.And, when reverse scan, the second clock signal end output scanning letter that n-th grade of bilateral scanning unit is corresponding Its first clock end output scanning signal after number；Same, the second clock signal end that the (n-1)th bilateral scanning unit is corresponding exports Its first clock signal terminal output scanning signal after scanning signal, and, the first clock signal terminal of n-th grade of bilateral scanning unit After output scanning signal, the second clock signal end output scanning signal of (n-1)th grade of bilateral scanning unit.

Additionally, in actual applications, described first clock signal terminal and second clock signal end that the application provides export Signal phase difference be 180 degree, wherein, the first clock signal terminal is identical with the frequency of the signal that second clock signal end exports, And when forward scan, second clock signal end postpones Preset Time output compared to the first clock signal terminal；And, reversely During scanning, the first clock signal terminal postpones Preset Time output compared to second clock signal end.Multistage bidirectional for cascade Scanning element, when forward scan, the first clock signal terminal of rear stage bilateral scanning unit is compared to previous stage bilateral scanning The second clock signal end of unit postpones Preset Time output；And, when reverse scan, the of rear stage bilateral scanning unit Export between two clock signal terminals are default compared to the first clock signal terminal delay of previous stage bilateral scanning unit.Wherein, originally Application is not particularly limited for Preset Time.

The embodiment of the present application provides a kind of bilateral scanning unit, driving method and gate driver circuit, bilateral scanning list Unit includes first order subelement and second level subelement, and bilateral scanning unit can be along first order subelement to second level sub-list The direction of unit exports scanning signal step by step, it is also possible to export scanning step by step along second level subelement to the direction of first order subelement Signal, and in scanning process, first order subelement and second level subelement cooperate, and make sweeping when the output of prime subelement When retouching signal, another grade of subelement does not export scanning signal.The technical scheme that the embodiment of the present application provides, bilateral scanning unit energy Enough output two-stage scan signals step by step, and interact by first order subelement and second level subelement and simplify bilateral scanning The structure of unit, and meet the multifarious demand of gate driver circuit.

Described above to the disclosed embodiments, makes professional and technical personnel in the field be capable of or uses this practicality new Type.Multiple amendment to these embodiments will be apparent from for those skilled in the art, is determined herein The General Principle of justice can realize in the case of without departing from spirit or scope of the present utility model in other embodiments.Cause This, this utility model is not intended to be limited to the embodiments shown herein, and is to fit to and principles disclosed herein The widest scope consistent with features of novelty.

Claims

1. a bilateral scanning unit, it is characterised in that described bilateral scanning unit includes first order subelement and second level Unit, wherein, described first order subelement includes: the first input module, the first pull-up node, the first pull-up control module, the Two pull-up control module, the first pull-down node, the first drop-down control module, the second drop-down control module, the first drop-down generation moulds Block, the first output module and the first outfan；And, described second level subelement includes: the second input module, the second pull-up joint Point, the 3rd pull-up control module, the 4th pull-up control module, the second pull-down node, the 3rd drop-down control module, the 4th drop-down control Molding block, the second drop-down generation module, the second output module and the second outfan；

Described first input module controls the first voltage end and described first pull-up node in response to the first signal controlling end Between and the on-state that controls between tertiary voltage end and described first outfan, and the signal controlling end in response to second And control between the second voltage end and described first pull-up node and control described tertiary voltage end and described first outfan it Between on-state, wherein, the level of signal of described first voltage end and the output of the second voltage end is contrary；

Described second input module controls described first voltage end and described second pull-up in response to the 3rd signal controlling end Between node and the on-state that controls between described tertiary voltage end and described second outfan, and control in response to the 4th End signal and control described second voltage end and described second pull-up node between and control described tertiary voltage end with described On-state between second outfan, wherein, the structure of described first input module and the second input module is identical；

Described first pull-up control module in response to described first pull-up node signal and control described first pull-down node with Between described tertiary voltage end and the on-state that controls between described first pull-down node and described first drop-down generation module； Described second pull-up control module controls described first pull-down node with described in response to the signal of described second pull-up node Between tertiary voltage end and the on-state that controls between described first pull-down node and described first drop-down generation module；

Described 3rd pull-up control module in response to described second pull-up node signal and control described second pull-down node with Between described tertiary voltage end and the on-state that controls between described second pull-down node and described second drop-down generation module； Described 4th pull-up control module controls described second pull-down node with described in response to the signal of described first pull-up node Between tertiary voltage end and the on-state that controls between described second pull-down node and described second drop-down generation module, its In, described first pull-up control module with the 3rd pull-up control module structure identical, and described second pull-up control module and The structure of the 4th pull-up control module is identical；

Described first drop-down generation module controls described first signal end and described first in response to the signal of the first signal end On-state between pull-down node；

Described second drop-down generation module controls described secondary signal end and described second in response to the signal of secondary signal end On-state between pull-down node, and the structure of described first drop-down generation module and the second drop-down generation module is identical；

Described first drop-down control module control in response to the signal of described first pull-down node described first pull-up node with Between described tertiary voltage end and the on-state that controls between described tertiary voltage end and described first outfan；Described second Drop-down control module controls described first pull-up node and described tertiary voltage in response to the signal of described second pull-down node Between end and the on-state that controls between described tertiary voltage end and described first outfan；

Described 3rd drop-down control module control in response to the signal of described second pull-down node described second pull-up node with Between described tertiary voltage end and the on-state that controls between described tertiary voltage end and described second outfan；Described 4th Drop-down control module controls described second pull-up node and described tertiary voltage in response to the signal of described first pull-down node Between end and the on-state that controls between described tertiary voltage end and described second outfan, wherein, described first drop-down control The structure of molding block and the 3rd drop-down control module is identical, and described second drop-down control module and the 4th drop-down control module Structure is identical；

Described first output module controls the first clock signal terminal and described the in response to the signal of described first pull-up node On-state between one outfan, and, described second output module is controlled in response to the signal of described second pull-up node On-state between second clock signal end processed and described second outfan, wherein, described first clock signal terminal and second The signal phase difference of clock signal terminal output is 180 degree, and the structure of described first output module and the second output module is identical.

Bilateral scanning unit the most according to claim 1, it is characterised in that described first input module includes: first is brilliant Body pipe, transistor seconds, third transistor and the 4th transistor；

The grid of described the first transistor is connected to described first and controls end, and the first end of described the first transistor is connected to described First voltage end, the second end of described the first transistor is connected to described first pull-up node；The grid of described transistor seconds Being connected to described second and control end, the first end of described transistor seconds is connected to described second voltage end, described second crystal Second end of pipe is connected to described first pull-up node；The grid of described third transistor is connected to described first and controls end, institute The first end stating third transistor is connected to described tertiary voltage end, and the second end of described third transistor is connected to described first Outfan；The grid of described 4th transistor is connected to described second and controls end, and the first end of described 4th transistor is connected to Described tertiary voltage end, the second end of described 4th transistor is connected to described first outfan；

And, described second input module includes: the 16th transistor, the 17th transistor, the 18th transistor and the 19th Transistor；

The grid of described 16th transistor is connected to the described 3rd and controls end, and the first end of described 16th transistor is connected to Described first voltage end, the second end of described 16th transistor is connected to described second pull-up node；Described 17th crystal The grid of pipe is connected to the described 4th and controls end, and the first end of described 17th transistor is connected to described second voltage end, institute The second end stating the 17th transistor is connected to described second pull-up node；The grid of described 18th transistor is connected to described 3rd controls end, and the first end of described 18th transistor is connected to described tertiary voltage end, the of described 18th transistor Two ends are connected to described second outfan；The grid of described 19th transistor be connected to described 4th control end, the described tenth First end of nine transistors is connected to described tertiary voltage end, and the second end of described 19th transistor is connected to described second defeated Go out end.

Bilateral scanning unit the most according to claim 1, it is characterised in that described first pull-up control module includes: the Five transistors and the 6th transistor；

The grid of described 5th transistor is connected to described first pull-up node, and the first end of described 5th transistor is connected to institute Stating tertiary voltage end, the second end of described 5th transistor is connected to described first pull-down node；The grid of described 6th transistor Pole is connected to described first pull-up node, and the first end of described 6th transistor is connected to described tertiary voltage end, and the described 6th Second end of transistor is connected to described first drop-down generation module；

And, described 3rd pull-up control module includes: the 20th transistor and the 21st transistor；

The grid of described 20th transistor is connected to described second pull-up node, and the first end of described 20th transistor connects To described tertiary voltage end, the second end of described 20th transistor is connected to described second pull-down node；Described 21st The grid of transistor is connected to described second pull-up node, and the first end of described 21st transistor is connected to described 3rd electricity Pressure side, the second end of described 21st transistor is connected to described second drop-down generation module.

Bilateral scanning unit the most according to claim 3, it is characterised in that described second pull-up control module includes: the Seven transistors and the 8th transistor；

The grid of described 7th transistor is connected to described second pull-up node, and the first end of described 7th transistor is connected to institute Stating tertiary voltage end, the second end of described 7th transistor is connected to described first pull-down node；The grid of described 8th transistor Pole is connected to described second pull-up node, and the first end of described 8th transistor is connected to described tertiary voltage end, and the described 8th Second end of transistor is connected to described first drop-down generation module；

And, described 4th pull-up control module includes: the 20th two-transistor and the 23rd transistor；

The grid of described 20th two-transistor is connected to described first pull-up node, the first end of described 20th two-transistor Being connected to described tertiary voltage end, the second end of described 20th two-transistor is connected to described second pull-down node；Described The grid of 23 transistors is connected to described first pull-up node, and the first end of described 23rd transistor is connected to described Tertiary voltage end, the second end of described 23rd transistor is connected to described second drop-down generation module.

Bilateral scanning unit the most according to claim 4, it is characterised in that described first drop-down generation module includes: the Nine transistors and the tenth transistor；

The grid of described 9th transistor is connected to described 6th transistor and the second end of the 8th transistor, described 9th crystal First end of pipe is connected to described first signal end, and the second end of described 9th transistor is connected to described first pull-down node； The grid of described tenth transistor and the first end are connected to described first signal end, and the second end of described tenth transistor connects To described 6th transistor and the second end of the 8th transistor；

And, described second drop-down generation module includes: the 24th transistor and the 25th transistor；

The grid of described 24th transistor is connected to described 21st transistor and the second end of the 23rd transistor, First end of described 24th transistor is connected to described secondary signal end, and the second end of described 24th transistor connects To described second pull-down node；The grid of described 25th transistor and the first end are connected to described secondary signal end, institute The second end stating the 25th transistor is connected to described 21st transistor and the second end of the 23rd transistor.

Bilateral scanning unit the most according to claim 5, it is characterised in that described 6th transistor and the 8th transistor Breadth length ratio is all higher than the breadth length ratio of described tenth transistor；

And, the breadth length ratio of described 21st transistor and the 23rd transistor is all higher than described 25th transistor Breadth length ratio.

Bilateral scanning unit the most according to claim 1, it is characterised in that described first drop-down control module includes: the 11 transistors and the tenth two-transistor；

The grid of described 11st transistor is connected to described first pull-down node, and the first end of described 11st transistor connects To described tertiary voltage end, the second end of described 11st transistor is connected to described first pull-up node；Described 12nd is brilliant The grid of body pipe is connected to described first pull-down node, and the first end of described tenth two-transistor is connected to described tertiary voltage End, the second end of described tenth two-transistor is connected to described first outfan；

And, described 3rd drop-down control module includes: the 26th transistor and the 27th transistor；

The grid of described 26th transistor is connected to described second pull-down node, the first end of described 26th transistor Being connected to described tertiary voltage end, the second end of described 26th transistor is connected to described second pull-up node；Described The grid of 27 transistors is connected to described second pull-down node, and the first end of described 27th transistor is connected to described Tertiary voltage end, the second end of described 27th transistor is connected to described second outfan.

Bilateral scanning unit the most according to claim 7, it is characterised in that described second drop-down control module includes: the 13 transistors and the 14th transistor；

The grid of described 13rd transistor is connected to described second pull-down node, and the first end of described 13rd transistor connects To described tertiary voltage end, the second end of described 13rd transistor is connected to described first pull-up node；Described 14th is brilliant The grid of body pipe is connected to described second pull-down node, and the first end of described 14th transistor is connected to described tertiary voltage End, the second end of described 14th transistor is connected to described first outfan；

And, described 4th drop-down control module includes: the 28th transistor and the 29th transistor；

The grid of described 28th transistor is connected to described first pull-down node, the first end of described 28th transistor Being connected to described tertiary voltage end, the second end of described 28th transistor is connected to described second pull-up node；Described The grid of 29 transistors is connected to described first pull-down node, and the first end of described 29th transistor is connected to described Tertiary voltage end, the second end of described 29th transistor is connected to described second outfan.

Bilateral scanning unit the most according to claim 1, it is characterised in that described first output module includes: the 15th Transistor and the first bootstrap capacitor；

The grid of described 15th transistor and the first pole plate of described first bootstrap capacitor are connected to described first pull-up joint Point, the first end of described 15th transistor is connected to described first clock signal terminal, the second end of described 15th transistor It is connected for described first outfan with the second pole plate of described first bootstrap capacitor；

And, described second output module includes: the 30th transistor and the second bootstrap capacitor；

The grid of described 30th transistor and the first pole plate of described second bootstrap capacitor are connected to described second pull-up joint Point, the first end of described 30th transistor is connected to described second clock signal end, the second end of described 30th transistor It is connected for described second outfan with the second pole plate of described second bootstrap capacitor.

Bilateral scanning unit the most according to claim 1, it is characterised in that described first signal end and secondary signal end The level of the signal of output is contrary, and the signal of described first signal end and the output of secondary signal end is frame reverse signal.

11. bilateral scanning unit according to claim 1, it is characterised in that described bilateral scanning unit also includes: with institute State the first initialization module that the first pull-up node connects, and, the second initialization mould being connected with described second pull-up node Block；

Wherein, described first initialization module controls described first pull-up node and reset in response to the signal of reseting controling end On-state between voltage end, and, described second initialization module controls in response to the signal of described reseting controling end On-state between described second pull-up node and described resetting voltage end.

12. bilateral scanning unit according to claim 11, it is characterised in that described first initialization module includes: the 31 transistors；

The grid of described 31st transistor is connected to described reseting controling end, and the first end of described 31st transistor is even Being connected to described resetting voltage end, the second end of described 31st transistor is connected to described first pull-up node；

And, described second initialization module includes: the 30th two-transistor；

The grid of described 30th two-transistor is connected to described reseting controling end, and the first end of described 30th two-transistor is even Being connected to described resetting voltage end, the second end of described 30th two-transistor is connected to described second pull-up node.

13. bilateral scanning unit according to claim 1, it is characterised in that described bilateral scanning unit also includes: with institute State the first initialization module that the first pull-down node connects, and, the second initialization mould being connected with described second pull-down node Block；

Wherein, described first initialization module controls described first pull-down node with described in response to the signal of reseting controling end On-state between reseting controling end, and, described second initialization module in response to described reseting controling end signal and Control the on-state between described second pull-down node and described reseting controling end.

14. bilateral scanning unit according to claim 13, it is characterised in that described first initialization module includes: the 31 transistors；

The grid of described 31st transistor and the first end are connected to described reseting controling end, described 31st transistor The second end be connected to described first pull-down node；

The grid of described 30th two-transistor and the first end are connected to described reseting controling end, described 30th two-transistor The second end be connected to described second pull-down node.

15. 1 kinds of gate driver circuits, it is characterised in that described gate driver circuit includes that n level bilateral scanning unit is first Level bilateral scanning unit is to n-th grade of bilateral scanning unit, and wherein, every one-level bilateral scanning unit is claim 1～14 Anticipating a described bilateral scanning unit, n is the integer not less than 2.

16. gate driver circuits according to claim 15, it is characterised in that define bilateral scanning list described in adjacent two-stage Unit is i-stage bilateral scanning unit and i+1 level bilateral scanning unit, and i is the positive integer of no more than n；

First outfan of described i-stage bilateral scanning unit controls end phase with the first of described i+1 level bilateral scanning unit Even, the first outfan of described i+1 level bilateral scanning unit controls end phase with the second of described i-stage bilateral scanning unit Even；

Second outfan of described i-stage bilateral scanning unit controls end phase with the 3rd of described i+1 level bilateral scanning unit Even, the second outfan of described i+1 level bilateral scanning unit controls end phase with the 4th of described i-stage bilateral scanning unit Even；

And, the first clock signal terminal of odd level bilateral scanning unit is same signal end and second clock signal end is same One signal end, the first clock signal terminal of even level bilateral scanning unit is same signal end and second clock signal end is same One signal end.