CN106409267B - A kind of scanning circuit, gate driving circuit and display device - Google Patents
A kind of scanning circuit, gate driving circuit and display device Download PDFInfo
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- CN106409267B CN106409267B CN201611168565.6A CN201611168565A CN106409267B CN 106409267 B CN106409267 B CN 106409267B CN 201611168565 A CN201611168565 A CN 201611168565A CN 106409267 B CN106409267 B CN 106409267B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of scanning circuits, gate driving circuit and display device, include two-stage sub-circuit be first order sub-circuit and second level sub-circuit, two-stage sub-circuit exports scanning signal step by step, and first pull-up node, second pull-up node, first pull-down node and the second pull-down node not only control module in the same level sub-circuit and work, module in another grade of sub-circuit of control is also taken into account to work, i.e. by interacting between first order sub-circuit and second level sub-circuit, and keep single sub-circuit operation more stable, and meet the multifarious demand of gate driving circuit.
Description
Technical field
The present invention relates to field of display technology, more specifically, are related to a kind of scanning circuit, gate driving circuit and aobvious
Showing device.
Background technique
With the development of electronic technology, display device has been widely used in each row field and various electronic products, at
A part indispensable with work for people's lives, such as TV, mobile phone, computer, personal digital assistant.Existing display dress
In setting, display device includes gate driving circuit, and gate driving circuit is mainly used for scanning multistage grid line, to pass through scanning
Grid line and the pixel array being electrically connected with grid line is scanned, and then cooperate All other routes structure and carry out the aobvious of picture
Show.Since people are to the multifarious demand of gate driving circuit, gate driving circuit is designed to developer now
One of main research tendency.
Summary of the invention
In view of this, including two-stage the present invention provides a kind of scanning circuit, gate driving circuit and display device
Circuit is first order sub-circuit and second level sub-circuit, and two-stage sub-circuit exports scanning signal step by step, and passes through first order son electricity
It interacts between road and second level sub-circuit, and keeps single sub-circuit operation more stable, and meet gate driving circuit
Multifarious demand.
To achieve the above object, technical solution provided by the invention is as follows:
A kind of scanning circuit, the scanning circuit include first order sub-circuit and second level sub-circuit, wherein described first
Grade sub-circuit includes: the first input module, the first pull-up node, the first pull-up control module, the first pull-down node, the first drop-down
Control module, the first clock control module, the first output module, the first output end, first capacitor and the second capacitor；And institute
Stating second level sub-circuit includes: the second input module, the second pull-up node, the second pull-up control module, the second pull-down node, the
Two pull-down control modules, second clock control module, the second output module, second output terminal, third capacitor and the 4th capacitor；
First input module in response to the signal of the first control terminal control and control first voltage end and described the
On-state between one pull-up node, and, in response to the second control terminal signal and control second voltage end and described the
On-state between one pull-up node, wherein the level of the signal of the first voltage end and the output of second voltage end is opposite；
Second input module in response to third control terminal signal and control the first voltage end and second pull-up node
Between on-state, and, in response to the 4th control terminal signal and control the second voltage end and it is described second pull-up
On-state between node；
Described first, which pulls up control module, controls the first drop-down section in response to the signal of first pull-up node
It puts and second descends the drawknot node on-state between tertiary voltage end respectively；The second pull-up control module is in response to described
The signal of second pull-up node and control second pull-down node and the first pull-down node respectively with the tertiary voltage end it
Between on-state；
First pull-down control module in response to first pull-down node signal and control it is described first pull-up save
Point, the second pull-up node and the first output end on-state between the tertiary voltage end respectively；The second drop-down control
Molding block in response to second pull-down node signal and to control second pull-up node, the first pull-up node and second defeated
The outlet on-state between the tertiary voltage end respectively；
First clock control module in response to the first clock signal terminal signal and control first output end with
On-state between the tertiary voltage end；The second clock control module in response to third clock signal terminal signal and
Control the on-state between the second output terminal and the tertiary voltage end；
First output module in response to first pull-up node signal and control the second clock signal end
With the on-state of first output end；Second output module in response to second pull-up node signal and control
The on-state of 4th clock signal terminal and the second output terminal；
And the first capacitor is used to couple first pull-up node, institute for the signal of first output end
The second capacitor is stated for coupleeing first pull-down node for the signal of the second clock signal end；The third capacitor is used
In coupleeing second pull-up node for the signal of the second output terminal, the 4th capacitor is used for the 4th clock
The signal of signal end is coupled to second pull-down node.
Correspondingly, the gate driving circuit includes N grades of scanning circuits the present invention also provides a kind of gate driving circuit
For first order scanning circuit to N grades of scanning circuits, wherein every level-one scanning circuit is above-mentioned scanning circuit, and N is not small
In 2 integer.
Correspondingly, the display device includes above-mentioned gate driving circuit the present invention also provides a kind of display device.
Compared to the prior art, technical solution provided by the invention has at least the following advantages:
It include two-stage sub-circuit is the present invention provides a kind of scanning circuit, gate driving circuit and display device
Level-one sub-circuit and second level sub-circuit, two-stage sub-circuit export scanning signal, and the first pull-up node, the second pull-up section step by step
Point, the first pull-down node and the second pull-down node not only control module in the same level sub-circuit and work, and also take into account another grade of son of control
Module works in circuit, i.e., by interacting between first order sub-circuit and second level sub-circuit, and makes single son electricity
Road transport row is more stable, and meets the multifarious demand of gate driving circuit.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of invention for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of scanning circuit provided by the embodiments of the present application；
Fig. 2 is the structural schematic diagram of another scanning circuit provided by the embodiments of the present application；
Fig. 3 is a kind of timing diagram along first direction scanning provided by the embodiments of the present application；
Fig. 4 is the timing diagram that one kind provided by the embodiments of the present application scans in a second direction；
Fig. 5 is a kind of structural schematic diagram of gate driving circuit provided by the embodiments of the present application；
Fig. 6 is a kind of structural schematic diagram of display device provided by the embodiments of the present application.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
As described in background, in existing display device, display device includes gate driving circuit, gate driving
Circuit is mainly used for scanning multistage grid line, to be swept by scanning grid line to the pixel array being electrically connected with grid line
It retouches, and then cooperates All other routes structure and carry out the display of picture.Since people are to the multifarious demand of gate driving circuit,
Therefore gate driving circuit is designed to developer's one of main research tendency now.
Based on this, it includes two that the embodiment of the present application, which provides a kind of scanning circuit, gate driving circuit and display device,
Grade sub-circuit is first order sub-circuit and second level sub-circuit, and two-stage sub-circuit exports scanning signal step by step, and passes through the first order
It interacts between sub-circuit and second level sub-circuit, and keeps single sub-circuit operation more stable, and meet gate driving
The multifarious demand of circuit.To achieve the above object, technical solution provided by the embodiments of the present application is as follows, specifically combines Fig. 1
To shown in Fig. 6, concrete scheme provided by the embodiments of the present application is described in detail.
Refering to what is shown in Fig. 1, being a kind of structural schematic diagram of scanning circuit provided by the embodiments of the present application, scanning circuit application
In gate driving circuit, wherein the scanning circuit includes:
First order sub-circuit and second level sub-circuit, wherein the first order sub-circuit include: the first input module 101,
When the first pull-up node P1, the first pull-up control module 201, the first pull-down node Q1, the first pull-down control module 301, first
Clock control module 401, the first output module 501, the first output end Gout1, first capacitor C1 and the second capacitor C2；
And the second level sub-circuit includes: the second input module 102, the second pull-up node P2, the second pull-up control
Module 202, the second pull-down node Q2, the second pull-down control module 302, second clock control module 402, the second output module
502, second output terminal Gout2, third capacitor C3 and the 4th capacitor C4；
First input module 101 in response to the signal of the first control terminal SET1 control and control first voltage end
On-state between DIR1 and the first pull-up node P1, and, in response to the second control terminal RESET1 signal and control
On-state between second voltage end DIR2 processed and the first pull-up node P1, wherein the first voltage end DIR1 and
The level of the signal of second voltage end DIR2 output is opposite；Second input module 102 is in response to third control terminal SET2's
Signal and control the on-state between the first voltage end DIR1 and the second pull-up node P2, and, in response to
The signal of four control terminal RESET2 and control the connection shape between the second voltage end DIR2 and the second pull-up node P2
State；
Described first pulls up control module 201 controls under described first in response to the signal of the first pull-up node P1
Draw the lower drawknot node of node Q1 and second on-state between the V3 of tertiary voltage end respectively；The second pull-up control module
202 in response to the second pull-up node P2 signal and control the second pull-down node Q2 and the first pull-down node Q1 and distinguish
With the on-state between the tertiary voltage end V3；
First pull-down control module 301 in response to the first pull-down node Q1 signal and control on described first
Draw node P1, the second pull-up node P2 and the first output end Gout1 on-state between the tertiary voltage end V3 respectively；
Second pull-down control module 302 in response to the second pull-down node Q2 signal and control second pull-up node
P2, the first pull-up node P1 and second output terminal the Gout2 on-state between the tertiary voltage end V3 respectively；
First clock control module 401 in response to the first clock signal terminal CK1 signal and to control described first defeated
On-state between outlet Gout1 and the tertiary voltage end V3；When the second clock control module 402 is in response to third
The signal of clock signal end CK2 and control the on-state between the second output terminal Gout2 and the tertiary voltage end V3；
First output module 501 in response to the first pull-up node P1 signal and control the second clock and believe
Number end CKB1 and the first output end Gout1 on-state；Second output module 502 is in response to second pull-up
The signal of node P2 and the on-state for controlling the 4th clock signal terminal CKB2 and the second output terminal Gout2；
And the first capacitor C1 is used to couple the signal of the first output end Gout1 to first pull-up
Node P1, the second capacitor C2 are for coupleeing first pull-down node for the signal of the second clock signal end CKB1
Q1；The third capacitor C3 is used to couple the second pull-up node P2 for the signal of the second output terminal Gout2, described
4th capacitor C4 is used to couple the second pull-down node Q2 for the signal of the 4th clock signal terminal CKB2.
Scanning circuit provided by the embodiments of the present application comprising having two-stage sub-circuit is first order sub-circuit and second level
Circuit, two-stage sub-circuit export scanning signal, and the first pull-up node, the second pull-up node, the first pull-down node and step by step
Two pull-down nodes not only control module in the same level sub-circuit and work, and also take into account module in another grade of sub-circuit of control and work,
I.e. by interacting between first order sub-circuit and second level sub-circuit, and keep single sub-circuit operation more stable, and
Meet the multifarious demand of gate driving circuit.
As shown in connection with fig. 2, detailed to a kind of structure progress of specific scanning circuit provided by the embodiments of the present application to retouch
It states.Wherein, Fig. 2 is the structural schematic diagram of another scanning circuit provided by the embodiments of the present application.
Refering to what is shown in Fig. 2, in one embodiment of the application, first input module 101 include: the first transistor M1 and
Second transistor M2；
Wherein, the grid of the first transistor M1 is connected to the first control terminal SET1, the first transistor M1
First end be connected to the first voltage end DIR1, the second end of the first transistor M1 is connected to the first pull-up section
Point P1, the grid of the second transistor M2 are connected to the second control terminal RESET1, and the first of the second transistor M2
End is connected to the second voltage end DIR2, and the second end of the second transistor M2 is connected to the first pull-up node P1.
In order to easy to make, in one embodiment of the application, the electricity of the first input module 101 and the second input module 102
Line structure can be designed as identical circuit structure, that is, second input module 102 includes: the tenth transistor M10 and the tenth
One transistor M11；
Wherein, the grid of the tenth transistor M10 is connected to the third control terminal SET2, the tenth transistor
The first end of M10 is connected to the first voltage end DIR1, and the second end of the tenth transistor M10 is connected on described second
Node P2 is drawn, the grid of the 11st transistor M11 is connected to the 4th control terminal RESET2, the 11st transistor
The first end of M11 is connected to the second voltage end DIR2, and the second end of the 11st transistor M11 is connected to described second
Pull-up node P2.
In addition, in the application other embodiments, the circuit structure of the first input module 101 and the second input module 102
It can also be different circuit structures, this application is not particularly limited, needs specifically to be designed according to practical application.
It should be noted that the conducting class of the first transistor M1 and second transistor M2 that the embodiment of the present application preferably provides
Type is identical；And the tenth transistor M10 and the 11st transistor M11 conductivity type it is identical.In addition, implementing in the application one
In example, due to needing the signal by the first pull-up node P1 and the second pull-up node P2 to define, thus for the first input module
For 101, when being connected between the first control terminal SET1 control the first pull-up node P1 and first voltage end DIR1, the second control
End RE SET1 cannot be controlled simultaneously to be connected between the first pull-up node P1 and second voltage end DIR2, and, in the second control terminal
When connecting between RESET1 control the first pull-up node P1 and second voltage end DIR2, the first control terminal SET1 cannot be controlled simultaneously
It is connected between first pull-up node P1 and first voltage end DIR1；Likewise, for the second input module 102, in third
When connecting between control terminal SET2 control the second pull-up node P2 and first voltage end DIR1, the 4th control terminal RESET2 cannot be same
When control and connected between the second pull-up node P2 and second voltage end DIR2, and, control second in the 4th control terminal RESET2
When connecting between pull-up node P2 and second voltage end DIR1, third control terminal SET2 cannot control the second pull-up node P2 simultaneously
It is connected between the DIR1 of first voltage end.That is, the first transistor M1 and second transistor M2 cannot be simultaneously turned on, with
And the tenth transistor M10 and the 11st transistor M11 cannot equally simultaneously turn on.
It, can be in addition, the signal of tertiary voltage end V3 provided by the embodiments of the present application output can be high level signal
For low level signal, this needs is specifically designed according to practical application, mainly meets the signal of tertiary voltage end V3 output
For that cannot scan grid line (i.e. the signal cannot be scanned pixel array connected to the gate line) and not can control and the
The transistor turns that three voltage end V3 are directly or indirectly connected to.
Refering to what is shown in Fig. 2, the first pull-up control module 201 provided by the embodiments of the present application includes: third transistor
M3 and the 4th transistor M4；
Wherein, the grid of the third transistor M3 is connected to the first pull-up node P1, the third transistor M3
First end be connected to the tertiary voltage end V3, the second end of the third transistor M3 is connected to first pull-down node
Q1, the grid of the 4th transistor M4 are connected to the first pull-up node P1, and the first end of the 4th transistor M4 connects
It is connected to the tertiary voltage end V3, the second end of the 4th transistor M4 is connected to the second pull-down node Q2.
In order to easy to make, in one embodiment of the application, the first pull-up control module 201 and the second pull-up control module
202 circuit structure can be designed as identical circuit structure, that is, the second pull-up control module 202 includes: the 12nd crystalline substance
Body pipe M12 and the 13rd transistor M13；
Wherein, the grid of the tenth two-transistor M12 is connected to the second pull-up node P2, the 12nd crystal
The first end of pipe M12 is connected to the tertiary voltage end V3, and the second end of the tenth two-transistor M12 is connected to described second
Pull-down node Q2, the grid of the 13rd transistor M13 are connected to the second pull-up node P2, the 13rd transistor
The first end of M13 is connected to the tertiary voltage end V3, and the second end of the 13rd transistor M13 is connected under described first
Draw node Q1.
In addition, the first pull-up control module 201 and second pulls up control module 202 in the application other embodiments
Circuit structure can also be different circuit structures, be not particularly limited to this application, need to be carried out according to practical application specific
Design.
It should be noted that the conducting class of third transistor M3 and the 4th transistor M4 that the embodiment of the present application preferably provides
Type is identical；And the tenth two-transistor M12 and the 13rd transistor M13 conductivity type it is identical.
Refering to what is shown in Fig. 2, first pull-down control module 301 provided by the embodiments of the present application includes: the 5th transistor
M5, the 6th transistor M6 and the 7th transistor M7；
Wherein, the grid of the 5th transistor M5 is connected to the first pull-down node Q1, the 5th transistor M5
First end be connected to the tertiary voltage end V3, the second end of the 5th transistor M5 is connected to first pull-up node
P1, the grid of the 6th transistor M6 are connected to the first pull-down node Q1, and the first end of the 6th transistor M6 connects
It is connected to the tertiary voltage end V3, the second end of the 6th transistor M6 is connected to the second pull-up node P2, and described
The grid of seven transistor M7 is connected to the first pull-down node Q1, and the first end of the 7th transistor M7 is connected to described
Three voltage end V3, the second end of the 7th transistor M7 are connected to the first output end Gout1.
In order to easy to make, in one embodiment of the application, the first pull-down control module 301 and the second pull-down control module
302 circuit structure can be designed as identical circuit structure, that is, second pull-down control module 302 includes: the 14th crystalline substance
Body pipe M14, the 15th transistor M15 and the 16th transistor M16；
Wherein, the grid of the 14th transistor M14 is connected to the second pull-down node Q2, the 14th crystal
The first end of pipe M14 is connected to the tertiary voltage end V3, and the second end of the 14th transistor M14 is connected to described second
Pull-up node P2, the grid of the 15th transistor M15 are connected to the second pull-down node Q2, the 15th transistor
The first end of M15 is connected to the tertiary voltage end V3, and the second end of the 15th transistor M15 is connected on described first
Node P1 is drawn, the grid of the 16th transistor M16 is connected to the second pull-down node Q2, the 16th transistor
The first end of M16 is connected to the tertiary voltage end V3, and the second end of the 16th transistor M16 is connected to described second
Output end Gout2.
In addition, in the application other embodiments, the first pull-down control module 301 and the second pull-down control module 302
Circuit structure is also designed to different circuit structures, is not particularly limited to this application, need according to practical application into
The specific design of row.
It should be noted that the 5th transistor M5, the 6th transistor M6 and the 7th that are preferably provided in the embodiment of the present application
The conductivity type of transistor M7 is identical；And the 14th transistor M14, the 15th transistor M15 and the 16th transistor M16
Conductivity type it is identical.
Refering to what is shown in Fig. 2, first clock control module 401 provided by the embodiments of the present application includes: the 8th transistor
M8；
Wherein, the grid of the 8th transistor M8 is connected to the first clock signal terminal CK1, the 8th transistor
The first end of M8 is connected to the tertiary voltage end V3, and the second end of the 8th transistor M8 is connected to first output end
Gout1。
In order to easy to make, in one embodiment of the application, the first clock control module 401 and second clock control module
402 circuit structure can be designed as identical circuit structure, that is, the second clock control module 402 includes: the 17th crystalline substance
Body pipe M17；
Wherein, the grid of the 17th transistor M17 is connected to the third clock signal terminal CK2, and the described 17th
The first end of transistor M17 is connected to the tertiary voltage end V3, and the second end of the 17th transistor M17 is connected to described
Second output terminal Gout2.
In addition, in the application other embodiments, the first clock control module 401 and second clock control module 402
Circuit structure is also designed to different circuit structures, is not particularly limited to this application, need according to practical application into
The specific design of row.
Refering to what is shown in Fig. 2, first output module 501 provided by the embodiments of the present application includes: the 9th transistor M9；
Wherein, the grid of the 9th transistor M9 is connected to the first pull-up node P1, the 9th transistor M9
First end be connected to the second clock signal end CKB1, it is defeated that the second end of the 9th transistor M9 is connected to described first
Outlet Gout1.
In order to easy to make, in one embodiment of the application, the electricity of the first output module 501 and the second output module 502
Line structure can be designed as same circuits structure, that is, second output module 502 includes: the 18th transistor M18；
Wherein, the grid of the 18th transistor M18 is connected to the second pull-up node P2, the 18th crystal
The first end of pipe M18 is connected to the third clock signal terminal CK2, and the second end of the 18th transistor M18 is connected to institute
State second output terminal Gout2.
In addition, in the application other embodiments, the circuit structure of the first output module 501 and the second output module 502
Different circuit structures are also designed to, this application is not particularly limited, need specifically to be designed according to practical application.
In order to guarantee that first capacitor C1 can couple the first pull-up node P1 for the signal of the first output end Gout1, and
In order to guarantee that the second capacitor C2 can couple the first pull-down node Q1 for the signal of second clock signal end CKB1, with reference to Fig. 2
Shown, the first pole plate of the first capacitor C1 provided by the embodiments of the present application is connected to the first output end Gout1, described
The second pole plate of first capacitor C1 is connected to the first pull-up node P1, and the first pole plate of the second capacitor C2 is connected to institute
Second clock signal end CKB1 is stated, the second pole plate of the second capacitor C2 is connected to the first pull-down node Q1.
And in order to guarantee that third capacitor C3 can couple the second pull-up node for the signal of second output terminal Gout2
P2, and in order to guarantee that the 4th capacitor C4 can couple the second pull-down node Q2 for the signal of the 4th clock signal terminal CKB2, this
The first pole plate for the third capacitor C3 that application embodiment provides is connected to the second output terminal Gout2, the third electricity
The second pole plate for holding C3 is connected to the second pull-up node P2, and the first pole plate of the 4th capacitor C4 is connected to the described 4th
Clock signal terminal CKB2, the second pole plate of the 4th capacitor C4 are connected to the second pull-down node Q2.
In practical applications, since gate driving circuit includes multistage scanning circuit provided by the above embodiment, it is
Guarantee that gate driving circuit can be realized the purpose for exporting scanning signal step by step, in scanning circuit provided by the embodiments of the present application
In, within the same clock cycle, the second clock signal end CKB1, the 4th clock signal terminal CKB2, the first clock signal terminal
The phase of the clock signal of CK1 and third clock signal terminal CK2 output successively lags.Wherein, for the specific number of phases of lag
Value, the embodiment of the present application are not particularly limited, need specifically to be designed according to practical application.
In addition, scanning circuit provided by the embodiments of the present application is preferably capable realizing the scanning circuit of bilateral scanning, so that
The gate driving circuit being made of the scanning circuit, can be realized forward scan and reverse scan.Wherein, it is swept along first direction
When retouching, the first order sub-circuit exports scanning signal prior to the second level sub-circuit；And it is scanning in a second direction
When, the second level sub-circuit exports the scanning signal prior to the first order sub-circuit.It should be noted that for first
Direction and second direction and forward and reverse corresponding relationship, the embodiment of the present application are not particularly limited.
Below with reference to driving method to all modules and comprising modules of scanning circuit provided by the embodiments of the present application
Each transistor connection and cut-off situation be further described.It should be noted that having below with high level signal
The scanning circuit of effect is described, that is, carries out so that the first transistor M1 to the 18th transistor M18 is N-type transistor as an example
Illustrate, and, using the output signal of tertiary voltage end V3 as low level, the first output end Gout1 of scanning circuit and second is defeated
The output signal of outlet Gout2 be high level for be illustrated.
In conjunction with shown in Fig. 1, Fig. 2, Fig. 3 and Fig. 4, driving method provided by the embodiments of the present application is described in detail,
In, driving method provided by the embodiments of the present application, applied to above-mentioned scanning circuit, and driving method include: first stage T1,
Second stage T2, phase III T3 and fourth stage T4.
Refering to what is shown in Fig. 3, for a kind of timing diagram along first direction scanning provided by the embodiments of the present application, that is, along first
Grade sub-circuit to second level sub-circuit is scanned, wherein the output signal of first voltage end DIR1 is high level, second voltage
The output signal for holding DIR2 is low level, when being scanned along first order sub-circuit to second level sub-circuit:
T1 in the first stage, the first input module 101 and control first voltage in response to the signal of the first control terminal SET1
It is connected between the DIR1 and the first pull-up node P1 of end, so that the signal of the first pull-up node P1 is first voltage end DIR1 output
High level；Wherein, first pull-up control module 201 in response to the first pull-up node P1 signal and control the first pull-down node Q1
And second pull-down node Q2 connected between the V3 of tertiary voltage end respectively；First clock control module 401 responds the first clock letter
The signal of number CK1, and control and connected between tertiary voltage end V3 and the first output end Gout1；First output module 501 in response to
The signal of first pull-up node P1 and control and connected between second clock signal end CKB1 and the first output end Gout1.
It specifically combines shown in Fig. 2 and Fig. 3, T1 in the first stage, the first control terminal SET1 export high level, and then control the
One transistor M1 conducting, so that the signal of the first pull-up node P1 is the high level of first voltage end DIR1 output；First pull-up
Node P1 controls third transistor M3 and the 4th transistor M4 conducting, so that the first pull-down node Q1 and the second pull-down node Q2
Signal is the low level of tertiary voltage end V3 output；And first pull-up node P1 control the 9th transistor M9 conducting, the 9th
The second clock signal end CKB1 low level exported is transmitted to the first output end Gout1 by transistor M9；In addition, the first clock is believed
Number end CK1 output be high level, and then control the 8th transistor M8 conducting, while by tertiary voltage end V3 output low level pass
Transport to the first output end Gout1.
In second stage T2, the first output module 501 and controls second clock in response to the signal of the first pull-up node P1
It is connected between signal end CKB1 and the first output end Gout1, and second clock signal end CKB1 output signal is scanning letter
Number；And second input module 102 in response to the signal of third control terminal SET2, and control first voltage end DIR1 and second
It is connected between pull-up node P2；Wherein, first control module 201 is pulled up in response to the signal of the first pull-up node P1, and control
First pull-down node Q1 and the second pull-down node Q2 are connected between the V3 of tertiary voltage end respectively；Second pull-up control module 202
In response to the signal of the second pull-up node P2, and control the second pull-down node Q2 and the first pull-down node Q1 respectively with tertiary voltage
It is connected between the V3 of end；Second clock control module 402 and controls tertiary voltage in response to the signal of third clock signal terminal CK2
It is connected between the V3 and second output terminal Gout2 of end；Second output module 502 and is controlled in response to the signal of the second pull-up node P2
It makes and is connected between the 4th clock signal terminal CKB2 and the second output terminal Gout2.
It specifically combines shown in Fig. 2 and Fig. 3, in second stage T2, the 9th transistor M9 is by second clock signal end at this time
The high level (i.e. scanning signal) of CKB1 output is transmitted to a pole plate of the first output end Gout1 and first capacitor C1, and first is defeated
Outlet Gout1 is scanned the grid line that it is accordingly connected, and first capacitor C1 saves the first pull-up for connecting another pole plate
The signal of point P1 is drawn high again.Due to the first pull-up node P1 signal be higher high level, thus with the first pull-up node
The transistor of P1 connection keeps the state of T1 in the first stage constant.In addition, third control terminal SET2 is same in second stage T2
Sample output is high level signal, and controls the tenth transistor M10 conducting, so that the signal of the second pull-up node P2 is first voltage
Hold the high level of DIR1 output；Second pull-up node P2 controls the tenth two-transistor M12 and the 13rd transistor M13 conducting, makes
The low level for obtaining tertiary voltage end V3 output is transmitted separately to the second pull-down node Q2 and the first pull-down node Q1, so that under first
Draw the signal of node Q1 and the second pull-down node Q2 more stable；And second pull-up node P2 also control the 18th transistor M18
Conducting, so that the 18th transistor M18 transmits the low level of the 4th clock signal terminal CKB2 output to second output terminal Gout2；
And the 17th transistor M17 also by third clock signal terminal CK2 high level control conducting so that tertiary voltage end V3 is defeated
Low level out is transmitted to second output terminal Gout2, so that the signal of second output terminal Gout2 is more stable.
In phase III T3, the second output module 502 and controls the 4th clock in response to the signal of the second pull-up node P2
It is connected between signal end CKB2 and second output terminal Gout2, and the 4th clock signal terminal CKB2 output signal is scanning signal；With
And first input module 101 is in response to the signal of the second control terminal RESET1, and control second voltage end DIR2 and first
It is connected between pull-up node P1；Second pulls up control module 202 in response to the signal of the second pull-up node P2, and controls under second
Node Q2 and the first pull-down node Q1 is drawn to connect between the tertiary voltage end V3 respectively；First clock control module, 401 sound
It should control and be connected between tertiary voltage end V3 and the first output end Gout1 in the signal of the first clock signal terminal CK1.
It specifically combines shown in Fig. 2 and Fig. 3, in phase III T3, the 18th transistor M18 is by the 4th clock signal terminal at this time
The high level (i.e. scanning signal) of CKB2 output is transmitted to a pole plate of second output terminal Gout2 and third capacitor C3, and second is defeated
Gout2 pairs of outlet grid line connected corresponding to its is scanned, and third capacitor C3 will connect the second pull-up of another pole plate
The signal of node P2 is drawn high again.Since the signal of the second pull-up node P2 is higher high level, thus saved with the second pull-up
The state that the transistor of point P2 connection is maintained at second stage T2 is constant.In addition, in phase III T3, the second control terminal
RESET1 exports high level, and controls second transistor M2 conducting, so that the signal of the first pull-up node P1 is second voltage end
The low level of DIR2 output, at this point, being off state with the first pull-up node P1 transistor being connected to；And the 8th crystal at this time
Pipe M8 is connected according to the control of the high level of the first clock signal terminal CK1, transmission tertiary voltage end V3 low level to the first output
Hold Gout1.
In fourth stage T4, the second input module 102 and controls the second electricity in response to the signal of the 4th control terminal RESET2
It is connected between pressure side DIR2 and the second pull-up node P2；The high level coupling that second capacitor C2 exports second clock signal end CKB1
It is bonded to the first pull-down node Q1；First pull-down control module 301 in response to the first pull-down node Q1 signal, and control first on
Node P1, the second pull-up node P2 and the first output end Gout1 is drawn to connect respectively with tertiary voltage end V3.
Specifically shown referring to figs. 2 and 3, in fourth stage T4, the 4th control terminal RESET2 exports high level, and controls
11st transistor M11 conducting, so that the signal of the second pull-up node P2 is the low level signal of second voltage end DIR2 output；
Due to the first pull-up node P1 and the second pull-up node P2 transistor connecting being off state in fourth stage T4, because
And the second clock signal end CKB1 high level exported is couple the first pull-down node Q1 by the second capacitor C2, in turn, under first
It draws node Q1 to control the 5th transistor M5, the 6th transistor M6 and the 7th transistor M7 conducting, and then transmits tertiary voltage respectively
Hold the low level of V3 to the first pull-up node P1, the second pull-up node P2 and the first output end Gout1, so that the second pull-up node
The low level of P2 and the first pull-up node P1 are more stable.
Wherein, after fourth stage T4, since second clock signal end CKB1 and the 4th clock signal terminal CKB2 alternating is defeated
High level out, after capacitive coupling, so that the first pull-down node Q1 and the second pull-down node Q2 are alternately high level respectively, into
And the first pull-up node P1 of control and the second pull-up node P2 can be continued by control respective transistor and keep low level, with
Complete period control is carried out to the first pull-up node P1 and the second pull-up node P2, so that scanning circuit is more stable.
And refering to what is shown in Fig. 4, the timing diagram scanned in a second direction for one kind provided by the embodiments of the present application, that is, edge
Second level sub-circuit to first order sub-circuit is scanned, at this point, first voltage end DIR1 and second voltage end DIR2 output
Signal inversion, i.e. first voltage end DIR1 export low level signal, and second voltage end DIR2 exports high level signal, wherein
When being scanned along the second level sub-circuit to first order sub-circuit:
T1 in the first stage, the second input module 102 and control described in response to the signal of the 4th control terminal RESET2
It is connected between two voltage end DIR2 and the second pull-up node P2, so that the signal of the second pull-up node P2 is second voltage end
The high level of DIR2 output；Wherein, the second pull-up control module 202 and controls the in response to the signal of the second pull-up node P2
Two pull-down node Q2 and the first pull-down node Q1 are connected between the V3 of tertiary voltage end respectively；402 sound of second clock control module
It should control and be connected between tertiary voltage end V3 and second output terminal Gout2 in the signal of third clock signal terminal CK2；Second
Output module 502 in response to the second pull-up node P2 signal, and control the 4th clock signal terminal CKB2 and it is described second output
It is connected between the Gout2 of end.
It specifically combining shown in Fig. 2 and Fig. 4, in the first stage T1, the 4th control terminal RESET2 output is high level signal, and
The 11st transistor M11 conducting is controlled, so that the signal of the second pull-up node P2 is the high level of second voltage end DIR2 output；
Second pull-up node P2 controls the tenth two-transistor M12 and the 13rd transistor M13 conducting, so that tertiary voltage end V3 output
Low level is transmitted separately to the second pull-down node Q2 and the first pull-down node Q1；And second pull-up node P2 also control the 18th crystalline substance
Body pipe M18 conducting, so that the 18th transistor M18 transmits the low level of the 4th clock signal terminal CKB2 output to second output terminal
Gout2；And the 17th transistor M17 also by third clock signal terminal CK2 high level control conducting so that tertiary voltage
The low level of end V3 output is transmitted to second output terminal Gout2, so that the signal of second output terminal Gout2 is more stable.
In second stage T2, the second output module 502 and controls the 4th clock in response to the signal of the second pull-up node P2
It is connected between signal end CKB2 and second output terminal Gout2, and the 4th clock signal terminal CKB2 output signal is scanning signal；With
And first input module 101 is in response to the signal of the second control terminal RESET1, and control second voltage end DIR2 and first
It is connected between pull-up node P1；Second pulls up control module 202 in response to the signal of the second pull-up node P2, and controls under second
Node Q2 and the first pull-down node Q1 is drawn to connect between the tertiary voltage end V3 respectively；First pull-up 201 sound of control module
Should in the signal of the first pull-up node P1, and control the first pull-down node Q1 and the second pull-down node Q2 respectively with tertiary voltage end
It is connected between V3；First clock control module 401 and controls tertiary voltage end in response to the signal of the first clock signal terminal CK1
It is connected between V3 and the first output end Gout1；And first output module 501 in response to the first pull-up node P1 signal, and
It is connected between control second clock signal end CKB1 and the first output end Gout1.
It specifically combines shown in Fig. 2 and Fig. 4, in second stage T2, the 18th transistor M18 is by the 4th clock signal terminal at this time
The high level (i.e. scanning signal) of CKB2 output is transmitted to a pole plate of second output terminal Gout2 and third capacitor C3, and second is defeated
Gout2 pairs of outlet grid line connected corresponding to its is scanned, and third capacitor C3 will connect the second pull-up of another pole plate
The signal of node P2 is drawn high again.Since the signal of the second pull-up node P2 is higher high level, thus saved with the second pull-up
The state that the transistor of point P2 connection is maintained at second stage T2 is constant.In addition, in second stage T2, the second control terminal
RESET1 exports high level, and controls second transistor M2 conducting, so that the signal of the first pull-up node P1 is second voltage end
The high level of DIR2 output, at this point, the first pull-up node P1 control third transistor M3 and the 4th transistor M4 conducting, so that the
The signal of one pull-down node Q1 and the second pull-down node Q2 are the low level of tertiary voltage end V3 output, so that the first drop-down section
The signal of point Q1 and the second pull-down node Q2 are more stable；And first pull-up node P1 control the 9th transistor M9 conducting, the
The second clock signal end CKB1 low level exported is transmitted to the first output end Gout1 by nine transistor M9；And it is the 8th brilliant at this time
Body pipe M8 is connected according to the control of the high level of the first clock signal terminal CK1, and transmission tertiary voltage end V3 low level is to first defeated
Outlet Gout1, so that the signal of the first output end Gout1 is more stable.
In phase III T3, the first output module 501 and controls second clock in response to the signal of the first pull-up node P1
It is connected between signal end CKB1 and the first output end Gout1, and second clock signal end CKB1 output signal is scanning letter
Number；And second input module 102 in response to the signal of third control terminal SET2, and control first voltage end DIR1 and second
It is connected between pull-up node P2；First pulls up control module 201 in response to the signal of the first pull-up node P1, and controls under first
Node Q1 and the second pull-down node Q2 is drawn to connect between the V3 of tertiary voltage end respectively；Second clock control module 402 in response to
The signal of third clock signal terminal CK2, and control and connected between tertiary voltage end V3 and second output terminal.
It specifically combines shown in Fig. 2 and Fig. 4, in phase III T3, the 9th transistor M9 is by second clock signal end at this time
The high level (i.e. scanning signal) of CKB1 output is transmitted to a pole plate of the first output end Gout1 and first capacitor C1, and first is defeated
Outlet Gout1 is scanned the grid line that it is accordingly connected, and first capacitor C1 saves the first pull-up for connecting another pole plate
The signal of point P1 is drawn high again.Due to the first pull-up node P1 signal be higher high level, thus with the first pull-up node
The transistor of P1 connection keeps the state of T1 in the first stage constant.In addition, third control terminal SET2 is same in phase III T3
Sample output is high level signal, and controls the tenth transistor M10 conducting, so that the signal of the second pull-up node P2 is first voltage
The low level for holding DIR1 output, at this point, being off state with the second pull-up node P2 transistor being connected to；And at this time the 17th
Transistor M17 controls conducting by the high level of third clock signal terminal CK2, so that the low level transmission of tertiary voltage end V3 output
To second output terminal Gout2.
In fourth stage T4, the first input module 101 and controls first voltage in response to the signal of the first control terminal SET1
It is connected between the DIR1 and the first pull-up node P1 of end；The high level that 4th capacitor C4 exports the 4th clock signal terminal CKB2 couples
To the second pull-down node Q2；Second pull-down control module 302 in response to the second pull-down node Q2 signal, and control second pull-up
Node P2, the first pull-up node P1 and second output terminal Gout2 are connected with tertiary voltage end V3 respectively.
Specifically with reference to shown in Fig. 2 and Fig. 4, high level is exported in fourth stage T4, the first control terminal SET1, and controls the
One transistor M1 conducting, so that the signal of the first pull-up node P1 is the low level of first voltage end DIR1 output；Due to
It with the first pull-up node P1 and the second pull-up node P2 transistor connecting is off state when four stage T4, thus, the 4th
The 4th clock signal terminal CKB2 high level exported is couple the second pull-down node Q2 by capacitor C4, in turn, the second pull-down node
Q2 controls the 14th transistor M14, the 15th transistor M15 and the 16th transistor M16 conducting, and then transmits third electricity respectively
The low level of pressure side V3 is to the second pull-up node P2, the first pull-up node P1 and second output terminal Gout2, so that the second pull-up section
The low level of point P2 and the first pull-up node P1 are more stable.
Wherein, after fourth stage T4, since second clock signal end CKB1 and the 4th clock signal terminal CKB2 alternating is defeated
High level out, after capacitive coupling, so that the first pull-down node Q1 and the second pull-down node Q2 are alternately high level respectively, into
And the first pull-up node P1 of control and the second pull-up node P2 can be continued by control respective transistor and keep low level, with
Complete period control is carried out to the first pull-up node P1 and the second pull-up node P2, so that scanning circuit is more stable.
In addition, the gate driving circuit includes N grades of scannings the embodiment of the present application also provides a kind of gate driving circuit
Circuit is first order scanning circuit to N grades of scanning circuits, wherein every level-one scanning circuit is above-mentioned any one embodiment institute
The scanning circuit stated, N are the integer not less than 2.
Wherein, refering to what is shown in Fig. 5, being a kind of structural schematic diagram of gate driving circuit provided by the embodiments of the present application,
In, defining adjacent two-stage scan circuit is i-stage scanning circuit 1i and i+1 grade scanning circuit 1 (i+1), and i is no more than N's
Positive integer；
Wherein, the first output end Gout1 of the i-stage scanning circuit 1i and the i+1 grade scanning circuit 1 (i+1)
The first control terminal SET1 be connected, the first output end Gout1 of the i+1 grade scanning circuit 1 (i+1) is swept with the i-stage
The second control terminal RESET1 of scanning circuit 1i is connected；
The third of the second output terminal Gout2 of the i-stage scanning circuit 1i and the i+1 grade scanning circuit 1 (i+1)
Control terminal SET2 is connected, the second output terminal Gout2 and the i-stage scanning circuit of the i+1 grade scanning circuit 1 (i+1)
The 4th control terminal RESET2 of 1i is connected.
Further, in order to save line, refering to what is shown in Fig. 5, in one embodiment of the application, odd level scanning circuit
First clock signal terminal CK1 is same signal end, second clock signal end CKB1 is same signal end, third clock signal terminal
CK2 is same signal end, the 4th clock signal terminal CKB2 is same signal end；And the first clock of even level scanning circuit
Signal end CK1 is same signal end, second clock signal end CKB1 is same signal end, third clock signal terminal CK2 is same
Signal end, the 4th clock signal terminal CKB2 are same signal end.
And in one embodiment of the application, the first clock signal terminal CK1 of odd level scanning circuit can be with even level
The third clock signal terminal CK2 of scanning circuit is same signal end；The second clock signal end CKB1 of odd level scanning circuit can
With with the 4th clock signal terminal CKB2 of even level scanning circuit be same signal end.
It should be noted that, in forward scan, the first order is swept in gate driving circuit provided by the embodiments of the present application
The the first control terminal SET1 and third control terminal SET2 of scanning circuit pass through outer signal line and provide initial control signal；With
And in reverse scan, the second control terminal RESET1 and the 4th control terminal RESET2 of N grades of scanning circuits pass through external
Signal wire provides initial control signal.In one embodiment of the application, the first control terminal SET1 of first order scanning circuit and
The external signal wire for providing initial control signal of 4th control terminal RESET2 of N grades of scanning circuits can be same signal
Line；And the second control terminal SET2 of the first order scanning circuit and third control terminal RESET1 of N grades of scanning circuits is external mentions
Signal wire for initial control signal can be same signal wire.
And in practical applications, since gate driving circuit includes multistage scanning provided by the above embodiment electricity
It is swept to guarantee that gate driving circuit can be realized the purpose of output scanning signal step by step provided by the embodiments of the present application on road
In scanning circuit, within the same clock cycle, the second clock signal end CKB1, the 4th clock signal terminal CKB2, the first clock
The phase of the clock signal of signal end CK1 and third clock signal terminal CK2 output successively lags.Wherein, for the specific of lag
Phase number, the embodiment of the present application are not particularly limited, and need specifically to be designed according to practical application.
Finally, the embodiment of the present application also provides a kind of display device, with specific reference to shown in Fig. 6, being the embodiment of the present application
The structural schematic diagram of a kind of display device provided, wherein the display device includes that there is above-mentioned any one embodiment to provide
Gate driving circuit display panel 10；
And when display device is liquid crystal display device, display device further includes providing backlight for display panel 10
The backlight source module 20 of (as shown by arrows).
It should be noted that the application is not particularly limited the type of the display device of offer, such as the application its
In his embodiment, display device can also be organic light-emitting display device.
The embodiment of the present application provides a kind of scanning circuit, gate driving circuit and display device, includes two-stage son electricity
Road is first order sub-circuit and second level sub-circuit, and two-stage sub-circuit exports scanning signal, and the first pull-up node, second step by step
Pull-up node, the first pull-down node and the second pull-down node not only control module in the same level sub-circuit and work, and it is another also to take into account control
Module works in level-one sub-circuit, i.e., by interacting between first order sub-circuit and second level sub-circuit, and makes list
A sub-circuit operation is more stable, and meets the multifarious demand of gate driving circuit.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (19)
1. a kind of scanning circuit, which is characterized in that the scanning circuit includes first order sub-circuit and second level sub-circuit,
In, the first order sub-circuit includes: the first input module, the first pull-up node, the first pull-up control module, the first drop-down section
Point, the first pull-down control module, the first clock control module, the first output module, the first output end, first capacitor and the second electricity
Hold；And the second level sub-circuit includes: the second input module, the second pull-up node, the second pull-up control module, second
Pull-down node, the second pull-down control module, second clock control module, the second output module, second output terminal, third capacitor and
4th capacitor；
First input module in response to the signal of the first control terminal control and control on first voltage end and described first
Draw node between on-state, and, in response to the second control terminal signal and control on second voltage end and described first
Draw the on-state between node, wherein the level of the signal of the first voltage end and the output of second voltage end is opposite；It is described
Second input module in response to third control terminal signal and control between the first voltage end and second pull-up node
On-state, and, in response to the 4th control terminal signal and control the second voltage end and second pull-up node
Between on-state；
It is described first pull-up control module in response to first pull-up node signal and control first pull-down node and
Second descends the drawknot node on-state between tertiary voltage end respectively；The second pull-up control module is in response to described second
The signal of pull-up node and control second pull-down node and the first pull-down node respectively between the tertiary voltage end
On-state；
First pull-down control module in response to first pull-down node signal and control first pull-up node,
Two pull-up nodes and the first output end on-state between the tertiary voltage end respectively；Second pull-down control module
In response to second pull-down node signal and control second pull-up node, the first pull-up node and second output terminal point
On-state not between the tertiary voltage end；
First clock control module in response to the first clock signal terminal signal and control first output end with it is described
On-state between tertiary voltage end；The second clock control module in response to third clock signal terminal signal and control
On-state between the second output terminal and the tertiary voltage end；
First output module in response to first pull-up node signal and control second clock signal end and described the
The on-state of one output end；Second output module in response to second pull-up node signal and control the 4th clock
The on-state of signal end and the second output terminal；
And the first capacitor is used to couple first pull-up node for the signal of first output end, described the
Two capacitors are used to couple first pull-down node for the signal of the second clock signal end；The third capacitor is used for will
The signal of the second output terminal is coupled to second pull-up node, and the 4th capacitor is used for the 4th clock signal
The signal at end is coupled to second pull-down node.
2. scanning circuit according to claim 1, which is characterized in that first input module includes: the first transistor
And second transistor；
Wherein, the grid of the first transistor is connected to first control terminal, the first end connection of the first transistor
To the first voltage end, the second end of the first transistor is connected to first pull-up node, the second transistor
Grid be connected to second control terminal, the first end of the second transistor is connected to the second voltage end, described
The second end of two-transistor is connected to first pull-up node.
3. scanning circuit according to claim 1, which is characterized in that second input module includes: the tenth transistor
With the 11st transistor；
Wherein, the grid of the tenth transistor is connected to the third control terminal, the first end connection of the tenth transistor
To the first voltage end, the second end of the tenth transistor is connected to second pull-up node, the 11st crystal
The grid of pipe is connected to the 4th control terminal, and the first end of the 11st transistor is connected to the second voltage end, institute
The second end for stating the 11st transistor is connected to second pull-up node.
4. scanning circuit according to claim 1, which is characterized in that the first pull-up control module includes: third crystalline substance
Body pipe and the 4th transistor；
Wherein, the grid of the third transistor is connected to first pull-up node, and the first end of the third transistor connects
It is connected to the tertiary voltage end, the second end of the third transistor is connected to first pull-down node, the 4th crystal
The grid of pipe is connected to first pull-up node, and the first end of the 4th transistor is connected to the tertiary voltage end, institute
The second end for stating the 4th transistor is connected to second pull-down node.
5. scanning circuit according to claim 1, which is characterized in that the second pull-up control module includes: the 12nd
Transistor and the 13rd transistor；
Wherein, the grid of the tenth two-transistor is connected to second pull-up node, and the first of the tenth two-transistor
End is connected to the tertiary voltage end, and the second end of the tenth two-transistor is connected to second pull-down node, and described the
The grid of 13 transistors is connected to second pull-up node, and the first end of the 13rd transistor is connected to the third
The second end of voltage end, the 13rd transistor is connected to first pull-down node.
6. scanning circuit according to claim 1, which is characterized in that first pull-down control module includes: the 5th crystalline substance
Body pipe, the 6th transistor and the 7th transistor；
Wherein, the grid of the 5th transistor is connected to first pull-down node, and the first end of the 5th transistor connects
It is connected to the tertiary voltage end, the second end of the 5th transistor is connected to first pull-up node, the 6th crystal
The grid of pipe is connected to first pull-down node, and the first end of the 6th transistor is connected to the tertiary voltage end, institute
The second end for stating the 6th transistor is connected to second pull-up node, and the grid of the 7th transistor is connected to described first
Pull-down node, the first end of the 7th transistor are connected to the tertiary voltage end, and the second end of the 7th transistor connects
It is connected to first output end.
7. scanning circuit according to claim 1, which is characterized in that second pull-down control module includes: the 14th
Transistor, the 15th transistor and the 16th transistor；
Wherein, the grid of the 14th transistor is connected to second pull-down node, and the first of the 14th transistor
End is connected to the tertiary voltage end, and the second end of the 14th transistor is connected to second pull-up node, and described the
The grid of 15 transistors is connected to second pull-down node, and the first end of the 15th transistor is connected to the third
Voltage end, the second end of the 15th transistor are connected to first pull-up node, the grid of the 16th transistor
It is connected to second pull-down node, the first end of the 16th transistor is connected to the tertiary voltage end, and described the
The second end of 16 transistors is connected to the second output terminal.
8. scanning circuit according to claim 1, which is characterized in that first clock control module includes: the 8th crystalline substance
Body pipe；
Wherein, the grid of the 8th transistor is connected to first clock signal terminal, the first end of the 8th transistor
It is connected to the tertiary voltage end, the second end of the 8th transistor is connected to first output end.
9. scanning circuit according to claim 1, which is characterized in that the second clock control module includes: the 17th
Transistor；
Wherein, the grid of the 17th transistor is connected to the third clock signal terminal, and the of the 17th transistor
One end is connected to the tertiary voltage end, and the second end of the 17th transistor is connected to the second output terminal.
10. scanning circuit according to claim 1, which is characterized in that first output module includes: the 9th crystal
Pipe；
Wherein, the grid of the 9th transistor is connected to first pull-up node, and the first end of the 9th transistor connects
It is connected to the second clock signal end, the second end of the 9th transistor is connected to first output end.
11. scanning circuit according to claim 1, which is characterized in that second output module includes: the 18th crystal
Pipe；
Wherein, the grid of the 18th transistor is connected to second pull-up node, and the first of the 18th transistor
End is connected to the third clock signal terminal, and the second end of the 18th transistor is connected to the second output terminal.
12. scanning circuit according to claim 1, which is characterized in that the first pole plate of the first capacitor is connected to institute
State the first output end, the second pole plate of the first capacitor is connected to first pull-up node, and the first of second capacitor
Pole plate is connected to the second clock signal end, and the second pole plate of second capacitor is connected to first pull-down node.
13. scanning circuit according to claim 1, which is characterized in that the first pole plate of the third capacitor is connected to institute
State second output terminal, the second pole plate of the third capacitor is connected to second pull-up node, and the first of the 4th capacitor
Pole plate is connected to the 4th clock signal terminal, and the second pole plate of the 4th capacitor is connected to second pull-down node.
14. scanning circuit according to claim 1, which is characterized in that within the same clock cycle, the second clock letter
The phase of the clock signal at number end, the 4th clock signal terminal, the first clock signal terminal and the output of third clock signal terminal is successively stagnant
Afterwards.
15. scanning circuit according to claim 1, which is characterized in that when being scanned along first direction, the first order
Circuit exports scanning signal prior to the second level sub-circuit；
And when scanning in a second direction, the second level sub-circuit exports the scanning prior to the first order sub-circuit
Signal.
16. a kind of gate driving circuit, which is characterized in that the gate driving circuit includes that N grades of scanning circuits are swept for the first order
Scanning circuit is to N grades of scanning circuits, wherein every level-one scanning circuit is scanning described in claim 1~15 any one
Circuit, N are the integer not less than 2.
17. gate driving circuit according to claim 16, which is characterized in that defining adjacent two-stage scan circuit is i-th
Grade scanning circuit and i+1 grade scanning circuit, i are the positive integer no more than N；
Wherein, the first output end of the i-stage scanning circuit is connected with the first control terminal of the i+1 grade scanning circuit,
First output end of the i+1 grade scanning circuit is connected with the second control terminal of the i-stage scanning circuit；
The second output terminal of the i-stage scanning circuit is connected with the third control terminal of the i+1 grade scanning circuit, and described
The second output terminal of i+1 grades of scanning circuits is connected with the 4th control terminal of the i-stage scanning circuit.
18. gate driving circuit according to claim 16, which is characterized in that the first clock of odd level scanning circuit is believed
Number end is that same signal end, second clock signal end are same signal end, when third clock signal terminal is same signal end, the 4th
Clock signal end is same signal end；And the first clock signal terminal of even level scanning circuit is same signal end, second clock
Signal end is same signal end, third clock signal terminal is same signal end, the 4th clock signal terminal is same signal end.
19. a kind of display device, which is characterized in that the display device includes grid described in claim 16~18 any one
Pole driving circuit.
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| CN106710511A (en) * | 2017-02-24 | 2017-05-24 | 上海天马微电子有限公司 | Single-stage scanning circuit, double-stage scanning circuit, grid driving circuit and display device |
| CN106652883B (en) * | 2017-03-21 | 2020-04-28 | 上海中航光电子有限公司 | Grid driving circuit |
| CN111477181B (en) | 2020-05-22 | 2021-08-27 | 京东方科技集团股份有限公司 | Gate driving circuit, display substrate, display device and gate driving method |
| US12073784B2 (en) * | 2021-05-31 | 2024-08-27 | Boe Technology Group Co., Ltd. | Line drive signal enhancement circuit, shift register unit and display panel |
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| CN105118414A (en) * | 2015-09-17 | 2015-12-02 | 京东方科技集团股份有限公司 | Shift register, driving method thereof, gate driving circuit, and display device |
| CN105528985A (en) * | 2016-02-03 | 2016-04-27 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
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| CN105895047A (en) * | 2016-06-24 | 2016-08-24 | 京东方科技集团股份有限公司 | Shift register unit, gate drive device, display device and control method |
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| CN105528985A (en) * | 2016-02-03 | 2016-04-27 | 京东方科技集团股份有限公司 | Shift register unit, driving method and display device |
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