CN205789043U

CN205789043U - A kind of 6K point-to-point super large resolution splicing volume broadcasts controller

Info

Publication number: CN205789043U
Application number: CN201620579392.6U
Authority: CN
Inventors: 戴志明
Original assignee: Shenzhen Universal Video Technology Co Ltd
Current assignee: Shenzhen Universal Video Technology Co Ltd
Priority date: 2016-06-14
Filing date: 2016-06-14
Publication date: 2016-12-07
Anticipated expiration: 2026-06-14

Abstract

The utility model discloses a kind of 6K point-to-point super large resolution splicing volume and broadcast controller, including main control chip and mosaic screen, main control chip lower surface connects installing plate, main control chip connects video data processing module and clock signal control module and communication interface modules, video data processing module includes Video Decoder and backup of memory, the signal output part of main control chip is also associated with view data and produces circuit, and view data produces circuit and includes phaselocked loop, synchronous generator and DDR buffer；Communication interface modules includes Transistor-Transistor Logic level interface, WiFi communication interface, and WiFi communication interface is provided with wireless transceiver, and the other end of Transistor-Transistor Logic level interface connects the drive end having LED driver, LED driver to be connected to mosaic screen；Main control chip uses field programmable logic device；Clock signal is also associated with external crystal-controlled oscillation；This device uses FPGA mode to control, it is achieved that online upgrading and remotely control, adds the motility of design.

Description

A kind of 6K point-to-point super large resolution splicing volume broadcasts controller

Technical field

This utility model relates to LED screen and controls technical field, is specially a kind of 6K point-to-point super large resolution splicing volume and broadcasts Controller.

Background technology

Mosaic screen, can use separately as display, can be spliced into again jumbotron and use.Need are used according to difference Ask, it is achieved the variable changeable large-size screen monitors function that also can diminish greatly: single screen segmentation shows, single screen individually shows, combination in any shows, entirely Shield splicing liquid crystal display screen liquid crystal-spliced, dual splicing, perpendicular screen display, the optional compensation of framing mask or covering, support digital signal Roaming, scaling stretch, across screen display, the setting of various display prediction schemes and operation, full HD real time signal processing.Although mosaic screen Can be spliced into super large screen easily to use, but be as the increase of mosaic screen number, its broadcast encoder controls more and more multiple Miscellaneous, it is desirable to the data volume of transmission is big, scanning speed is fast, for traditional single-chip microcomputer, owing to internal resource is few, and the speed of service Slowly, it is impossible to meet system requirements.

Utility model content

For problem above, this utility model provides a kind of 6K point-to-point super large resolution splicing volume and broadcasts controller, energy Enough realizing big data to process, processing speed is fast, and design flexibility is high, can effectively solve the problem in background technology.

For achieving the above object, this utility model provides following technical scheme: a kind of 6K point-to-point super large resolution is spliced Volume broadcasts controller, and including main control chip and mosaic screen, described main control chip lower surface connects installing plate, and described main control chip is even Being connected to video data processing module and clock signal control module and communication interface modules, described video data processing module includes Video Decoder and backup of memory, described Video Decoder is connected to the data input pin of main control chip, and backup of memory is even Receiving the data storage outfan of main control chip, described clock signal control module is connected to the URAT interface of main control chip；Institute The signal output part stating main control chip is also associated with view data generation circuit, and described view data produces circuit and includes phase-locked Ring, synchronous generator and DDR buffer；One end of described phaselocked loop is connected with clock signal control module, DDR buffer It is connected to the data-interface of main control chip；Described communication interface modules is connected to the communication interface of main control chip, and described communication connects Mouth die block includes Transistor-Transistor Logic level interface, WiFi communication interface, and the other end of described Transistor-Transistor Logic level interface connects LED driver, LED Driver is connected to the drive end of mosaic screen.

As a kind of preferably technical scheme of this utility model, described main control chip uses field programmable logic device EP2C20 family chip, described LED driver uses JXI5050 driving chip.

As a kind of preferably technical scheme of this utility model, WiFi communication interface is provided with wireless transceiver.

As a kind of preferably technical scheme of this utility model, described clock signal control module uses S-35390 series RTC real-time timepiece chip, and this chip is also associated with the external crystal-controlled oscillation of 32.768KHz.

Compared with prior art, the beneficial effects of the utility model are: Broadcast Control is compiled in the splicing of this 6K point-to-point super large resolution Device processed, by arranging main control chip, uses FPGA controller, utilizes the parallel processing advantage of FPGA controller, substantially increase Data reading speed and processing speed；Clock signal control module and phaselocked loop be set, it is ensured that clock synchronizes, it is to avoid because The video playback that sequence problem causes is abnormal；WiFi communication interface and wireless transceiver are set, it is achieved that wireless data transmission, carry High device motility.

Accompanying drawing explanation

Fig. 1 is this utility model structural representation；

Fig. 2 is this utility model cross-sectional view；

Fig. 3 is LED driver circuit schematic diagram.

In figure: 1-main control chip；2-mosaic screen；3-installing plate；4-video data processing module；5-clock signal controls mould Block；6-communication interface modules；7-backup of memory；8-view data produces circuit；9-phaselocked loop；10-synchronous generator； 11-DDR buffer；12-TTL electric level interface；13-WiFi communication interface；14-LED driver；15-external crystal-controlled oscillation；16-is wireless Transceiver；17-Video Decoder.

Detailed description of the invention

Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is carried out Clearly and completely describe, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole Embodiment.Based on the embodiment in this utility model, those of ordinary skill in the art are not under making creative work premise The every other embodiment obtained, broadly falls into the scope of this utility model protection.

Embodiment:

Referring to Fig. 1 to Fig. 3, this utility model provides a kind of technical scheme: a kind of 6K point-to-point super large resolution is spliced Volume broadcasts controller, and including main control chip 1 and mosaic screen 2, described main control chip 1 lower surface connects installing plate 3, described master control core Sheet 1 connects video data processing module 4 and clock signal control module 5 and communication interface modules 6, and described video data processes Module 4 includes that Video Decoder 17 and backup of memory 7, described Video Decoder 17 are connected to the data input of main control chip 1 End, backup of memory 7 is connected to the data storage outfan of main control chip 1, and described clock signal control module 5 is connected to master control The URAT interface of chip 1；The signal output part of described main control chip 1 is also associated with view data and produces circuit 8, described picture number Phaselocked loop 9, synchronous generator 10 and DDR buffer 11 is included according to producing circuit 8；One end of described phaselocked loop 9 and clock Signal control module 5 is connected, and DDR buffer 11 is connected to the data-interface of main control chip 1；Described communication interface modules 6 connects To the communication interface of main control chip 1, described communication interface modules 6 includes Transistor-Transistor Logic level interface 12, WiFi communication interface 13, described The other end of Transistor-Transistor Logic level interface 12 connects has LED driver 14, LED driver 14 to be connected to the drive end of mosaic screen 2；Described Main control chip 1 uses field programmable logic device EP2C20 family chip, described LED driver 14 to use JXI5050 to drive Chip；Described WiFi communication interface 13 is provided with wireless transceiver 16；Described clock signal control module 5 uses S-35390 system The RTC real-time timepiece chip of row, and this chip is also associated with the external crystal-controlled oscillation 15 of 32.768KHz.

Operation principle of the present utility model: described main control chip 1 is arranged on the lower section of mosaic screen 2 by installing plate 3, described Main control chip 1 utilizes FPGA controller, is used for realizing clock configuration, data process and LED and drives and control；At described video data The video data of the compressed encoding received is decoded operation, described backup storage by the Video Decoder 17 in reason module 4 The data received are carried out backup storage by device 7；Described clock signal control module 5 produces clock arteries and veins by external crystal-controlled oscillation 15 Punching, and produced scan synchronizing signal by RTC real-time timepiece chip, carry out real time scan, described picture number controlling main control chip 1 According to producing circuit 8 for producing the signal of telecommunication to show the data image received on mosaic screen 2, described phaselocked loop 9 is for real Existing Phase synchronization operation, the clock frequency of synchronous generator 10 will keep consistent with clock signal control module 5, thus Ensure correct read-write sequence；Described DDR buffer 11 is for buffered video data, it is achieved same clock rising edge and under Fall is along all reading data, thus improves data read rates；Synchronous generator 10 is produced by described Transistor-Transistor Logic level interface 12 The signal of telecommunication is input to LED driver 14, lights mosaic screen 2 by LED driver 14, and described WiFi communication interface 13 is connected to nothing Line transceiver 16, by wireless transceiver 16 by local data signal with radio wave by the way of according to set channel be sent to far Journey computer.

This 6K point-to-point super large resolution splicing volume broadcasts controller, by arranging main control chip 1, uses FPGA controller, Utilize the parallel processing advantage of FPGA controller, substantially increase data reading speed and processing speed；Clock signal control is set Molding block 5 and phaselocked loop 9, it is ensured that clock synchronizes, it is to avoid because the video playback that sequence problem causes is abnormal；WiFi is set Communication interface 13 and wireless transceiver 16, it is achieved that wireless data transmission, improve device motility, also save into simultaneously This.

The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all at this Any amendment, equivalent and the improvement etc. made within the spirit of utility model and principle, should be included in this utility model Protection domain within.

Claims

1. 6K point-to-point super large resolution splicing volume broadcasts a controller, including main control chip (1) and mosaic screen (2), described master Control chip (1) lower surface connects installing plate (3), it is characterised in that: described main control chip (1) connects has video data to process mould Block (4) and clock signal control module (5) and communication interface modules (6), described video data processing module (4) includes video solution Code device (17) and backup of memory (7), described Video Decoder (17) is connected to the data input pin of main control chip (1), backup Memorizer (7) is connected to the data storage outfan of main control chip (1), and described clock signal control module (5) is connected to master control The URAT interface of chip (1)；The signal output part of described main control chip (1) is also associated with view data and produces circuit (8), described View data produces circuit (8) and includes phaselocked loop (9), synchronous generator (10) and DDR buffer (11)；Described phaselocked loop (9) one end is connected with clock signal control module (5), and DDR buffer (11) is connected to the data-interface of main control chip (1)； Described communication interface modules (6) is connected to the communication interface of main control chip (1), and described communication interface modules (6) includes Transistor-Transistor Logic level Interface (12), WiFi communication interface (13), the other end of described Transistor-Transistor Logic level interface (12) connects LED driver (14), LED Driver (14) is connected to the drive end of mosaic screen (2).

A kind of 6K point-to-point super large resolution splicing volume the most according to claim 1 broadcasts controller, it is characterised in that: described Main control chip (1) uses field programmable logic device EP2C20 family chip, and described LED driver (14) uses JXI5050 Driving chip.

A kind of 6K point-to-point super large resolution splicing volume the most according to claim 1 broadcasts controller, it is characterised in that: described WiFi communication interface (13) is provided with wireless transceiver (16).

A kind of 6K point-to-point super large resolution splicing volume the most according to claim 1 broadcasts controller, it is characterised in that: described Clock signal control module (5) uses the RTC real-time timepiece chip of S-35390 series, and this chip is also associated with 32.768KHz External crystal-controlled oscillation (15).