CN205752144U - There is the semiconductor packages of multilayer film electrically-conductive backing plate and structure - Google Patents

There is the semiconductor packages of multilayer film electrically-conductive backing plate and structure Download PDF

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Publication number
CN205752144U
CN205752144U CN201620469646.9U CN201620469646U CN205752144U CN 205752144 U CN205752144 U CN 205752144U CN 201620469646 U CN201620469646 U CN 201620469646U CN 205752144 U CN205752144 U CN 205752144U
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conductive
encapsulant
conductive structure
conductive pattern
pillar
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CN201620469646.9U
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Inventor
班文贝
元秋亨
郑季洋
金本吉
金即俊
李钟炫
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Imark Technology Co
Amkor Technology Inc
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Imark Technology Co
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Abstract

There is the semiconductor packages of multilayer film electrically-conductive backing plate and structure.A kind of semiconductor packages includes one first conductive structure.One first encapsulant is encapsulated at least part of of this first conductive structure, and the other parts of this first conductive structure are exposed in this first encapsulant.One second conductive structure is arranged on this first encapsulant, and is electrically coupled to this first conductive structure.One second encapsulant is encapsulated a Part I of this second conductive structure, and a Part II of this second conductive structure is exposed in this second encapsulant.One first semiconductor grain is electrically coupled to this second conductive structure.

Description

There is the semiconductor packages of multilayer film electrically-conductive backing plate and structure
Technical field
The U.S. patent application case that subject application is advocated to be submitted on April 19th, 2016 in USPO preferential Power, its Reference Number is 15/133,081, invention entitled " in order to manufacture the semiconductor package with multilayer film electrically-conductive backing plate and structure The method of dress ", and the priority of the korean patent application case submitted on May 22nd, 2015 in Korean Intellectual Property Office, Its Reference Number is 10-2015-0071718, and the ownership equity acquired in above-mentioned patent application case its according to 35U.S.C. § 119, The most by reference its content intact is incorporated to.
This utility model is usually about electronic circuit, and is more particularly about semiconductor packages and structure thereof.
Background technology
According to recently for miniaturization and the high performance demand of electronic installation, researched and developed various processing procedure with In providing high performance semiconductor packages.There is provided high performance semiconductor packages a kind of processing procedure be increase a memory chip Capacity, it is, reach the memory chip of high long-pending body.Reaching of the memory chip of Gao Jitiization can be by brilliant at semiconductor The confined space of grain is filled many unit as much as possible.
But, the memory chip of high long-pending body needs the technology of high complexity, and including seems that needs are reached accurate, fine Line width and develop for a long time.Alternatively, it has been suggested that the stacking of a kind of semiconductor grain, to provide high The semiconductor module of capacity.Also been proposed the technology manufacturing an encapsulation with a wafer scale, be formed multiple on the wafer Several semiconductor grains.In addition to needing costly and complicated manufacturing technology, each in these technology all lacks at electricity Motility in the redesign of road pattern.
Accordingly, it would be desirable to have the structure forming encapsulation semiconductor device that can solve previously described and other problems And method.Also want to these structures and methods and can be readily incorporated into manufacturing process, and there is cost benefit.
Utility model content
Narration of the present utility model includes, particularly following characteristics, a kind of multilayer film electrically-conductive backing plate or multilayer film guidance Electricity structure includes being encapsulated or moulding conductive interconnecting structure of at least two-layer.In certain embodiments, a support plate is attached to this multilamellar One surface of molding conductive structure is using as a temporary support structure.In other embodiments, this support plate can be configured to one Heat sink or heat spreader structures.Electronic component, such as semiconductor device and/or passive component, can be attached to this multilayer film Conductive structure processed, it includes the attachment in recess portions.Upper conductive pattern layer in this multilamellar support plate and/or attachment structure Can redesign in manufacturing processing procedure, to allow elastic, time-consuming and cost-benefit manufacturing capacity.
More particularly, in one embodiment, a kind of semiconductor packages, including: multilayer film conductive structure, its bag Include: the first conductive structure；First encapsulant, it is encapsulated at least part of of this first conductive structure, wherein this first conductive structure Other parts be exposed in this first encapsulant；Second conductive structure, it is arranged on this first encapsulant, and electrically coupling Close this first conductive structure；With the second encapsulant, it is encapsulated the Part I of this second conductive structure, wherein this second conduction The Part II of structure is exposed in this second encapsulant, and the Part III of wherein this second conductive structure is exposed to setting In reception space in this second encapsulant；And first semiconductor grain, it is electrically coupled to this second conductive structure and exists This Part III in this reception space.
Wherein, farther including: conductive projection, it is attached to this Part II of this second conductive structure；Electronic installation, It is electrically coupled to this first conductive structure；And the 3rd encapsulant, it is encapsulated this electronic installation.
Wherein: this first conductive structure includes: the first conductive pattern；With the first conductive pillar, its be electrically coupled to this One conductive pattern；This first conductive pattern and this first conductive pillar are encapsulated with this first encapsulant；This first conductive structure A part is exposed in this first encapsulant；And this second conductive structure includes: the second conductive pattern, it is electrically coupled to this First conductive structure；With the second conductive pillar, it is electrically coupled to a part for the second conductive pattern.In another embodiment In, a kind of semiconductor packages, including: the first conductive structure；First encapsulant, it is encapsulated at least portion of this first conductive structure Point, during wherein the other parts of this first conductive structure are exposed to this first encapsulant；Second conductive structure, its be arranged on this On one encapsulant, and it is electrically coupled to this first conductive structure；And second encapsulant, it is encapsulated this second conductive structure Part I, during wherein the Part II of this second conductive structure is exposed to this second encapsulant；And first semiconductor grain, It is electrically coupled to this second conductive structure.
Wherein, farther include: receiving space, it is arranged in this second encapsulant, wherein: this second conductive structure Part III is exposed in this reception space；And this first semiconductor grain system is directly connected to this second conductive structure at this Receive this Part III in space.
Wherein, farther including: electronic installation, it is electrically coupled to this first conductive structure；And the 3rd encapsulant, its It is encapsulated this electronic installation.
Wherein: this first conductive structure includes: the first conductive pattern, it is on the first surface of support plate；With the first conduction Pillar, it is electrically coupled to this first conductive pattern；This second conductive structure includes: the second conductive pattern, and it is connected electrically to This first conductive structure；With the second conductive pillar, it is electrically coupled to a part for the second conductive pattern；And this semiconductor package Dress farther includes conducting carrier plate, and it is coupled to this first encapsulant being opposite on the side of this second conductive structure.
In a further embodiment, a kind of semiconductor packages, including: the first conductive pattern；First conductive pillar, its electricity Gas is connected to this first conductive pattern；First encapsulant, it is encapsulated this first conductive pattern and this first conductive pillar；Second leads Electrical pattern, its this first conductive pillar being connected electrically to be exposed to the outside of this first encapsulant；Second conductive pillar, its electricity Gas is connected to a part for this second conductive pattern；Second encapsulant, it is encapsulated the Part I of this second conductive pattern and is somebody's turn to do A part for second conductive pillar；Receiving space, it is arranged in this second encapsulant, to expose this second conductive pattern extremely Few Part II；And first semiconductor grain, it is placed on this reception space, and is connected electrically to this second conductive pattern This Part II.
Wherein: this first semiconductor grain is directly connected to this second conductive pattern in this reception space；And should Semiconductor packages farther includes at least one conductive projection, and what it was coupled to this second conductive pillar is exposed to this second encapsulant The part of outside.
Wherein, farther include: the one in the second semiconductor grain and passive component or more person, it is placed with electricity Gas is coupled to this first conductive pattern, wherein: in this first semiconductor grain and this second semiconductor grain and this passive component This one or more person be positioned on the counter surface of this first encapsulant.
Having the beneficial effect that of technique scheme of the present utility model:
In such scheme, described semiconductor packages is capable of high long-pending body and the purpose of motility, and production technology Simply.
Accompanying drawing explanation
Above and other feature of this specification, by graphic with reference to enclose, carry out details by exemplary embodiment and retouches State, and become more to understand, wherein:
Fig. 1 to Figure 11 is fragmentary cross-sectional view, and it sequentially manufactures half exemplified with according to an embodiment of the present utility model The method of conductor encapsulation；
Figure 12 is fragmentary cross-sectional view, it illustrates the semiconductor packages according to another embodiment of the present utility model；
Figure 13 is fragmentary cross-sectional view, it illustrates the semiconductor packages according to still another embodiment of the present utility model；
Figure 14 is fragmentary cross-sectional view, it illustrates the semiconductor packages according to still another embodiment of the present utility model； And
Figure 15 is fragmentary cross-sectional view, it illustrates the semiconductor packages according to still another embodiment of the present utility model.
In order to simplify and clearly demonstrate, the assembly in figure is not drawn necessarily to scale, and in different drawings, identical Element numbers represent identical assembly.Furthermore it is known that step and the description of assembly and details omitted in the hope of describing Simplify.Term used herein " and/or " include the combination in any of one or more relevant listed project and all combinations. Additionally, the purpose of term used herein is only for describing specific embodiment, it is no intended to limit this announcement.Made herein Singulative be also intended to include plural form, unless the context clearly indicates otherwise.Should further be appreciated that term " Including and/or comprise ", when using in this manual, be to specify stated feature, numeral, step, operation, group Part and/or the existence of component rather than in order to get rid of one or more further feature, numeral, step, operation, assembly, component, And/or the increase of combinations thereof or existence.Although it should be understood that term " first, second ... etc. " can be used in this article retouching State various parts, assembly, region, layer and/or block, but these components, assembly, region, layer and/or block should not be restricted by The restriction of these terms.These terms are only used for component, assembly, region, floor and/or block and other component, assembly, district Territory, layer and/or block make differentiation.So that it takes up a position, for example, a first component, one first assembly, a first area, one first Layer and/or one first block discussed below can be referred to as a second component, one second assembly, a second area, one second Layer and/or one second block, the teaching disclosed without deviating from this.With reference to " embodiment " or " embodiment " mean with This embodiment relevant described special characteristic, structure or characteristic are included at least one embodiment of the present utility model. Therefore, " in one embodiment " or the different occasions that occurred in this specification of the word of " in one embodiment " differ Establish a capital and refer to identical embodiment, but in some cases, it may be true.Additionally, in one or more embodiments, specific spy Levy, structure or characteristic can be combined in any suitable manner, and its personage having usual knowledge for this area will be Obviously.It addition, term " when ... when " refer at least at least part of generation of persistent period of the action started Some actions.The use of word " about " or " about " physically refers to, the expection of the value of assembly will close to a state value or Position.But, as in the art it is well known that always have difference slightly so that value or position are old with institute The value stated difference.Except as otherwise noted, used herein " on " or " top " term include orientation, position or close System, wherein specified assembly can direct or indirect material contact.Should further be appreciated that illustrated below and describe this A little embodiments can have embodiment and/or can be practiced by under lacking the assembly not had specific announcement herein.
Detailed description of the invention
Referring to figs. 1 to Figure 11, a kind of method for manufacturing semiconductor packages according to first embodiment and one make The semiconductor packages 1000 manufactured by the method will be described.Fig. 1 to Figure 11 exemplified with one according to first embodiment Manufacture the fragmentary cross-sectional view of the method for semiconductor packages.
First, as it is shown in figure 1, one first conductive pattern 110 is formed on a first surface 11 of a support plate 10.Here, This support plate 10 including this first surface 11 farther includes to be opposite to the second surface 12 of this first surface 11.An enforcement In example, the scope of the thickness that this support plate 10 is had is from about 3 microns to 300 microns.In certain embodiments, this support plate 10 can With by the one in metal, silicon, glass, epoxy resin or the other materials of dawn as known to art technology personage or more person Formed.At least this first surface 11 is ready for and cleans, and is used for receiving this first conductive pattern 110.
In one embodiment, this first conductive pattern 110 can be made of an electrically conducting material, including copper (Cu), gold (Au), Silver (Ag), aluminum (Al) or other material of dawn as known to art technology personage.It addition, this first conductive pattern 110 can be by Physical vapour deposition (PVD) (PVD), chemical gaseous phase deposit (CVD), metal sputtering, metal evaporation, electrolysis or electroless-plating or such as ability Other formation technology that field technique personage is known is formed.In one embodiment, this first conductive pattern 110 is had The scope of thickness is from about 3 microns to 50 microns.After deposition, this conductive material can be by physical etch or chemistry erosion Carve, or other technology of dawn patterns as known to art technology personage.In other embodiments, a screen layer is (not Diagram) can be first deposited upon on this first major surfaces (first surface) 11, and deposit this conductive material subsequently.Formed After this conductive pattern, this screen layer is removable or can not remove, and depends on that it is applied.
Then, with reference to Fig. 2, it is connected electrically to one or more first conductive pillar 120 quilts of this first conductive pattern 110 Formed.This first conductive pillar 120 is formed to extend outwardly away from the first surface of this first conductive pattern 110 and this support plate 10 11, or stretch out from the first surface 11 of this first conductive pattern 110 and this support plate 10.In one embodiment, this One conductive pillar 120 preferably to have good conduction, the material of heat conduction is formed, as copper (Cu), copper alloy or its be similar to Thing, but the shape of this first conductive pillar 120 and material are not the most limited by content disclosed herein.An enforcement In example, the scope of the thickness that this first conductive pillar 120 is had is from about 30 microns to 300 microns.Additionally, this first conduction Pillar 120 can use PVD, CVD, metal sputtering, metal evaporation, electrolysis or electroless-plating or as known to art technology personage Other formation technology of dawn is formed.In one embodiment, electrolysis or electroless deposition technique collocation use a screen layer, this screen Cover layer to be arranged at above this first major surfaces 11, and there is a preselected pattern, for formed in desired position this One conductive pillar 120.In one embodiment, this first conductive pillar 120 has the width different from this first conductive pattern 110 Degree.In one embodiment, one first conductive structure 121 can include this first conductive pattern 110 and this first conductive pillar 120 and/or extra conductive structure in one or more person.
Then, reference Fig. 3, the top section of the first surface 11 of this support plate 10, that is, this first conductive pattern 110 He The outer surface of each of this first conductive pillar 120 is encapsulated by one first encapsulant 130 or the first molding encapsulant.
In one embodiment, this first encapsulant 130 be encapsulated completely and cover this first conductive pattern 110 and this first Conductive pillar 120, to protect this first conductive pattern 110 and this first conductive pillar 120 so that it is will not be seemed that outside rushes The infringement hit or aoxidize.In one embodiment, this first encapsulant 130 is formed with than this first conductive pillar 120 Higher thickness.In other embodiments, this first encapsulant can be formed with remotely the flushing of this first conductive pillar 120. Here, this first encapsulant 130 can be polymer composites, such as, seem for performing to be encapsulated through molding processing procedure Epoxy molding compounds, the liquid being used for performing to be encapsulated through an allotter are encapsulated component or its above-mentioned analog, but The aspect of the present embodiment is not limited to this.
Then, with reference to Fig. 4, one is used to remove processing procedure to remove the part of this first encapsulant 130.An embodiment In, use a grinding processing procedure to remove the material of a predetermined thickness on a surface of this first encapsulant 130 so that this is first years old Conductive pillar 120 is exposed to the outside of this first encapsulant 130.Here, grind can use seem a diamond abrasive machine or its Equivalent performs, but aspect of the present utility model is not limited to this.In other embodiments, shielding and etching technique, Yi Jiyan Mill technology or combinations thereof may be used for removing the part of this first encapsulant 130.In one embodiment, the structure of Fig. 4 can Being referred to as molding support plate sub-assembly 100 or a first molding support plate 100, it includes this support plate 10, this first conductive pattern 110, one Individual or more this first conductive pillar 120 and this first encapsulant 130.In most embodiments, this molding support plate Assembly 100 includes the first one or more conductive pillar 120 being exposed to the outside of this first encapsulant 130, as generally As shown in Figure 4.In one embodiment, this molding support plate sub-assembly 100 can be pre-fabricated and it is anticipated that design Revise and be embodied in one second conductive pattern 140 and one second conductive pillar 150, as described below.According to this enforcement Example, this provides the design flexibility of enhancing, and saves manufacturing cost and cycle time.
Then, with reference to Fig. 5, it is connected electrically to this first conductive pillar 120 and is exposed to the outside of this first encapsulant 130 On the second conductive pattern 140 be formed.Here, know as known to art technology personage, this second conductive pattern 140 is permissible It is made of an electrically conducting material, including copper (Cu), gold (Au), silver (Ag), aluminum (Al) or other material.It addition, this second conductive pattern 140 can be by physical vapour deposition (PVD) (PVD), chemical gaseous phase deposition (CVD), metal sputtering, metal evaporation, electrolysis or electric without electricity Plating or other formation technology of dawn as known to art technology personage are formed.In one embodiment, this second conductive pattern The scope of 140 thickness being had is from about 3 microns to 50 microns.Select the conduction material on this second conductive pattern 140 It can be same or different for expecting and select the conductive material on this first conductive pattern 110.
According to present embodiment, owing to this second conductive pattern 140 can have different from this first conductive pattern 110 Pattern, such as, position and vpg connection, can be according to one first semiconductor grain or other electric members that will be described later Or electronic installation and redesign easily or revise circuit pattern.
Then, with reference to Fig. 6, it is connected electrically to one or more second conductive pillar 150 quilts of this second conductive pattern 140 Formed.Here, this second conductive pillar 150 can be selectively connected to a part for this second conductive pattern 140.This is second years old Conductive pillar 150 is formed extend upwardly away from from this second conductive pattern 140 or stretch out, and preferably with good Good conduction, the material of heat conductivity are made, such as copper (Cu), copper alloy or its analog, but the shape of this second conductive pillar 150 Shape and material are not limited in the disclosure herein.In one embodiment, the thickness that this second conductive pillar 150 is had Scope from about 30 microns to 300 microns.Additionally, this second conductive pillar 150 can be by physical vapour deposition (PVD) (PVD), change Learn vapour deposition (CVD), metal sputtering, metal evaporation, electrolysis or electroless-plating or know as known to art technology personage its Its formation technology is formed.In one embodiment, electrolysis or electroless deposition technique collocation use a screen layer, and this screen layer sets Be placed in the surface of this first encapsulant 130, and there is a preselected pattern, for formed in desired position this second Conductive pillar 150.In one embodiment, this second conductive pillar 150 has the width different from this second conductive pattern 140 Degree, and can have the width different from this first conductive pillar 120 and shape further.In one embodiment, one Two conductive structures 221 can include in this second conductive pattern 140 and this second conductive pillar 150 and/or other conductive structure One or more.
Then, with reference to Fig. 7, the top section of this first encapsulant 130, it is, this second conductive pattern 140 and this The outer surface of each of two conductive pillars 150 is encapsulated by one second encapsulant 160.In one embodiment, this Two encapsulants 160 farther include a reception space 161, and it is formed to prevent this second conductive pillar 150 from not connecting Remaining area to this second conductive pattern 140 avoids tunica dress.This reception space 161 can use tone screen or its equivalence Thing is formed, but aspect of the present utility model is not limited to this.In other embodiments, this reception space 161 can this Two encapsulants 160 are just formed after being formed.In other embodiments, the sidewall of the conductive pattern 140 in this reception space 161 Part can be encapsulated by this second encapsulant 160 or other insulant or cover.In one embodiment, this reception space 161 sidewalls being configured with inclination the most as shown in Figure 7, in order to more preferably promote to manufacture and avoid at this second capsule The wedge angle of envelope agent 160.
This second encapsulant 160 is encapsulated and covers the one of this second conductive pattern 140 and this second conductive pillar 150 completely Part, to protect this second conductive pattern 140 and this second conductive pillar 150 so that its will not be seemed external impact or The infringement of oxidation.In one embodiment, this second encapsulant 160 is formed with higher than this second conductive pillar 150 Thickness.Or, this second encapsulant can be formed with remotely the flushing of this second conductive pillar 150.In certain embodiments, This second encapsulant 160 can be polymer composites, such as, seem for performing, through molding processing procedure, the epoxy being encapsulated Mold compound, it is encapsulated component or its above-mentioned analog for the liquid that performs to be encapsulated through an allotter, but this reality The aspect executing example is not limited to this.This second encapsulant 160 can be the material identical from this first encapsulant 130 or different materials Material.According to the present embodiment, this first encapsulant 130 and this second encapsulant 160 are different and separate material areas.
Then, with reference to Fig. 8, use one to remove processing procedure and remove the part of this second encapsulant 160.In one embodiment, Use a grinding processing procedure to remove the material of a predetermined thickness on a surface of this second encapsulant 160 so that this second is led Electricity pillar 150 is exposed to the outside of this second encapsulant 160.In one embodiment, it is possible to use seem a diamond abrasive machine Or its equivalent performs grinding, but aspect of the present utility model is not limited to this.In other embodiments, shield and etch skill Art, and grinding technique or combinations thereof may be used for removing the part of this second encapsulant 160.In an alternate embodiment In, this reception space 161 can be formed after the part of this second encapsulant is removed.In one embodiment, Fig. 8 Structure can be described as multilayer film conductive structure 201, multilayer film electrically-conductive backing plate 201, molding carrying board structure 201 or the second mould Support plate 201 processed, it includes this molding support plate sub-assembly 100, this second conductive pattern 140, one or more second conductive pillars 150 and there is second encapsulant 160 in one or more reception space 161.In most embodiments, this multilamellar molding Conductive structure 201 includes these one or more second conductive pillars being exposed to the outside of this second encapsulant 160.Real at other Executing in example, multilayer film conductive structure 202 or multilayer film electrically-conductive backing plate 202 include this first conductive pattern 110, this first capsule Envelope agent 130, this second conductive pattern 140, one or more second conductive pillar 150, and there is no this second capsule of support plate 10 Envelope agent 160.
Then, it is placed at this reception space 161, to be connected electrically to reference to Fig. 9 mono-first semiconductor module 200 The remainder of this second conductive pattern 140, and this first semiconductor module 200 is not encapsulated by this second encapsulant 160.? In some embodiments, this first semiconductor module 200 includes one first semiconductor grain 210,1 first joint sheet 220,1 One conductive projection 230 and one first underfilling 240.This first semiconductor grain 210 has a basal surface, and electrical connection This first joint sheet 220 to an active layers (not shown) is exposed to this basal surface.In one embodiment, this first joint sheet 220 include a conductive material, a layer or more layers of such as aluminum, copper, stannum, nickel, gold silver or other suitable conductive material.
This first conductive projection 230 is electrically and to connect this first joint sheet 220 and through a backflow system in the way of entity Journey is to connect this second conductive pattern 140, and this first conductive projection 230 is made up of one or more conductive materials, such as, Lead/stannum (Pb/Sn) or without lead-in wire stannum and analog or other suitable conductive material.In one embodiment, this first is led Electricity projection 230 can be a solder projection, copper pillar, solder ball or ball-type projection.In one embodiment, this first bottom Filler 240 fill or be configured at a surface of this first encapsulant 130 and this first semiconductor grain 210 basal surface it Between, carry out curing process subsequently.
According to the present embodiment, this first underfilling 240 protects the projection bonding part will not be by the shadow of external factor Ring, seem produced mechanical shock or corrosion during manufacturing semiconductor packages.Here, this first underfilling 240 Can be polymeric material, seem epoxy resin, thermoplastic, thermosets, polyimides, polyurethane, polymeric material Material, the epoxy resin filled, the thermoplastic of filling, the thermosets of filling, the polyimides of filling, the poly-ammonia of filling Ester, filling polymeric material in, in the underfilling fluxed or the other materials of dawn as known to art technology personage one Person or more person.In one embodiment, this first semiconductor grain 210 has major surfaces (such as, with the first conductive projection 230 opposed surfaces), it is identical with the outer surface of this second encapsulant 160 that this major surfaces is positioned essentially at (such as, horizontal plane) Plane on.In other embodiments, the major surfaces of this first semiconductor grain 210 is positioned at and this second encapsulant 160 In the plane (such as, horizontal plane) that outer surface is different.
Then, with reference to Figure 10 and Figure 11, according to another embodiment of this utility model, this semiconductor packages 1000 is by attachment One or more conductive projections 20 are to be connected electrically to be exposed to (multiple) second conduction of the outside of this second encapsulant 160 Post 150 and make.In one embodiment, this conductive projection 20 can be made up of metal material, such as lead/stannum (Pb/Sn) or Without lead-in wire stannum and analog or as known to art technology personage know other suitable conductive material.In one embodiment, This conductive projection 20 can be a solder projection, copper pillar, solder ball or ball-type projection.According to the present embodiment, this semiconductor die The outside major surfaces of grain 210 is in different planes from the long-range of this conductive projection 20 or surface, in order at this quasiconductor Encapsulation 1000 is attached to now, it is provided that assembly (e.g. a, printing of this first semiconductor grain 210 and next level (level) Circuit board) between gap.In one embodiment, this support plate 10 is separated, to provide semiconductor packages as shown in figure 11 1000, its first conductive pattern 110 is externally exposed, for function or the heat radiation of further interconnection, hereinafter can describe into The embodiment of one step.
Figure 12 is the fragmentary cross-sectional view illustrating semiconductor encapsulation 2000 according to another embodiment.An embodiment In, a radiator 13 or a heat sink 13 are attached to the top section of this first encapsulant 130.In one embodiment, this dissipates Hot plate 13 can also be attached to this first encapsulant 130 dividually.In a preferred embodiment, this support plate 10 is configured to The insulating barrier 14 being inserted between this support plate 10 and this first encapsulant layers 130 is used (such as, to lead including one as heat sink 13 Hot material).In certain embodiments, this heat sink 13 preferably carrys out shape having the metal of high heat conductance and low thermal coefficient of expansion Become.But, owing to this heat sink 13 is directly connected to the first conductive pattern 110 of exposure, an insulating barrier 14 is inserted in this heat radiation Between plate 13 and this first conductive pattern 110, to prevent from occurring electrically between this heat sink 13 and this first conductive pattern 110 Short circuit.In certain embodiments, this heat sink 13 can be formed by the material with high heat conductance, such as silicon, glass or, ring Epoxy resins, and a metal and/or ceramic powders be formed in this heat sink 13.
Figure 13 is the fragmentary cross-sectional view illustrating semiconductor encapsulation 3000 according to further embodiment.An enforcement In example, after this support plate 10 separates with this first encapsulant 130, one second semiconductor module 300 is placed to be connected electrically to At the first conductive pattern 110 of the top office of this first encapsulant 130, and the appearance of this second semiconductor module 300 Face is that the 3rd encapsulant 30 by the top office at this first encapsulant 130 is encapsulated.
In one embodiment, this second semiconductor module 300 includes that one second semiconductor grain 310,1 second engages Pad 320,1 second conductive projection 330 and one second underfilling (not shown).This second semiconductor grain 310 has an end Surface, and the second joint sheet 320 being connected electrically to active layers (not shown) is exposed to this basal surface.In one embodiment, This second joint sheet 320 includes a conductive material, a layer of such as aluminum, copper, stannum, nickel, gold silver or other suitable conductive material Or more layers.
This second conductive projection 330 is electrically and to connect this second joint sheet 320 and through a backflow system in the way of entity Journey is to connect this first conductive pattern 110, and this second conductive projection 330 is made up of one or more conductive materials, such as, Lead/stannum (Pb/Sn) or without lead-in wire stannum and analog or other suitable conductive material.In one embodiment, this second is led Electricity projection 330 can be a solder projection, copper pillar, solder ball or ball-type projection.3rd encapsulant 30 can be with previously The identical material of the first described encapsulant 130 is formed.In other embodiments, the 3rd encapsulant 30 can be formed, To expose this second semiconductor module 300 or this second semiconductor grain 310 to outside, to make the feelings with or without heat sink The heat leakage of improvement is provided under condition.
Figure 14 is the fragmentary cross-sectional view illustrating semiconductor encapsulation 4000 according to still further embodiments.A reality Executing in example, after this support plate 10 separates with this first encapsulant 130, a passive component 400 is placed to be connected electrically at this First conductive pattern 110 of the top office of the first encapsulant 130, and be attached and signal can be exchanged.Additionally, this quilt The outer surface of dynamic assembly 400 is that the 3rd encapsulant 30 by the top office at this first encapsulant 130 is encapsulated.? In one embodiment, this passive component 400 is formed as a resistor, an inducer or a capacitor.3rd encapsulant 30 Can be formed with the identical material with the first previously described encapsulant 130.
Figure 15 is the fragmentary cross-sectional view illustrating semiconductor encapsulation 5000 according to another embodiment.An embodiment In, after this support plate 10 separates with this first encapsulant 130, this second semiconductor module 300 and this passive component 400 are placed To be connected electrically to the first conductive pattern 110 in the top office of this first encapsulant 130, and it is attached and can hand over Change signal.Additionally, the outer surface of this second semiconductor module 300 and this passive component 400 is by this first encapsulant 130 The 3rd encapsulant 30 of top office be encapsulated.In one embodiment, this second semiconductor module 300 is passive with this Assembly 400 is as being above relevant to described by Figure 13 and Figure 14.3rd encapsulant 30 can be encapsulated with previously described first The identical material of agent 130 is formed.In alternative embodiments, the 3rd encapsulant 30 can be formed, with expose this second half The surface of semiconductor die 310, as previously mentioned.
Knowable to above-mentioned all, according to another embodiment, those skilled in the art scholar can determine that, one is used for The method manufacturing semiconductor packages, it includes forming one first conductive pattern on a first surface of a support plate；Form one One conductive pillar, it is electrically connected to this first conductive pattern；It is encapsulated this first conduction first by one first encapsulant Pattern and this first conductive pillar；Forming one second conductive pattern, it is electrically connected to this first conductive pillar, and this first is led Electricity pillar is exposed to the outside of this first encapsulant；Forming one second conductive pillar, it is electrically connected to this second conductive pattern A part for case；Secondly one second encapsulant is used to be encapsulated the part of this second conductive pattern and this second conductive pillar, and And one receive space, the remainder of this second conductive pattern is exposed to this reception space；And place one first quasiconductor Crystal grain is connected electrically to be exposed to this second conductive pattern of the outside of this second encapsulant in this reception space.
Knowable to above-mentioned all, according to further embodiment, those skilled in the art scholar can determine that, Yi Zhongban Conductor encapsulates, comprising: one first conductive pattern；One first conductive pillar, it is electrically connected to this first conductive pattern；One First encapsulant, it is encapsulated this first conductive pattern and this first conductive pillar；One second conductive pattern, it is electrically connected to It is exposed to this first conductive pillar of the outside of this first encapsulant；One second conductive pillar, its be electrically connected to this second The part of conductive pattern；One second encapsulant, its formation one reception space, the remainder of this second conductive pattern is exposed to This reception space, this second encapsulant is encapsulated the part of this second conductive pattern and this second conductive pillar；And one first Semiconductor grain, its this second conductive pattern being electrically connected to be exposed to the outside of this second encapsulant, and be placed In this reception space.
Knowable to above-mentioned all, according to the further embodiment of approach described herein, those skilled in the art Scholar can determine that, this first semiconductor grain of electrical couplings includes: directly this first semiconductor grain is connected to second and leads Electricity structure Part III in this reception space.In still further embodiments, this first semiconductor grain of electrical couplings Can include that electrical couplings has this first semiconductor grain of a major surfaces, this major surfaces is positioned essentially at and this second capsule In the identical plane of one outer surface of envelope agent.In another embodiment, it is provided that this multilayer film conductive structure comprises the steps that and carries For comprising one or the support plate of more person of metal, silicon, glass or epoxy resin.In a further embodiment, it is provided that these are many Layer molding conductive structure comprises the steps that offer includes a metal and has this support plate of an insulating barrier, and this insulating barrier is arranged on this load Between this first surface and this first conductive structure of plate.
Knowable to above-mentioned all, according to the further embodiment of structures described herein, those skilled in the art Scholar can determine that, this semiconductor packages can farther include conductive projection, and it is attached to second of this second conductive structure Point.
Knowable to above-mentioned all, according to the further embodiment of structures described herein, those skilled in the art Scholar can determine that, a heat sink, and it can be configured in the top being opposite to this first semiconductor grain of this first encapsulant Near surface.
In view of described above, it is obvious that have revealed that a kind of multilamellar molding using and having resilient designed capacity Conductive structure manufactures method and the structure of semiconductor encapsulation.It includes, particularly, one first conductive structure and one second is led Electricity structure, this first conductive structure is encapsulated by one first molding encapsulant, and this second conductive structure is arranged on this first molding On encapsulant and be connected electrically to this first conductive structure.This second conductive structure contributes to this base plate for packaging interconnection structure Elastic design variation or redesign.This second molding encapsulant is encapsulated at least part of of this second conductive structure, and an electricity Sub-device is connected electrically to this second conductive pattern.In certain embodiments, one or more extra electronic installations can be electric It is connected to this first conductive pattern.In other embodiments, a heat sink can be attached to this semiconductor packages.
Although being particularly shown exemplary embodiment of the present utility model and being described, those skilled in the art scholar can To be appreciated that, can for carry out in its form and details various change without deviating from spirit and scope of the present utility model before Putting, spirit and scope of the present utility model is as defined by following claims.
As claims reflect, characteristic of the present utility model may be in the institute than single embodiment disclosed above There is feature the fewest.Therefore, the claims stated below are expressly incorporated in the detailed description of accompanying drawing, each right at this Requirement itself is as an independent embodiment of the present utility model.Although additionally, some of the embodiments described herein is included in Some features in other embodiments but be not the feature of other embodiments, the combination of the feature of different embodiments is wished to fall at this In the category of utility model, it is desirable to form those skilled in the art scholar and can be appreciated by different embodiments.

Claims (10)

1. a semiconductor packages, it is characterised in that including:
Multilayer film conductive structure, comprising:
First conductive structure；
First encapsulant, it is encapsulated at least part of of this first conductive structure, and wherein the other parts of this first conductive structure are sudden and violent It is exposed in this first encapsulant；
Second conductive structure, it is arranged on this first encapsulant, and is electrically coupled to this first conductive structure；With
Second encapsulant, it is encapsulated the Part I of this second conductive structure, and wherein the Part II of this second conductive structure is sudden and violent It is exposed in this second encapsulant, and wherein the Part III of this second conductive structure is exposed to and is arranged in this second encapsulant Reception space in；And
First semiconductor grain, it is electrically coupled to this second conductive structure this Part III in this reception space.
2. semiconductor packages as claimed in claim 1, it is characterised in that farther include:
Conductive projection, it is attached to this Part II of this second conductive structure；
Electronic installation, it is electrically coupled to this first conductive structure；And
3rd encapsulant, it is encapsulated this electronic installation.
3. semiconductor packages as claimed in claim 1, it is characterised in that:
This first conductive structure includes:
First conductive pattern；With
First conductive pillar, it is electrically coupled to this first conductive pattern；
This first conductive pattern and this first conductive pillar are encapsulated with this first encapsulant；
A part for this first conductive structure is exposed in this first encapsulant；And
This second conductive structure includes:
Second conductive pattern, it is electrically coupled to this first conductive structure；With
Second conductive pillar, it is electrically coupled to a part for the second conductive pattern.
4. a semiconductor packages, it is characterised in that including:
First conductive structure；
First encapsulant, it is encapsulated at least part of of this first conductive structure, and wherein the other parts of this first conductive structure are sudden and violent It is exposed in this first encapsulant；
Second conductive structure, it is arranged on this first encapsulant, and is electrically coupled to this first conductive structure；And
Second encapsulant, it is encapsulated the Part I of this second conductive structure, and wherein the Part II of this second conductive structure is sudden and violent It is exposed in this second encapsulant；And
First semiconductor grain, it is electrically coupled to this second conductive structure.
5. semiconductor packages as claimed in claim 4, it is characterised in that farther include:
Receiving space, it is arranged in this second encapsulant, wherein:
The Part III of this second conductive structure is exposed in this reception space；And
This first semiconductor grain system is directly connected to this second conductive structure this Part III in this reception space.
6. semiconductor packages as claimed in claim 4, it is characterised in that farther include:
Electronic installation, it is electrically coupled to this first conductive structure；And
3rd encapsulant, it is encapsulated this electronic installation.
7. semiconductor packages as claimed in claim 4, it is characterised in that:
This first conductive structure includes:
First conductive pattern, it is on the first surface of support plate；With
First conductive pillar, it is electrically coupled to this first conductive pattern；
This second conductive structure includes:
Second conductive pattern, it is connected electrically to this first conductive structure；With
Second conductive pillar, it is electrically coupled to a part for the second conductive pattern；And
This semiconductor packages farther includes conducting carrier plate, its be coupled to be opposite on the side of this second conductive structure this One encapsulant.
8. a semiconductor packages, it is characterised in that including:
First conductive pattern；
First conductive pillar, it is connected electrically to this first conductive pattern；
First encapsulant, it is encapsulated this first conductive pattern and this first conductive pillar；
Second conductive pattern, its this first conductive pillar being connected electrically to be exposed to the outside of this first encapsulant；
Second conductive pillar, it is connected electrically to a part for this second conductive pattern；
Second encapsulant, its Part I being encapsulated this second conductive pattern and a part for this second conductive pillar；
Receiving space, it is arranged in this second encapsulant, to expose at least Part II of this second conductive pattern；And
First semiconductor grain, it is placed on this reception space, and is connected electrically to this Part II of this second conductive pattern.
9. semiconductor packages as claimed in claim 8, it is characterised in that:
This first semiconductor grain is directly connected to this second conductive pattern in this reception space；And
This semiconductor packages farther includes at least one conductive projection, its be coupled to this second conductive pillar be exposed to this second A part for the outside of encapsulant.
10. semiconductor packages as claimed in claim 8, it is characterised in that farther include:
One in second semiconductor grain and passive component or more person, it is placed to be electrically coupled to this first conductive pattern Case, wherein:
This first semiconductor grain is positioned over this with this one in this second semiconductor grain and this passive component or more person On the counter surface of the first encapsulant.
CN201620469646.9U 2015-05-22 2016-05-20 There is the semiconductor packages of multilayer film electrically-conductive backing plate and structure Active CN205752144U (en)

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KR1020150071718A KR101651362B1 (en) 2015-05-22 2015-05-22 Method for fabricating semiconductor package and semiconductor package using the same
US15/133,081 US10177117B2 (en) 2015-05-22 2016-04-19 Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure
US15/133,081 2016-04-19

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US10177117B2 (en) 2019-01-08
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CN106169445A (en) 2016-11-30
US20160343688A1 (en) 2016-11-24
TW201709477A (en) 2017-03-01
TWI702709B (en) 2020-08-21

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