CN206505907U - Semiconductor packages - Google Patents
Semiconductor packages Download PDFInfo
- Publication number
- CN206505907U CN206505907U CN201720098027.8U CN201720098027U CN206505907U CN 206505907 U CN206505907 U CN 206505907U CN 201720098027 U CN201720098027 U CN 201720098027U CN 206505907 U CN206505907 U CN 206505907U
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- Prior art keywords
- conductive
- conductive pattern
- substrate
- semiconductor device
- dielectric layer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 112
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000008393 encapsulating agent Substances 0.000 claims abstract description 35
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000004020 conductor Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 14
- 239000000945 filler Substances 0.000 description 31
- 239000013078 crystal Substances 0.000 description 25
- 238000000034 method Methods 0.000 description 21
- 230000015572 biosynthetic process Effects 0.000 description 14
- 239000010949 copper Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 13
- 238000007747 plating Methods 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 238000002161 passivation Methods 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 8
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000011049 filling Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 239000003822 epoxy resin Substances 0.000 description 5
- 238000009434 installation Methods 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 4
- 238000000465 moulding Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 229920000642 polymer Polymers 0.000 description 4
- 238000007639 printing Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920002577 polybenzoxazole Polymers 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 3
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 description 2
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 101001031591 Mus musculus Heart- and neural crest derivatives-expressed protein 2 Proteins 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
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- 238000005516 engineering process Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 229920001568 phenolic resin Polymers 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229920003192 poly(bis maleimide) Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004541 SiN Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000004026 adhesive bonding Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 150000003851 azoles Chemical class 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000004069 differentiation Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000000608 laser ablation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000012778 molding material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920006389 polyphenyl polymer Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- KCTAWXVAICEBSD-UHFFFAOYSA-N prop-2-enoyloxy prop-2-eneperoxoate Chemical compound C=CC(=O)OOOC(=O)C=C KCTAWXVAICEBSD-UHFFFAOYSA-N 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005245 sintering Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002562 thickening agent Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The utility model provides a kind of semiconductor packages, and it includes:Substrate, it includes：Dielectric layer；First conductive pattern, it is at least partially embedded at the lower surface of the dielectric layer in the dielectric layer；Second conductive pattern, it is located on the top surface of the dielectric layer；Conductive through hole, to electrically connect first conductive pattern and second conductive pattern；And conductive pole, it is downwardly projected from the lower surface of first conductive pattern；At least one semiconductor device, it is arranged in one or more of the top surface of the substrate and lower surface；And encapsulant, it is over the substrate to be completely covered at least one described semiconductor device.The semiconductor packages that the utility model is provided is for ensuring that the space for installing semiconductor device, and it is by etching Temporary Met plate to form multiple conductive poles.
Description
Technical field
Some embodiments of the present utility model are related to a kind of semiconductor packages.
Background technology
With the miniaturization to the electronic product in current semicon industry and high performance increased demand, study
And have been developed for for providing the various technologies that large-capacity semiconductor is encapsulated.It is many in order to provide large-capacity semiconductor encapsulation
Passive and/or activation element is integrated or is stacked on limited substrate, is derived from highly integrated semiconductor packages.
Of the present utility model one illustrated by relatively more such system and such as in the remainder of the application referring to schema
A little aspects, the further limitation of conventional and conventional method and inferior position will become apparent to those skilled in the art.
Utility model content
The utility model provides a kind of semiconductor packages, and it includes：Substrate, it includes：Dielectric layer；First conductive pattern,
It is at least partially embedded at the lower surface of the dielectric layer in the dielectric layer；Second conductive pattern, it is located at described
On the top surface of dielectric layer；Conductive through hole, to electrically connect first conductive pattern and second conductive pattern；And lead
Electric post, it is downwardly projected from the lower surface of first conductive pattern；At least one semiconductor device, it is arranged on the lining
On one or more of the top surface and lower surface at bottom；And encapsulant, it is over the substrate to be completely covered
State at least one semiconductor device.
In described semiconductor packages, at least one described semiconductor device includes：First semiconductor device, it is arranged on
To be electrically connected to second conductive pattern on the top surface of the substrate；And second semiconductor device, it is installed
To be electrically connected to first conductive pattern in the lower surface of the substrate.
In described semiconductor packages, second semiconductor device is in the lower surface corresponding to the dielectric layer
The substrate the lower surface central area in be electrically connected to first conductive pattern, and the conductive pole exists
Corresponding to being electrically connected to institute in the outer peripheral areas of the lower surface of the substrate of the lower surface of the dielectric layer
State the first conductive pattern.
In described semiconductor packages, the encapsulant includes：First encapsulant, to cover first semiconductor device
With the top surface of the substrate；And second encapsulant, to cover second semiconductor device and the substrate
The lower surface that the lower surface leaves the conductive pole simultaneously is externally exposed.
Described semiconductor packages includes being electrically connected to multiple conductive projections of the lower surface of the conductive pole.
The semiconductor packages that the utility model is provided can be by being formed on interim (or virtual) metallic plate by etching
Multiple conductive poles ensure the space for installing semiconductor device.
The utility model, which also provides a kind of semiconductor packages, can reduce cost and the processing time for manufacturing conductive pole.
Brief description of the drawings
Fig. 1 is the sectional view for illustrating the semiconductor packages according to embodiment of the present utility model；
Fig. 2 is the flow chart for illustrating to manufacture the case method of semiconductor packages illustrated in fig. 1；And
Fig. 3 A to 3L are the case methods of formation substrate in the example semiconductor encapsulation making method that explanation is illustrated in Figure 2
Sectional view.
Embodiment
The application quotes the 10-2016-0042986 korean patent applications submitted on April 7th, 2016, advocates described
The priority of korean patent application and the rights and interests for advocating the korean patent application, the content of the korean patent application herein with
The mode introduced in full is incorporated herein.
Various aspects of the present utility model can in many different forms be implemented and be not intended to be limited to institute herein
The example embodiment of elaboration.In fact, it is in order that the utility model will be to provide these example embodiments of the present utility model
Thorough and complete, and various aspects of the present utility model will be passed on to those skilled in the art.
In the drawings, layer and the thickness in region are for the sake of clarity exaggerated.Herein, similar reference numerals are referred to
Similar component.As used herein, term "and/or" include any of one or more of associated Listed Items and
All combinations.In addition, term used herein is not limiting as merely for the sake of the purpose of description specific embodiment
The utility model.As used herein, unless the context clearly, otherwise singulative is also intended to include plural shape
Formula.Will be further understood that, term " comprising ", "comprising" specified when for this specification stated feature, number, step,
Operation, the presence of element and/or component, but it is not excluded that one or more of the other feature, number, step, operation, element,
The presence or addition of component and/or its group.
Although it should be understood that term first, second etc. can be used to describe various parts, element, region, layer herein
And/or section, but these parts, element, region, layer and/or section should not be limited by these terms.These terms are only used
In one part of differentiation, element, region, layer and/or section and another part, element, region, layer and/or section.Therefore, lift
For example, first component, the first element, first area, first layer and/or the first section being discussed herein below are referred to alternatively as second
Part, the second element, second area, the second layer and/or the second section are without departing from teaching of the present utility model.With detailed reference to
Present example of the present utility model, illustrates the example of the embodiment in the accompanying drawings.
According to one side of the present utility model, there is provided a kind of method for manufacturing semiconductor packages.Methods described includes passing through
Etching metal plate formation conductive pole, wherein after the etching, conductive pole may be coupled to the remaining planar section of metallic plate.Fill out
Filling thing can be used subsequently to be filled between conductive pole, and after filling, can remove the remaining planar section of metallic plate,
And semiconductor die may be electrically connected to conductive pole.
According to another aspect of the present utility model, there is provided a kind of method for manufacturing semiconductor packages, wherein methods described bag
Include by etching metal plate to form conductive pole.After the etching, conductive pole may be coupled to the remaining planar portions of metallic plate
Divide, and filler can be used for being filled between conductive pole.After filling, the remaining planar portions of metallic plate can be removed
Point.Subsequent first conductive pattern can be formed on the top surface of filler and on the top surface of conductive pole, its
In one or more of the first conductive pattern may be electrically connected to it is corresponding one or more in conductive pole.
Dielectric layer can be formed as covering filler, conductive pole and the first conductive pattern.Conductive through hole can be formed as prolonging
Extend through dielectric layer and be connected to the first conductive pattern, the second conductive pattern can be formed on the top surface of dielectric layer,
Wherein the second conductive pattern may be electrically connected to conductive through hole.First semiconductor die may be mounted at the top surface of dielectric layer
On, wherein the first semiconductor die is electrically connected at least a portion of the second conductive pattern.Second semiconductor die can be installed
In the lower surface of dielectric layer, wherein the second semiconductor die is electrically connected at least a portion of the first conductive pattern.
Another aspect of the present utility model provides a kind of semiconductor packages, and it includes substrate, and the substrate includes：Dielectric layer；
First conductive pattern, it is at least partially embedded dielectric layer at the lower surface of dielectric layer；Second conductive pattern, it is formed at
On the top surface of dielectric layer；Conductive through hole, it is formed as the first conductive pattern of electrical connection and the second conductive pattern；And it is conductive
Post, it is downwardly projected from the lower surface of the first conductive pattern.At least one semiconductor device may be mounted at the top of substrate
On one or more of surface and/or lower surface, and encapsulant can be formed on substrate that semiconductor is completely covered
Device.
As described above, according in semiconductor packages of the present utility model and its manufacture method, due to multiple conductive poles
It can be formed at by etching on interim (or virtual) metallic plate, may be easy to ensure the space for installing semiconductor device.
In addition, according in semiconductor packages of the present utility model and its manufacture method, can reducing for manufacturing conduction
The cost of post and processing time.
With reference to Fig. 1, the sectional view that explanation is encapsulated according to the example semiconductor of embodiment of the present utility model is shown.
As illustrated in Figure 1, semiconductor packages 100 includes：Substrate 110；One or more semiconductor devices 120 (for example,
First semiconductor device 121, second semiconductor device 122 etc.), it is electrically connected to substrate 110；One or more encapsulant 130
(for example, the first encapsulant 131, second encapsulant 132 etc.), it covers semiconductor device 120；And conductive projection 140, its electricity
It is connected to substrate 110.
Substrate 110 can include dielectric layer 111 and multiple conductive through holes 113, these conductive through holes by or reach dielectric
The top surface 111a and/or lower surface 111b of layer 111.In addition, substrate 110 can further comprise multiple first conductive patterns
112, these first conductive patterns are placed on the lower surface 111b of dielectric layer 111 (for example, being embedded in dielectric layer 111) simultaneously
And it is electrically connected to multiple conductive through holes 113.In addition, substrate 110 may further include the top surface for being placed in dielectric layer 111
111a is upper and is electrically connected to multiple second conductive patterns 114 of multiple conductive through holes 113.Substrate 110 may further include
It is placed on the lower surface 111b of dielectric layer 111 and is electrically connected to the conductive pole 115 of the first conductive pattern 112.Conductive pole
115 can also be electrically connected to conductive through hole 113.Thus, the first semiconductor die 121 and the second semiconductor die 122 can electricity
It is connected to conductive pole 115.
The top surface 110a of substrate 110 can be identical for example with the top surface 111a of dielectric layer 111, and substrate
110 lower surface 110b can be identical for example with the lower surface 111b of dielectric layer 111.
Referring to figs. 2 and 3 A to 3L, there is provided the flow chart of the case method of explanation manufacture Fig. 1 semiconductor packages (100)
And explanation forms the sectional view of the case method of substrate (110) in the case method of Fig. 2 manufacture semiconductor packages.Under
Wen Zhong, will describe the exemplary configuration and case method of the substrate 110 of manufacture semiconductor packages 100 referring to figs. 2 and 3 A to 3L.
As illustrated in figure 2, manufacture semiconductor packages 100 case method include formed substrate (S1), attachment (or peace
Dress) semiconductor device (S2), be encapsulated (S3) and formation conductive projection (S4).In addition, such as illustrated in Fig. 2 and 3A to 3L, substrate
Formation (S1) include formed conductive pole (S11), grinding (S12), formed the first conductive pattern (S13), formed conductive through hole
(S14) the second conductive pattern (S15), is formed, passivation layer (S16) is formed and removes filler (S17).
It is illustrated such as in Fig. 3 A to 3C, in conductive pole (S11) is formed, prepare interim (or virtual) metallic plate of plane
115x and multiple mask patterns 1 are subsequently formed on Temporary Met plate 115x top surface 115xa.Do not covered by the multiple
The Temporary Met plate 115x that mould pattern 1 is covered is removed to desired depth.The Temporary Met plate 115x's covered by mask pattern 1
Region is consequently formed conductive pole 115.Conductive pole 115 can be then accessed when mask pattern 1 is removed.
Accordingly, it is seen that conductive pole 115 can be by removing downwards the Temporary Met not covered by multiple mask patterns 1
Plate 115x expose portion is formed.The removal of Temporary Met plate 115x top surface 115xa expose portion, which can illustrate, to be come
Say via etching into desired depth.Herein, the base section of conductive pole 115 can be by Temporary Met plate 115x remainder
115x' is connected to each other.For example, the conductive pole 115 being spaced apart from each other on remainder 115x' top surface 115xb,
The top surface can for example be original Temporary Met plate 115x plane or plate-like portion.But the He of conductive pole 115
Remainder 115x' is original Temporary Met plate 115x remaining part, and they are discussed as single reality herein
Body.
The width A of each in conductive pole 115 can for example substantially between 200 μm and 450 μm, and
And the lateral separation B between neighbouring conductive pole 115 can be substantially between 90 μm and 500 μm, but this practicality is new
The each side of type is not limited to this.In addition, the height C of each in conductive pole 115 can substantially 60 μm and 100 μm it
Between in the range of, but each side of the present utility model is not limited to this.When increase conductive pole 115 in the width A of each and
During at least one of height C, lateral separation B can also increase.According to the configuration of semiconductor packages 100 and function, conductive pole
The width A of each and height C in 115 can be different such that with one in width A, lateral separation B and height C
It is individual.It should be noted that be etched due to conductive pole 115 (for example, from side etc.), each in conductive pole 115 can have indicate it is such
The style characteristic of etching.For example, due to etching, the side surface of conductive pole 115 can include roughness (or rough texture).
And, for example, due to the metal at first end (or core) place in conductive pole 115 and the second of conductive pole 115
Metal phase ratio at end is exposed to etchant longer time period, so the side surface of conductive pole 115 can be with run-off the straight.Citing
For, conductive pole 115 can have hourglass (or snowman) shape, the shape of truncated cone shape (or frustum), the truncation protruded around center
Shape of spheroid etc..
Because conductive pole 115 is to be formed by etching by Temporary Met plate 115x, thus with by plating or without electricity
Pole plating formation conductive pole 115 can reduce processing cost and time when comparing.Although it should be noted that present only one herein
Step after individual etching, but shelter and/or etching step can be performed a plurality of times, for example, forming staged or multi-level structure.
After conductive pole 115 is formed, (for example, chemical stripping etc.) remaining mask on conductive pole 115 can be removed
Pattern 1.Temporary Met plate 115x can be made up of copper (Cu), but each side of the present utility model is not limited to this.In addition, mask
Pattern 1 can be made up of photoresist, but each side of the present utility model is not limited to this.
Illustrated such as in Fig. 3 D to 3F, in grinding (S12), it is surplus with conductive pole 115 that filler 2 is formed as covering
Remaining part point 115x' etched top surface 115xb, and remainder 115x' is removed.
First, as illustrated in fig. 3d, filler 2 can be formed as covering the etched of remaining Temporary Met plate 115x
Top surface 115xb, and fill the space between conductive pole 115 to allow the top surface 2b of filler 2 to be placed with
High or higher than conductive pole 115 the top surface 115b as the top surface 115b of conductive pole 115.For example, fill
Thing 2 can fill each in conductive pole 115 between space so that the top surface 2b of filler 2 and conductive pole 115
Top surface 115b is equally high or top surface 115b higher than conductive pole 115.Filler 2 can be made up of insulating materials,
For example, for example, photoresist or epoxy resin, but each side of the present utility model is not limited to this.Filler 2 can be with a variety of
Any one of mode formation (for example, rotary coating, injection, dipping, deposition, printing, molding etc.).
As illustrated by Fig. 3 E, after the formation of filler 2, remaining Temporary Met plate 115x and conductive pole 115 are overturn
To allow remaining Temporary Met plate 115x to be placed on conductive pole 115 and filler 2.
After being reversed, as described in Figure 3 F, Temporary Met plate 115x remainder 115x' be removed (for example,
Removed, removed using the injection of fluid and/or gas by mechanical lapping and/or chemical method, using laser
Deng).In addition, when remainder 115x' is removed, the corresponding surface 115a and 2a of conductive pole 115 and filler 2 is exposed to
It is outside.In addition, by removing the surface 115a for the conductive pole 115 that Temporary Met plate 115x is externally exposed and the table of filler 2
Face 2a can be coplanar.Such as diamond lap can for example be used by the removal of remainder 115x' grinding
Machine or its equivalent are performed, but each side of the present utility model is not limited to this.
As illustrated by Fig. 3 G and 3H, in the formation (S13) of the first conductive pattern, first be made of an electrically conducting material is brilliant
The surface 115a of layer 112s covering conductive poles 115 and the surface 2a of filler 2 are planted, and the first conductive pattern 112 passes through plating
It is formed on the first crystal seed layer 112s.
First, as illustrated in fig. 3g, the first crystal seed layer 112s can be formed as leading to cover with uniform thickness
The surface 115a of the electric post 115 and surface 2a of filler 2.First crystal seed layer 112s can include copper, titanium or titanium tungsten, but this practicality
New each side is not limited to this.First crystal seed layer 112s can in many ways (for example, vapour deposition, electrodeless plating etc.)
Any one of formed.
As illustrated in fig. 3h, in order to form the first conductive pattern 112, multiple mask pattern (not shown) can be formed at
Those regions in addition to the region that will form the first conductive pattern 112 are covered on first crystal seed layer 112s region.It is such
Mask pattern can be formed for example using photoresist, but each side of the present utility model is not limited to this.With predetermined thickness
First conductive pattern 112 of degree can be subsequently formed, for example, not be masked the first crystal seed layer of pattern covers by plating
112s region.It should be noted that the first conductive pattern 112 (or conductive layer) can include any one of multiple material (for example,
Copper, aluminium, nickel, iron, silver, gold, titanium, chromium, tungsten, palladium, its combination, its alloy, its equivalent etc.), but scope of the present utility model
Not limited to this.Again, it should be noted that the first conductive pattern 112 (or conductive layer) can utilize any one in a variety of processing or many
Individual formation or deposition are (for example, electrolysis plating, electrodeless plating, chemical vapor deposition (CVD), sputter or physical vapour deposition (PVD)
(PVD), ald (ALD), plasma gas phase deposition, printing, silk-screen printing, photoetching etc.), but it is of the present utility model
Scope not limited to this.
Formed the first conductive pattern 112 after, remove the first crystal seed layer 112s on remaining mask pattern (for example,
Chemical stripping etc.).In addition, after mask pattern is removed, can also remove in the region for not forming the first conductive pattern 112
The first crystal seed layer 112s (for example, by chemical etching etc.) so that the surface 2a of filler 2 to be externally exposed.For example,
First crystal seed layer 112s and the first conductive pattern 112 can be covered and the identical region shown in Fig. 3 H.First conductive pattern
112 can be electrically connected to conductive pole 115 by the first crystal seed layer 112s.In addition, the first crystal seed layer 112s is used for by plating
The reference layer of the first conductive pattern 112 is formed, and for ease of description, description below will allow for the first conductive pattern
112 be to include the first crystal seed layer 112s and the individual layer of the first conductive pattern 112 is made.First conductive pattern 112 can be by copper
(Cu) it is made, but each side of the present utility model is not limited to this.
Fig. 3 I illustrate to form conductive through hole (S14).Dielectric layer 111 can be formed as that the first conductive pattern 112 is completely covered
With the surface 2a of filler 2, the multiple through hole 111h for being externally exposed multiple first conductive patterns 112 can be formed, and
Multiple conductive through holes 113 can be formed as filling through hole 111h.
Dielectric layer 111 is formed as with predetermined thickness that the conductive pattern 112 of filler 2 and first is completely covered.Dielectric layer
111 can be electrically insulated with the first conductive pattern 112 and the first crystal seed layer 112s.First conductive pattern 112 can be arranged such that
Their top surface 112a and side surface 112c is covered by dielectric layer 111.Dielectric layer 111 can by for example prepreg,
One or more of built up film, silicon oxide film, silicon nitride film, mold compound and its equivalent are made, but the utility model
Each side be not limited to this.Dielectric layer can include one or more layers of any one of a variety of dielectric materials, these
Dielectric material for example, Inorganic Dielectric Material (for example, Si3N4, SiO2, SiON, SiN, oxide, nitride, its combination, its etc.
Imitate thing etc.) and/or organic dielectric materials (for example, polymer, polyimides (PI), benzocyclobutene (BCB), polybenzoxazoles
(PBO), Bismaleimide Triazine (BT), molding material, phenolic resin, epoxy resin, silicone, acrylate polymer, its
Combination, its equivalent etc.), but scope of the present utility model is not limited to this.Dielectric layer 111 can be used in a variety of processing
Any one or more formed (for example, rotary coating, spraying coating, printing, sintering, thermal oxide, physical vapour deposition (PVD) (PVD),
Chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), ald (ALD), low pressure chemical phase sink
Product (LPCVD), plasma enhanced chemical vapor deposition (PECVD), plasma gas phase deposition (PVD), thin slice are laminated, steam
Hair etc.), but scope of the present utility model is not limited to this.
Multiple through hole 111h are formed down from the top surface 111a of dielectric layer 111, are made from there through multiple through hole 111h
Multiple first conductive patterns 112 are externally exposed.Multiple conductive through holes 113 are formed as by filling multiple through hole 111h electrical connections
To the first conductive pattern 112.Through hole 111h can be formed (for example, laser ablation, mechanical ablation any one of in many ways
Or drilling, chemical etching etc.).
Multiple conductive through holes 113 can be formed as filling through hole 111h, and method is to electroplate to expose by multiple through hole 111h
In outside multiple first conductive patterns 112.For example, conductive through hole 113 can be formed as by using the first conductive pattern
Case 112 is electroplated to fill through hole 111h as crystal seed layer.In addition, conductive through hole 113 can be by through hole 111h and
Through hole crystal seed layer 113s is formed on the inwall of one conductive pattern 112 and plating formation is carried out on through hole crystal seed layer 113s.Such as
Described above, conductive through hole 113 can use the first conductive pattern 112 as crystal seed layer or with single through hole crystal seed layer
113s is as reference layer for plating, but each side of the present utility model is not limited to this.Through hole crystal seed layer 113s may include
Such as copper, titanium or titanium tungsten, but each side of the present utility model is not limited to this.It should be noted that through hole 111h can in many ways in
Any form (for example, plating, electrodeless plating, printing, gluing etc.).
Fig. 3 J illustrate the formation (S15) of the second conductive pattern.Multiple second conductive patterns 114 are formed at the He of dielectric layer 111
To be electrically connected to conductive through hole 113 on the top surface of conductive through hole 113.
Second conductive pattern 114 can be formed with the identical mode of the first conductive pattern 112.For example, second is conductive
The top surface 111a and conductive through hole of dielectric layer 111 can be completely covered by forming the second crystal seed layer 114s in pattern 114
113 top surface 113a is formed.Mask pattern can be subsequently formed on the second crystal seed layer 114s region, make to be formed second
The region exposure of conductive pattern 114, and electroplated on the second crystal seed layer 114s.Second crystal seed layer 114s, which can illustrate, to be come
Say it is layers of copper, titanium layer or titanium tungsten layer, and the second conductive pattern 114 can include copper, but each side of the present utility model is not
It is limited to this.In addition, the second crystal seed layer 114s can be the reference layer for forming the second conductive pattern 114 by electroplating, and
For ease of description, it is to include the conductions of the second crystal seed layer 114s and second that description, which will allow for the second conductive pattern 114, below
What the individual layer of pattern 114 was made.
Second be formed on the top surface 113a of the top surface 111a of dielectric layer 111 and conductive through hole 113 is conductive
Pattern 114 can be electrically connected to the first conductive pattern 112 by conductive through hole 113.
As illustrated by Fig. 3 K, in the formation (S16) of passivation layer, passivation layer 116 (or dielectric layer) is formed as covering and is situated between
The top surface 111a of electric layer 111 and the second conductive pattern 114.For example, at least one of second conductive pattern 114 can
With exposed to the outside of passivation layer 116.For example, the second conductive pattern 114 can be each via corresponding in passivation layer 116
Opening exposure and/or the single opening that can pass through in passivation layer of multiple second conductive patterns 114 expose.It is externally exposed
Second conductive pattern 114 may be electrically connected to semiconductor device 121, as shown in fig. 1.It should be noted that passivation layer 116 can be by this
Any material described in text on dielectric layer 111 is formed and/or can utilized herein in connection with appointing that dielectric layer 111 is discussed
Where method is formed.
In one embodiment, among multiple second conductive patterns 114, the top surface 110a of substrate 110 center
The second conductive pattern 114 in region can be externally exposed (for example, being open by one or more of passivation layer 116),
And the second conductive pattern 114 in the top surface 110a of substrate 110 outer peripheral areas can be covered by passivation layer 116.
As illustrated in Fig. 3 L, in the removal (S17) of filler, filler 2 is removed with by the bottom table of dielectric layer 111
Face 111b and the first conductive pattern 112 (for example, those parts for the conductive pattern 112 not covered by conductive pole 115) are exposed to
It is outside.Herein, when filler 2 is removed, the side surface 115c of conductive pole 115 can be externally exposed.Thus, in such as Fig. 3 L
Shown, substrate 110 (or one part) can be formed by removing filler 2.For example, substrate 110 can be provided so that
The conductive pole 115 being spaced apart from each other contacts the lower surface 112b of the first conductive pattern 112 and is electrically connected to the first conductive pattern
112 lower surface 112b and it is downwardly projected.
In addition, the first conductive pattern 112 being externally exposed when filler 2 is removed is changed into semiconductor to be electrically connected to
The pattern of device 122.In the first conductive pattern 112, first in the lower surface 110b of substrate 110 central area is conductive
Pattern 112 can be externally exposed, and the first conductive pattern 112 in the lower surface 110b of substrate 110 outer peripheral areas
It may be electrically connected to conductive pole 115.
With reference to Fig. 1 and 3L, in the installation (S2) of semiconductor device, at least one semiconductor device 120 is installed as being electrically connected
The second conductive pattern 114 and/or the first conductive pattern 112 are connected to, these conductive patterns are correspondingly in the top surface of substrate 110
Exposed at 110a or lower surface 110b.For example, one or more semiconductor devices 120 may be mounted at substrate 110
(for example, at least the first semiconductor device 121) to be electrically connected to the second conductive pattern 114 of substrate 110 on top surface 110a,
(for example, at least the second semiconductor device 122) to be electrically connected to substrate 110 on the lower surface 110b of substrate 110
First conductive pattern 112, or both top surface 110a and lower surface 110b installed in substrate 110 on.
For example, in the installation (S2) of semiconductor device, at least one first semiconductor device 121 may be mounted at
On the top surface 110a of substrate 110 be electrically connected to be exposed to substrate 110 top surface 110a the second conductive pattern
114, and at least one second semiconductor device 122 may be mounted on the lower surface 110b of substrate 110 to be electrically connected to
Exposed to the lower surface 110b of substrate 110 the first conductive pattern 112.Second semiconductor device 122 may be mounted at substrate
On 110 lower surface 110b central area and conductive pole 115 can the lower surface 110b of substrate 110 external zones
It is downwardly projected in domain.For example, it can ensure to be enough the second semiconductor by the height C of each in conductive pole 115
Device 122 is arranged on the vertical space on the lower surface 110b of substrate 110.
First semiconductor device 121 can be flip-chip variety semiconductor die and can be for example by miniature
Projection 121a is electrically connected to the second conductive pattern 114 of substrate 110.In addition, the second semiconductor device 122 can be flip-chip
Type semiconductor nude film and the first conductive pattern 112 that substrate 110 can be electrically connected to for example, by miniature projection 122a.It is micro-
Type projection 121a and 122a may include such as conducting sphere, for example, the conductive pole of solder ball, such as copper post and/or with being formed at
The conductive pole of solder caps in copper post.In addition, the semiconductor device 120 including joint sheet can be electrically connected to lining by wire bonding
First conductive pattern 112 or the second conductive pattern 114 at bottom 110.However, the utility model is not intended to limit semiconductor device 120
Annexation disclosure of that in this article between each in conductive pattern 112 and 114.Semiconductor device 120 can
To be for example electrically connected to substrate 110 by extensive reflow processing, hot compression processing and/or laser joining process.In addition, partly leading
Body device 120 may further include the semiconductor device being provided on vertical direction.
Herein, semiconductor device 120 may include the IC chip separated with semiconductor wafer.Semiconductor device 120
It may include such as circuit, for example, CPU (CPU), digital signal processor (DSP), network processing unit, power management
Unit, audio process, radio frequency (RF) circuit, system (SoC) processor, sensor, special integrated electricity on wireless baseband chips
Road (ASIC).In addition, semiconductor device 120 can be the device of such as resistor, capacitor, inductor, connector, but this reality
This is not limited to new each side.In addition, semiconductor device 120 can include other encapsulation with chip, for example,
BGA package, leadframe package etc..
In (S3) is encapsulated, as shown in fig. 1, encapsulant 130 is formed as covering (for example, partly covering, being completely covered
Deng) the top surface 110a and lower surface 110b of substrate 110.In (S3) is encapsulated, the first encapsulant 131 can be formed as covering
The top surface 110a of lid substrate 110 and the first semiconductor device 121, and the second encapsulant 132 can be formed as covering completely
The lower surface 110b of lid substrate 110 and the second semiconductor device 122.When the second encapsulant 132 is formed, conductive pole 115
Lower surface 115b can be externally exposed.
Encapsulant 130 can be formed as on encapsulated semiconductor device 120 and substrate 110 except the bottom of conductive pole 115
All surfaces outside the 115b of surface, thus protect semiconductor device 120 from outside mechanical/electrical/chemical contamination or influence.
It should be noted that encapsulant 130 can also be formed as exposing at least top surface of any one or more in semiconductor device 120.
First encapsulant 131 and the second encapsulant 132 can be formed simultaneously using mould and molding frame, but this practicality
New each side is not limited to this.First encapsulant 131 and/or the second encapsulant 132 can include such as prepreg, accumulation
One or more of film, silicon oxide film, silicon nitride film, mold compound and its equivalent, but each side of the present utility model
It is not limited to this.
In addition, after first semiconductor device 121 is arranged on the top surface 110a of substrate 110 encapsulant 130
First encapsulant 131 can be formed as being completely covered the top surface 110a of the first semiconductor device 121 and substrate 110, and
Second encapsulant 132 can be formed as after the second semiconductor device 122 is arranged on the lower surface 110b of substrate 110
The lower surface 110b of the second semiconductor device of all standing 122 and substrate 110.The installation of semiconductor device 120 and encapsulant 130
Formation may be reversed order perform.
Encapsulant 130 (or encapsulation materials) may include such as polyimides (PI), benzocyclobutane (BCB), polyphenyl and dislike
Azoles (PBO), Bismaleimide Triazine (BT), phenolic resin and epoxy resin, but each side of the present utility model is not limited to
This.For example, encapsulation materials can include it is a variety of be encapsulated or mould any one of material (for example, resin, polymer,
Polymer composites, the polymer with filler, epoxy resin, the epoxy resin with filler, with filler
Epoxy acrylate, silicone resin, its combination, its equivalent etc.).Encapsulant 130 (or encapsulation materials) can in many ways in
Any formed (for example, compression molded, transfer molding, liquid encapsulant molding, vacuum laminated, thickener are printed, film is aided in
Molding etc.).
In the formation (S4) of conductive projection, conductive projection 140 is formed on the lower surface 115b of conductive pole 115 to permit
Perhaps conductive pole 115 is electrically connected to the outside of encapsulant 130.Conductive projection 140 can serve as input and/or output connection for
In the external plates that semiconductor packages 100 is arranged on to electronic installation.Conductive projection 140 can be for example conductive pole, copper
Post, conducting sphere, solder ball or copper ball, but each side of the present utility model is not limited to this.
Because the various aspects of the semiconductor packages 100 manufactured by examples detailed above manufacture method are by the interim gold of etching
Belong to plate 115x to be formed formed by conductive pole 115, so the efficient space that ensure that installation semiconductor device 120, and
Processing cost and time can be reduced compared with the situation that conductive pole 115 is stacked by plating.
In addition, though encapsulant 130 can be described, but various embodiments of the present utility model can be for example optional
Ground is without encapsulant or can also use filler material.For example, whole filler 2 can be removed or be only filled with
A part for thing 2, and after the second semiconductor device 122 is attached to the first conductive pattern 112, the second semiconductor device
122 possibly can not be capped.Or, it can use filler material or encapsulation materials to cover.Accordingly, it is seen that this practicality
New encapsulant 132 can be removed entirely or part is removed, and if removing, then same type can be used
Encapsulation materials or another type of material can be used for covering the second semiconductor device 122 or with different degree be removed
Until untill the volume occupied before filler 2 is removed.Therefore, the embodiment of the second semiconductor device 122 of covering can be with
Seem as shown in fig. 1, to occupy certain part of the volume that is occupied by encapsulant 132, or be shown as being encapsulated thing 132 and account for
According to volume not be filled with anything.
Although the embodiment by reference to some supports describes semiconductor package according to various aspects of the present utility model
Dress and its manufacture method, but those skilled in the art will appreciate that, the utility model is not limited to disclosed specific implementation
Example, but, the utility model will include all embodiments fallen within the scope of the accompanying claims.
Claims (5)
1. a kind of semiconductor packages, it is characterised in that including：
Substrate, it includes：Dielectric layer；First conductive pattern, it is at least partially embedded at the lower surface of the dielectric layer
In the dielectric layer；Second conductive pattern, it is located on the top surface of the dielectric layer；Conductive through hole, it is described to electrically connect
First conductive pattern and second conductive pattern；And conductive pole, it is downward from the lower surface of first conductive pattern
It is prominent；
At least one semiconductor device, it is arranged in one or more of the top surface of the substrate and lower surface；
And
Encapsulant, it is over the substrate to be completely covered at least one described semiconductor device.
2. semiconductor packages according to claim 1, it is characterised in that at least one described semiconductor device includes：The
Semiconductor device, it is arranged on the top surface of the substrate to be electrically connected to second conductive pattern；And
Second semiconductor device, it is arranged in the lower surface of the substrate to be electrically connected to first conductive pattern.
3. semiconductor packages according to claim 2, it is characterised in that second semiconductor device is corresponding to described
Described first is electrically connected in the central area of the lower surface of the substrate of the lower surface of dielectric layer conductive
Pattern, and the conductive pole is in the lower surface of the substrate of the lower surface corresponding to the dielectric layer
First conductive pattern is electrically connected in outer peripheral areas.
4. semiconductor packages according to claim 3, it is characterised in that the encapsulant includes：First encapsulant, to cover
Cover the top surface of first semiconductor device and the substrate；And second encapsulant, to cover described the second half
The lower surface that the lower surface of conductor device and the substrate leaves the conductive pole simultaneously is externally exposed.
5. semiconductor packages according to claim 1, it is characterised in that the bottom table including being electrically connected to the conductive pole
Multiple conductive projections in face.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2016-0042986 | 2016-04-07 | ||
| KR1020160042986A KR101799668B1 (en) | 2016-04-07 | 2016-04-07 | Semiconductor package and manufacturing method thereof |
| US15/297,365 US10020263B2 (en) | 2016-04-07 | 2016-10-19 | Semiconductor package and manufacturing method thereof |
| US15/297,365 | 2016-10-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206505907U true CN206505907U (en) | 2017-09-19 |
Family
ID=59833232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720098027.8U Active CN206505907U (en) | 2016-04-07 | 2017-01-25 | Semiconductor packages |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN206505907U (en) |
-
2017
- 2017-01-25 CN CN201720098027.8U patent/CN206505907U/en active Active
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Effective date of registration: 20240909 Address after: Singapore Patentee after: Anrely Technology Singapore Holdings Pte. Ltd. Country or region after: Singapore Address before: Arizona, USA Patentee before: AMKOR TECHNOLOGY, Inc. Country or region before: U.S.A. |