CN205752133U - The chip architecture of sliver can be rolled easily - Google Patents

The chip architecture of sliver can be rolled easily Download PDF

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Publication number
CN205752133U
CN205752133U CN201620020377.8U CN201620020377U CN205752133U CN 205752133 U CN205752133 U CN 205752133U CN 201620020377 U CN201620020377 U CN 201620020377U CN 205752133 U CN205752133 U CN 205752133U
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CN
China
Prior art keywords
wafer substrate
sliver
chip architecture
rolling device
cutting
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Expired - Fee Related
Application number
CN201620020377.8U
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Chinese (zh)
Inventor
彭工及
萧上智
张靖奇
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Yea Shin Technology Co Ltd
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Yea Shin Technology Co Ltd
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Priority to CN201620020377.8U priority Critical patent/CN205752133U/en
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Publication of CN205752133U publication Critical patent/CN205752133U/en
Expired - Fee Related legal-status Critical Current
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Abstract

This utility model relates to a kind of chip architecture that can roll sliver easily, including a silicon substrate, admixture district containing a boron and a phosphorus, to form a wafer substrate, and some Cutting Roads are formed in the front of wafer substrate, described Cutting Road has several crystal grain districts with etching mode definition, wherein, form a groove respectively with etching mode at the corresponding each Cutting Road in the back side of described wafer substrate, and utilize rolling device to carry out rolling sliver, to form several grainiesses to described wafer substrate with vertical and parallel direction along described groove.

Description

The chip architecture of sliver can be rolled easily
Technical field
This utility model relates to a kind of chip architecture that can roll sliver easily;A kind of can roll sliver and without the chip architecture of cutter cutting splitting.
Background technology
Along with the progress in epoch, for product consumption and the lifting day by day of quality of IC, promote the flourish of electronic industry.And the development evolution of electronic manufacturing technology, under the requirement of IC (IC) wafer " function light, thin, short, little, high ", also the structure packing technique making electronic industry is constantly weeded out the old and bring forth the new, wherein wafer cutting isolation technics is along with the difference of material and thinning, for obtaining high yield and maintaining due productivity effect, thus one of key successful factors of control ability actually quality of cutting splitting mechanism.
The making of general diode be first from single-chip as the substrate of growth, recycle various epitaxy flop-in methods and make epitaxy sheet, and cut epitaxy sheet after these epitaxy sheets are carried out platform etching, finally epitaxy sheet is cut into single crystal grain again, and cutting splitting always quasiconductor or the very important processing procedure of photoelectricity industry of crystal grain, after complicated processing procedure gone through by crystal grain, if being unable to maintain that high yield or because die separation method affects the original characteristic of crystal grain in the stage of crystal grain cutting, the production of whole crystal grain can will be caused the most serious impact.
But, now in crystal grain cutting processing procedure, wafer cutting tool typically can be utilized to cleave, to separate crystal grain, but, due to when wafer imposes glass coating because of cannot controlled quentity controlled variable the most accurately, drop down onto bottom Cutting Road so having caused portions of light resistance glass to draw, during as carried out cutter cutting, can be because switching to draw the light resistance glass dropped down onto bottom Cutting Road, and easily cause very much the damage of cutter, burst apart with crystal edge, or it is discontinuous to produce fracture, the problem such as burr or peeling conditions, especially when the blade of cutter is passivated, rupture it would be possible to cause the cut surface of wafer to produce and damage (as shown in Figure 5), even production line must all stop and change cutting tool, and cause the least production cost allowance.Therefore, how to be effectively improved drawbacks described above, be the problem place to be solved for dealer.
Utility model content
The chip architecture that can roll sliver easily described in the utility model, including: a silicon substrate, containing a boron admixture district and a phosphorus admixture district, to form a wafer substrate, and some Cutting Roads are formed in the front of wafer substrate, described Cutting Road has several crystal grain districts with etching mode definition, wherein, form a groove respectively with etching mode at the corresponding each Cutting Road in the back side of described wafer substrate, and utilize rolling device to carry out rolling sliver, to form several grainiesses to described wafer substrate with vertical and parallel direction along described groove.
A kind of chip architecture that can roll sliver easily that this utility model is proposed, wherein, this etching mode is a wet etching or an electric paste etching.
A kind of chip architecture that can roll sliver easily that this utility model is proposed, wherein, this boron admixture district is formed at this wafer substrate front.
A kind of chip architecture that can roll sliver easily that this utility model is proposed, wherein, this phosphorus admixture district is formed at this wafer substrate back side.
A kind of chip architecture that can roll sliver easily that this utility model is proposed, wherein, this rolling device is the full-automatic rolling device of a manual rolling device, half automatic rolling device or.
A kind of chip architecture that can roll sliver easily that this utility model is proposed, wherein, the groove at this wafer substrate back side is a groined type.
Therefore, a kind of chip architecture that can roll sliver easily provided by the utility model, it is to utilize the corresponding each Cutting Road in the back side of wafer substrate to sentence etching mode to form a groove respectively, further along described groove with wafer substrate described in vertical and parallel rolling mode sliver, to form several grainiesses, i.e. can reach the purpose separating crystal grain, and the mode that this utility model uses rolling divides crystal grain, and non-used cutter cutting crystal grain, so the problems such as tool damage will not be had.
In addition, after this utility model is because form a groove respectively with etching mode again at the corresponding each Cutting Road in the back side of wafer substrate, the only remaining thickness than originally few about 1/2 of wafer substrate structure, now utilize rolling sliver, because of material characteristic relation, crystal grain i.e. can start fracture along with wafer substrate thinnest part groove, and this rolling fracture only can cause crystal edge damage slightly, have no effect on yield, crystal edge is caused to burst apart when therefore can be effectively improved the cutting of known cutter, or it is discontinuous to produce fracture, the problem such as burr or peeling conditions, therefore can effectively promote crystal grain yield.
Accompanying drawing explanation
Fig. 1 is the generalized section of wafer substrate of the present utility model;
Fig. 2 is vertical and horizontal Cutting Road schematic diagram of the present utility model;
Fig. 3 is the schematic diagram that this utility model Manual rolling device carries out sliver to wafer substrate;
Fig. 4 is the horizontal and vertical groove schematic diagram that this utility model forms some in the wafer substrate back side;
Fig. 5 is that existing cutter cutting crystal edge bursts apart schematic diagram.
Description of reference numerals:
Wafer substrate 1
Silicon substrate 11
Boron admixture district 12
Phosphorus admixture district 13
Cutting Road 14
Groove 15
Light resistance glass 16
Crystal grain 2.
Detailed description of the invention
Due to the open a kind of coated diode chip structure of this utility model, the making relative theory of its diode epitaxy sheet can understand for correlative technology field technical staff, therefore with following description, no longer makees complete description.Meanwhile, graphic with hereinafter compareed, it is to express the structural representation relevant with this utility model feature, the most also need not completely draw according to actual size.
nullPlease be with reference to shown in Fig. 1 and Fig. 2,For according to a preferred embodiment of the present utility model,This chip architecture includes: a silicon substrate 11,The admixture district 12 that a boron (P) is contained in front is formed with epitaxy flop-in method,And the back side contains the admixture district 13 of a phosphorus (N+),To form a wafer substrate 1,And some the horizontal resection roads being substantially parallel to each other 14 and some perpendicular cuts roads 14 (as shown in Figure 2) the most parallel to each other are formed in the front of wafer substrate 1,Then with etching mode,Such as wet etching (wet etch) or electric paste etching (plasma etch) mode,Cutting Road 14 definition is made to have several crystal grain districts 2,And of the present utility model be improved by: at the corresponding each Cutting Road 14 in the back side of described wafer substrate 1, form a groove 15 respectively with etching mode such as wet etching (wet etch) or electric paste etching (plasma etch) mode again,Deng wafer substrate 1 impose light resistance glass 16 coating with protection PN contact after,Utilize Manual rolling device 3, with vertical and parallel direction, described wafer substrate 1 is carried out sliver then along described groove 15,To form several crystal grain 2 structures,As shown in Figure 3.In the present embodiment, rolling device is not limited with Manual rolling device 3, and it also such as can carry out sliver with semi-automatic rolling device or full-automatic rolling device according to different needed for actual processing procedure, here, only with a most preferred embodiment performance.
The thing being worth mentioning, described groove 15 is to be formed at corresponding wafer substrate 1 front each horizontal and vertical Cutting Road 14, therefore, described groove 15 also forms some the horizontal channels being substantially parallel to each other 15 and some vertical trench 15 the most parallel to each other in wafer substrate 1 back side, and in a groined type (as shown in Figure 4).
Owing to this utility model uses the mode of rolling to divide crystal grain 2, and non-used cutter cutting crystal grain, so the problems such as tool damage will not be had.In addition, after this utility model is because form a groove 15 respectively with etching mode again at the corresponding each Cutting Road 14 in the back side of wafer substrate 1, the only remaining thickness than originally few about 1/2 of wafer substrate 1 structure, now utilize rolling sliver, because of material characteristic relation, crystal grain 2 i.e. can start fracture along with wafer substrate 1 thinnest part groove 15, and this rolling fracture only can cause crystal edge damage slightly, have no effect on yield, crystal edge is caused to burst apart when therefore can be effectively improved the cutting of known cutter, or it is discontinuous to produce fracture, the problem such as burr or peeling conditions, therefore can effectively promote crystal grain 2 yield.
Embodiment described above is only the preferred embodiment lifted by absolutely proving this utility model, and protection domain of the present utility model is not limited to this.The equivalent that those skilled in the art are made on the basis of this utility model substitutes or conversion, all within protection domain of the present utility model.Protection domain of the present utility model is as the criterion with claims.

Claims (5)

1. the chip architecture that can roll sliver easily, including: a silicon substrate, containing a boron admixture district and a phosphorus admixture district, to form a wafer substrate, and some Cutting Roads are formed in the front of wafer substrate, this Cutting Road has several crystal grain districts with etching mode definition, it is characterized in that: at corresponding respectively this Cutting Road in the back side of this wafer substrate, be respectively provided with a groove formed with etching mode, and along this groove, form several and utilize a rolling device to carry out rolling the grainiess that sliver shapes to this wafer substrate with vertical and parallel direction.
The chip architecture of sliver can be rolled the most as claimed in claim 1 easily, it is characterised in that wherein this boron admixture district is formed at this wafer substrate front.
The chip architecture of sliver can be rolled the most as claimed in claim 1 easily, it is characterised in that wherein this phosphorus admixture district is formed at this wafer substrate back side.
The chip architecture of sliver can be rolled the most as claimed in claim 1 easily, it is characterised in that wherein this rolling device is the full-automatic rolling device of a manual rolling device, half automatic rolling device or.
The chip architecture of sliver can be rolled the most as claimed in claim 1 easily, it is characterised in that wherein the groove at this wafer substrate back side is a groined type.
CN201620020377.8U 2016-01-11 2016-01-11 The chip architecture of sliver can be rolled easily Expired - Fee Related CN205752133U (en)

Priority Applications (1)

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Application Number Priority Date Filing Date Title
CN201620020377.8U CN205752133U (en) 2016-01-11 2016-01-11 The chip architecture of sliver can be rolled easily

Publications (1)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107188111A (en) * 2017-05-27 2017-09-22 龙微科技无锡有限公司 The splinter method of MEMS sensor wafer, MEMS sensor wafer
CN108328570A (en) * 2018-01-31 2018-07-27 北京航天控制仪器研究所 A kind of MEMS chip splinter method and supporting tool with film back cavity structure
CN111470471A (en) * 2019-01-23 2020-07-31 上海新微技术研发中心有限公司 Substrate cutting method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107188111A (en) * 2017-05-27 2017-09-22 龙微科技无锡有限公司 The splinter method of MEMS sensor wafer, MEMS sensor wafer
CN108328570A (en) * 2018-01-31 2018-07-27 北京航天控制仪器研究所 A kind of MEMS chip splinter method and supporting tool with film back cavity structure
CN111470471A (en) * 2019-01-23 2020-07-31 上海新微技术研发中心有限公司 Substrate cutting method

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20161130

Termination date: 20210111

CF01 Termination of patent right due to non-payment of annual fee